Patents by Inventor Satoshi Toriumi
Satoshi Toriumi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Publication number: 20160172382Abstract: An object of the present invention is to prevent the deterioration of a TFT (thin film transistor). The deterioration of the TFT by a BT test is prevented by forming a silicon oxide nitride film between the semiconductor layer of the TFT and a substrate, wherein the silicon oxide nitride film ranges from 0.3 to 1.6 in a ratio of the concentration of N to the concentration of Si.Type: ApplicationFiled: November 18, 2015Publication date: June 16, 2016Applicant: Semiconductor Energy Laboratory Co., Ltd.Inventors: Masahiko Hayakawa, Mitsunori Sakama, Satoshi Toriumi
-
Publication number: 20160056179Abstract: A semiconductor device includes a first layer, a second layer over the first layer, and a third layer over the second layer. The first layer includes a first transistor. The third layer includes a second transistor. A channel formation region of the first transistor includes a single crystal semiconductor. A channel formation region of the second transistor includes an oxide semiconductor. The second layer includes a first insulating film, a second insulating film, and a conductive film. The conductive film has a function of electrically connecting the first transistor and the second transistor. The first insulating film is over and in contact with the conductive film. The second insulating film is provided over the first insulating film. The second insulating film includes a region with a carbon concentration of greater than or equal to 1.77×1017 atoms/cm3 and less than or equal to 1.0×1018 atoms/cm3.Type: ApplicationFiled: August 12, 2015Publication date: February 25, 2016Inventors: Satoshi TORIUMI, Yoshikazu HIURA, Mai SUGIKAWA
-
Patent number: 9196632Abstract: An object of the present invention is to prevent the deterioration of a TFT (thin film transistor). The deterioration of the TFT by a BT test is prevented by forming a silicon oxide nitride film between the semiconductor layer of the TFT and a substrate, wherein the silicon oxide nitride film ranges from 0.3 to 1.6 in a ratio of the concentration of N to the concentration of Si.Type: GrantFiled: December 13, 2013Date of Patent: November 24, 2015Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Masahiko Hayakawa, Mitsunori Sakama, Satoshi Toriumi
-
Patent number: 9111775Abstract: Provided is a silicon structure with a three-dimensionally complex shape. Further provided is a simple and easy method for manufacturing the silicon structure with the use of a phenomenon in which an ordered pattern is formed spontaneously to form a nano-structure. Plasma treatment under hydrogen atmosphere is performed on an amorphous silicon layer and the following processes are performed at the same time: a reaction process for growing microcrystalline silicon on a surface of the silicon layer and a reaction process for etching the amorphous silicon layer which is exposed, so that a nano-structure including an upper structure in a microcrystalline state and a lower structure in an amorphous state, over the silicon layer is formed; accordingly, a silicon structure with a three-dimensionally complex shape can be provided.Type: GrantFiled: January 24, 2012Date of Patent: August 18, 2015Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventor: Satoshi Toriumi
-
Publication number: 20150179810Abstract: A change in electrical characteristics is suppressed and reliability in a semiconductor device using a transistor including an oxide semiconductor is improved. The semiconductor device includes an oxide semiconductor film over an insulating surface, an antioxidant film over the insulating surface and the oxide semiconductor film, a pair of electrodes in contact with the antioxidant film, a gate insulating film over the pair of electrodes, and a gate electrode which is over the gate insulating film and overlaps with the oxide semiconductor film. In the antioxidant film, a width of a region overlapping with the pair of electrodes is longer than a width of a region not overlapping with the pair of electrodes.Type: ApplicationFiled: December 18, 2014Publication date: June 25, 2015Inventors: Shunpei Yamazaki, Akihisa Shimomura, Yasumasa Yamane, Yuhei Sato, Tetsuhiro Tanaka, Masashi Tsubuku, Toshihiko Takeuchi, Ryo Tokumaru, Mitsuhiro Ichijo, Satoshi Toriumi, Takashi Ohtsuki, Toshiya Endo
-
Patent number: 9054206Abstract: After a gate insulating film is formed over a gate electrode, in order to improve the quality of a microcrystalline semiconductor film which is formed in an early stage of deposition, a film near an interface with the gate insulating film is formed under a first deposition condition in which a deposition rate is low but the quality of a film to be formed is high, and then, a film is further deposited under a second deposition condition in which a deposition rate is high. Then, a buffer layer is formed to be in contact with the microcrystalline semiconductor film. Further, plasma treatment with a rare gas such as argon or hydrogen plasma treatment is performed before formation of the film under the first deposition condition for removing adsorbed water on a substrate.Type: GrantFiled: August 1, 2008Date of Patent: June 9, 2015Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Shunpei Yamazaki, Sachiaki Teduka, Satoshi Toriumi, Makoto Foruno, Yasuhiro Jinbo, Koji Dairiki, Hideaki Kuwabara
-
Patent number: 9044793Abstract: A method for cleaning a hot-wall type film formation apparatus having a batch processing system with industrially high mass productivity is provided. In the method, a carbon film deposited on an inner wall or the like of a reaction chamber of the apparatus is removed efficiently in a short time. To remove the carbon film deposited on the inner wall of the reaction chamber by a thermal CVD method, the reaction chamber is heated at a temperature higher than or equal to 700° C. and lower than or equal to 800° C., and oxygen is introduced into the reaction chamber.Type: GrantFiled: November 19, 2012Date of Patent: June 2, 2015Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Satoshi Toriumi, Makoto Furuno
-
Publication number: 20150053264Abstract: An object is to increase conversion efficiency of a photoelectric conversion device without increase in the manufacturing steps. The photoelectric conversion device includes a first semiconductor layer formed using a single crystal semiconductor having one conductivity type which is formed over a supporting substrate, a buffer layer including a single crystal region and an amorphous region, a second semiconductor layer which includes a single crystal region and an amorphous region and is provided over the butler layer, and a third semiconductor layer having a conductivity type opposite to the one conductivity type, which is provided over the second semiconductor layer. A proportion of the single crystal region is higher than that of the amorphous region on the first semiconductor layer side in the second semiconductor layer, and the proportion of the amorphous region is higher than that of the single crystal region on the third semiconductor layer side.Type: ApplicationFiled: October 15, 2014Publication date: February 26, 2015Inventors: Sho KATO, Yoshikazu HIURA, Akihisa SHIMOMURA, Takashi OHTSUKI, Satoshi TORIUMI, Yasuyuki ARAI
-
Patent number: 8951902Abstract: The present invention is provided in order to remove contamination due to contaminant impurities of the interfaces of each film which forms a TFT, which is the major factor that reduces the reliability of TFTs. By connecting a washing chamber and a film formation chamber, film formation can be carried out without exposing TFTs to the air during the time from washing step to the film formation step and it becomes possible to maintain the cleanliness of the interfaces of each film which form the TFT.Type: GrantFiled: January 31, 2012Date of Patent: February 10, 2015Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Taketomi Asami, Mitsuhiro Ichijo, Satoshi Toriumi, Takashi Ohtsuki, Shunpei Yamazaki
-
Publication number: 20140319514Abstract: Electrical characteristics of a semiconductor device including the oxide semiconductor are improved. Furthermore, a highly reliable transistor with small variation in electrical characteristics is manufactured. An oxynitride insulating film functioning as a base insulating film and a transistor in contact with the oxynitride insulating film are provided. The transistor includes an oxide semiconductor film in contact with the oxynitride insulating film functioning as a base insulating film. The total amount of gas having a mass-to-charge ratio of 30 released from the oxynitride insulating film by heat treatment and double of the amount of a gas having a mass-to-charge ratio of 32 released from the oxynitride insulating film by heat treatment is greater than or equal to 5×1015/cm2 and less than or equal to 5×1016/cm2, or greater than or equal to 5×1015/cm2 and less than or equal to 3×1016/cm2.Type: ApplicationFiled: April 14, 2014Publication date: October 30, 2014Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.Inventors: Kosei Noda, Satoshi Toriumi, Kazuki Tanemura
-
Patent number: 8872021Abstract: An object is to increase conversion efficiency of a photoelectric conversion device without increase in the manufacturing steps. The photoelectric conversion device includes a first semiconductor layer formed using a single crystal semiconductor having one conductivity type which is formed over a supporting substrate, a buffer layer including a single crystal region and an amorphous region, a second semiconductor layer which includes a single crystal region and an amorphous region and is provided over the buffer layer, and a third semiconductor layer having a conductivity type opposite to the one conductivity type, which is provided over the second semiconductor layer. A proportion of the single crystal region is higher than that of the amorphous region on the first semiconductor layer side in the second semiconductor layer, and the proportion of the amorphous region is higher than that of the single crystal region on the third semiconductor layer side.Type: GrantFiled: September 23, 2009Date of Patent: October 28, 2014Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Sho Kato, Yoshikazu Hiura, Akihisa Shimomura, Takashi Ohtsuki, Satoshi Toriumi, Yasuyuki Arai
-
Patent number: 8735897Abstract: In an inverted staggered thin film transistor, a microcrystalline silicon film and a pair of silicon carbide films are provided between a gate insulating film and wirings serving as a source wiring and a drain wiring. The microcrystalline silicon film is formed on the gate insulating film side and the pair of silicon carbide films are formed on the wiring side. In such a manner, a semiconductor device having favorable electric characteristics can be manufactured with high productivity.Type: GrantFiled: March 11, 2011Date of Patent: May 27, 2014Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Hidekazu Miyairi, Koji Dairiki, Satoshi Toriumi
-
Publication number: 20140139776Abstract: An object of the present invention is to prevent the deterioration of a TFT (thin film transistor). The deterioration of the TFT by a BT test is prevented by forming a silicon oxide nitride film between the semiconductor layer of the TFT and a substrate, wherein the silicon oxide nitride film ranges from 0.3 to 1.6 in a ratio of the concentration of N to the concentration of Si.Type: ApplicationFiled: December 13, 2013Publication date: May 22, 2014Applicant: Semiconductor Energy Laboratory Co., Ltd.Inventors: Masahiko Hayakawa, Mitsunori Sakama, Satoshi Toriumi
-
Patent number: 8610182Abstract: An object of the present invention is to prevent the deterioration of a TFT (thin film transistor). The deterioration of the TFT by a BT test is prevented by forming a silicon oxide nitride film between the semiconductor layer of the TFT and a substrate, wherein the silicon oxide nitride film ranges from 0.3 to 1.6 in a ratio of the concentration of N to the concentration of Si.Type: GrantFiled: April 5, 2012Date of Patent: December 17, 2013Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Masahiko Hayakawa, Mitsunori Sakama, Satoshi Toriumi
-
Patent number: 8603899Abstract: At present, a forming process of a base film through an amorphous silicon film is conducted in respective film forming chambers in order to obtain satisfactory films. When continuous formation of the base film through the amorphous silicon film is performed in a single film forming chamber with the above film formation condition, crystallization is not sufficiently attained in a crystallization process. By forming the amorphous silicon film using silane gas diluted with hydrogen, crystallization is sufficiently attained in the crystallization process even with the continuous formation of the base film through the amorphous silicon film in the single film forming chamber.Type: GrantFiled: October 25, 2012Date of Patent: December 10, 2013Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Taketomi Asami, Mitsuhiro Ichijo, Satoshi Toriumi
-
Patent number: 8591650Abstract: It is an object to provide a method for forming a crystalline semiconductor film in which a transition layer is not formed or which includes a thinner transition layer than that in a crystalline semiconductor film which is formed by conventional method, and a method for manufacturing a thin film transistor to which the above method is applied. A semiconductor film including hydrogen is formed over a substrate or over an insulating film formed over a substrate. The semiconductor film including hydrogen undergoes surface wave plasma treatment, which is performed in a gas including hydrogen and/or a rare gas, to generate a crystal nucleus in the semiconductor film including hydrogen. The crystal nucleus is grown to form a crystalline semiconductor film by employing a plasma CVD method.Type: GrantFiled: November 25, 2008Date of Patent: November 26, 2013Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventor: Satoshi Toriumi
-
Patent number: 8519394Abstract: In an inverted staggered thin film transistor, a microcrystalline silicon film and a silicon carbide film are provided between a gate insulating film and wirings serving as a source wiring and a drain wiring. The microcrystalline silicon film is formed on the gate insulating film side and the silicon carbide film is formed on the wiring side. In such a manner, a semiconductor device having favorable electric characteristics can be manufactured with high productivity.Type: GrantFiled: March 11, 2011Date of Patent: August 27, 2013Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Hidekazu Miyairi, Koji Dairiki, Satoshi Toriumi
-
Patent number: 8487342Abstract: A separation layer containing a halogen element is formed over a glass substrate by a plasma CVD method; a semiconductor element is formed over the separation layer; and separation is then performed inside the separation layer or at its interface, so that the large-area glass substrate and the semiconductor element are detached from each other. In order to perform detachment at the interface between the glass substrate and the separation layer, the separation layer may have concentration gradient of the halogen element, and the halogen element is contained more near the interface between the separation layer and the glass substrate than in the other areas.Type: GrantFiled: December 28, 2010Date of Patent: July 16, 2013Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventor: Satoshi Toriumi
-
Patent number: 8476638Abstract: An object of the present invention is to provide a technique for manufacturing a dense crystalline semiconductor film without a cavity between crystal grains. A plasma region is formed between a first electrode and a second electrode by supplying high-frequency power of 60 MHz or less to the first electrode under a condition where a pressure of a reactive gas in a reaction chamber of a plasma CVD apparatus is set to 450 Pa to 13332 Pa, and a distance between the first electrode and the second electrode of the plasma CVD apparatus is set to 1 mm to 20 mm; crystalline deposition precursors are formed in a gas phase including the plasma region; a crystal nucleus of 5 nm to 15 nm is formed by depositing the deposition precursors; and a microcrystalline semiconductor film is formed by growing a crystal from the crystal nucleus.Type: GrantFiled: July 17, 2012Date of Patent: July 2, 2013Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Satoshi Toriumi, Ryota Tajima, Takashi Ohtsuki, Tetsuhiro Tanaka, Ryo Tokumaru, Mitsuhiro Ichijo, Kazutaka Kuriki, Tomokazu Yokoi, Toshiya Endo, Shunpei Yamazaki
-
Patent number: 8431496Abstract: A threshold voltage of a thin film transistor is adjusted. The thin film transistor is manufactured through the steps of: introducing a semiconductor material gas into a treatment chamber; forming a semiconductor film in the treatment chamber over a gate insulating layer provided covering a gate electrode; evacuating the semiconductor material gas in the treatment chamber; introducing rare gas into the treatment chamber; performing plasma treatment on the semiconductor film in the treatment chamber; forming an impurity semiconductor film over the semiconductor film; processing the semiconductor film and the impurity semiconductor film into island shapes, so that a semiconductor stack is formed; forming source and drain electrodes in contact with an impurity semiconductor layer included in the semiconductor stack. Argon is preferably used as the rare gas. The rare gas element is preferably contained in the semiconductor film at 2.5×1018 cm?3 or more.Type: GrantFiled: February 25, 2011Date of Patent: April 30, 2013Assignee: Semiconductor Energy Labortory Co., Ltd.Inventor: Satoshi Toriumi