Patents by Inventor Satoshi Toriumi
Satoshi Toriumi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8362518Abstract: A separation layer containing a halogen element is formed over a glass substrate by a plasma CVD method; a semiconductor element is formed over the separation layer; and separation is then performed inside the separation layer or at its interface, so that the large-area glass substrate and the semiconductor element are detached from each other. In order to perform detachment at the interface between the glass substrate and the separation layer, the separation layer may have concentration gradient of the halogen element, and the halogen element is contained more near the interface between the separation layer and the glass substrate than in the other areas.Type: GrantFiled: December 28, 2010Date of Patent: January 29, 2013Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventor: Satoshi Toriumi
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Patent number: 8349702Abstract: A semiconductor substrate is provided by a method suitable for mass production. Further, a semiconductor substrate having an excellent characteristic with effective use of resources is provided.Type: GrantFiled: April 20, 2009Date of Patent: January 8, 2013Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Sho Kato, Satoshi Toriumi, Fumito Isaka
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Patent number: 8343857Abstract: To provide a manufacturing method of a microcrystalline semiconductor film, the manufacturing method comprises the steps of forming a first semiconductor film over a substrate by generating plasma by performing continuous discharge under an atmosphere containing a deposition gas; forming a second semiconductor film over the first semiconductor film by generating plasma by performing pulsed discharge under the atmosphere containing the deposition gas; forming a third semiconductor film over the second semiconductor film by generating plasma by performing continuous discharge under the atmosphere containing the deposition gas; and forming a fourth semiconductor film over the third semiconductor film by generating plasma by performing pulsed discharge under the atmosphere containing the deposition gas.Type: GrantFiled: April 25, 2011Date of Patent: January 1, 2013Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventor: Satoshi Toriumi
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Patent number: 8338240Abstract: To provide a method for manufacturing a transistor which has little variation in characteristics and favorable electric characteristics. A gate insulating film is formed over a gate electrode; a semiconductor layer including a microcrystalline semiconductor is formed over the gate insulating film; an impurity semiconductor layer is formed over the semiconductor layer; a mask is formed over the impurity semiconductor layer, and then the semiconductor layer and the impurity semiconductor layer are etched with use of the mask to form a semiconductor stacked body; the mask is removed and then the semiconductor stacked body is exposed to plasma generated in an atmosphere containing a rare gas to form a barrier region on a side surface of the semiconductor stacked body; and a wiring over the impurity semiconductor layer of the semiconductor stacked body is formed.Type: GrantFiled: September 20, 2011Date of Patent: December 25, 2012Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Satoshi Toriumi, Shinobu Furukawa
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Publication number: 20120304932Abstract: An object of the present invention is to provide a technique for manufacturing a dense crystalline semiconductor film without a cavity between crystal grains. A plasma region is formed between a first electrode and a second electrode by supplying high-frequency power of 60 MHz or less to the first electrode under a condition where a pressure of a reactive gas in a reaction chamber of a plasma CVD apparatus is set to 450 Pa to 13332 Pa, and a distance between the first electrode and the second electrode of the plasma CVD apparatus is set to 1 mm to 20 mm; crystalline deposition precursors are formed in a gas phase including the plasma region; a crystal nucleus of 5 nm to 15 nm is formed by depositing the deposition precursors; and a microcrystalline semiconductor film is formed by growing a crystal from the crystal nucleus.Type: ApplicationFiled: July 17, 2012Publication date: December 6, 2012Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.Inventors: Satoshi Toriumi, Ryota Tajima, Takashi Ohtsuki, Tetsuhiro Tanaka, Ryo Tokumaru, Mitsuhiro Ichijo, Kazutaka Kuriki, Tomokazu Yokoi, Toshiya Endo, Shunpei Yamazaki
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Patent number: 8304327Abstract: At present, a forming process of a base film through an amorphous silicon film is conducted in respective film forming chambers in order to obtain satisfactory films. When continuous formation of the base film through the amorphous silicon film is performed in a single film forming chamber with the above film formation condition, crystallization is not sufficiently attained in a crystallization process. By forming the amorphous silicon film using silane gas diluted with hydrogen, crystallization is sufficiently attained in the crystallization process even with the continuous formation of the base film through the amorphous silicon film in the single film forming chamber.Type: GrantFiled: February 25, 2010Date of Patent: November 6, 2012Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Taketomi Asami, Mitsuhiro Ichijo, Satoshi Toriumi
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Patent number: 8278740Abstract: An object of the present invention is to provide a semiconductor device including an insulating layer with a high dielectric strength voltage, a low dielectric constant, and low hygroscopicity. Another object of the present invention is to provide an electronic appliance with high performance and high reliability, which uses the semiconductor device. An insulator containing nitrogen, such as silicon oxynitride or silicon nitride oxide, and an insulator containing nitrogen and fluorine, such as silicon oxynitride added with fluorine or silicon nitride oxide added with fluorine, are alternately deposited so that an insulating layer is formed. By sandwiching an insulator containing nitrogen and fluorine between insulators containing nitrogen, the insulator containing nitrogen and fluorine can be prevented from absorbing moisture and thus a dielectric strength voltage can be increased. Further, an insulator contains fluorine so that a dielectric constant can be reduced.Type: GrantFiled: April 1, 2011Date of Patent: October 2, 2012Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Satoshi Toriumi, Noriyoshi Suzuki
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Patent number: 8263421Abstract: An object is to provide a manufacturing method of a microcrystalline semiconductor film with favorable quality over a large-area substrate. After forming a gate insulating film over a gate electrode, in order to improve quality of a microcrystalline semiconductor film formed in an initial stage, glow discharge plasma is generated by supplying high-frequency powers with different frequencies, and a lower part of the film near an interface with the gate insulating film is formed under a first film formation condition, which is low in film formation rate but results in a good quality film. Thereafter, an upper part of the film is deposited under a second film formation condition with higher film formation rate, and further, a buffer layer is stacked on the microcrystalline semiconductor film.Type: GrantFiled: November 12, 2010Date of Patent: September 11, 2012Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Shunpei Yamazaki, Sachiaki Teduka, Satoshi Toriumi, Makoto Furuno, Yasuhiro Jinbo, Koji Dairiki, Hideaki Kuwabara
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Patent number: 8252669Abstract: An object of one embodiment of the present invention is to provide a technique for manufacturing a dense crystalline semiconductor film (e.g., a microcrystalline semiconductor film) without a cavity between crystal grains. A plasma region is formed between a first electrode and a second electrode by supplying high-frequency power of 60 MHz or less to the first electrode under a condition where a pressure of a reactive gas in a reaction chamber of a plasma CVD apparatus is set to 450 Pa to 13332 Pa, and a distance between the first electrode and the second electrode of the plasma CVD apparatus is set to 1 mm to 20 mm; crystalline deposition precursors are formed in a gas phase including the plasma region; a crystal nucleus of 5 nm to 15 nm is formed by depositing the deposition precursors; and a microcrystalline semiconductor film is formed by growing a crystal from the crystal nucleus.Type: GrantFiled: August 20, 2010Date of Patent: August 28, 2012Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Satoshi Toriumi, Ryota Tajima, Takashi Ohtsuki, Tetsuhiro Tanaka, Ryo Tokumaru, Mitsuhiro Ichijo, Kazutaka Kuriki, Tomokazu Yokoi, Toshiya Endo, Shunpei Yamazaki
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Publication number: 20120193632Abstract: Provided is a silicon structure with a three-dimensionally complex shape. Further provided is a simple and easy method for manufacturing the silicon structure with the use of a phenomenon in which an ordered pattern is formed spontaneously to form a nano-structure. Plasma treatment under hydrogen atmosphere is performed on an amorphous silicon layer and the following processes are performed at the same time: a reaction process for growing microcrystalline silicon on a surface of the silicon layer and a reaction process for etching the amorphous silicon layer which is exposed, so that a nano-structure including an upper structure in a microcrystalline state and a lower structure in an amorphous state, over the silicon layer is formed; accordingly, a silicon structure with a three-dimensionally complex shape can be provided.Type: ApplicationFiled: January 24, 2012Publication date: August 2, 2012Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.Inventor: Satoshi TORIUMI
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Publication number: 20120187411Abstract: An object of the present invention is to prevent the deterioration of a TFT (thin film transistor). The deterioration of the TFT by a BT test is prevented by forming a silicon oxide nitride film between the semiconductor layer of the TFT and a substrate, wherein the silicon oxide nitride film ranges from 0.3 to 1.6 in a ratio of the concentration of N to the concentration of Si.Type: ApplicationFiled: April 5, 2012Publication date: July 26, 2012Inventors: Masahiko Hayakawa, Mitsunori Sakama, Satoshi Toriumi
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Patent number: 8198629Abstract: To provide a photoelectric conversion device with improved photoelectric conversion characteristics and cost competitiveness. A photoelectric conversion device including a semiconductor junction has a semiconductor layer in which a needle-like crystal is made to grow over an impurity semiconductor layer. The impurity semiconductor layer is formed of a microcrystalline semiconductor and includes an impurity imparting one conductivity type. An amorphous semiconductor layer is deposited on a microcrystalline semiconductor layer by setting the flow rate of a dilution gas (typically silane) to 1 time to 6 times the flow rate of a semiconductor source gas (typically hydrogen) at the time of deposition. Thus, a crystal with a three-dimensional shape tapered in a direction of the deposition of a film, i.e., in a direction from the microcrystalline semiconductor layer to the amorphous semiconductor layer is made to grow.Type: GrantFiled: February 9, 2011Date of Patent: June 12, 2012Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Shunpei Yamazaki, Satoshi Toriumi, Tomokazu Yokoi, Makoto Furuno
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Publication number: 20120129329Abstract: The present invention is provided in order to remove contamination due to contaminant impurities of the interfaces of each film which forms a TFT, which is the major factor that reduces the reliability of TFTs. By connecting a washing chamber and a film formation chamber, film formation can be carried out without exposing TFTs to the air during the time from washing step to the film formation step and it becomes possible to maintain the cleanliness of the interfaces of each film which form the TFT.Type: ApplicationFiled: January 31, 2012Publication date: May 24, 2012Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.Inventors: Taketomi ASAMI, Mitsuhiro ICHIJO, Satoshi TORIUMI, Takashi OHTSUKI, Shunpei YAMAZAKI
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Patent number: 8173496Abstract: A stack including at least an insulating layer, a first electrode, and a first impurity semiconductor layer is provided over a supporting substrate; a first semiconductor layer to which an impurity element imparting one conductivity type is added is formed over the first impurity semiconductor layer; a second semiconductor layer to which an impurity element imparting the one conductivity type is added is formed over the first semiconductor layer under a condition different from that of the first semiconductor layer; crystallinity of the first semiconductor layer and crystallinity of the second semiconductor layer are improved by a solid-phase growth method to form a second impurity semiconductor layer; an impurity element imparting the one conductivity type and an impurity element imparting a conductivity type different from the one conductivity type are added to the second impurity semiconductor layer; and a gate electrode layer is formed via a gate insulating layer.Type: GrantFiled: February 10, 2011Date of Patent: May 8, 2012Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Sho Kato, Satoshi Toriumi, Fumito Isaka, Hideto Ohnuma
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Patent number: 8154059Abstract: An object of the present invention is to prevent the deterioration of a TFT (thin film transistor). The deterioration of the TFT by a BT test is prevented by forming a silicon oxide nitride film between the semiconductor layer of the TFT and a substrate, wherein the silicon oxide nitride film ranges from 0.3 to 1.6 in a ratio of the concentration of N to the concentration of Si.Type: GrantFiled: October 22, 2010Date of Patent: April 10, 2012Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Masahiko Hayakawa, Mitsunori Sakama, Satoshi Toriumi
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Publication number: 20120083078Abstract: To provide a method for manufacturing a transistor which has little variation in characteristics and favorable electric characteristics. A gate insulating film is formed over a gate electrode; a semiconductor layer including a microcrystalline semiconductor is formed over the gate insulating film; an impurity semiconductor layer is formed over the semiconductor layer; a mask is formed over the impurity semiconductor layer, and then the semiconductor layer and the impurity semiconductor layer are etched with use of the mask to form a semiconductor stacked body; the mask is removed and then the semiconductor stacked body is exposed to plasma generated in an atmosphere containing a rare gas to form a barrier region on a side surface of the semiconductor stacked body; and a wiring over the impurity semiconductor layer of the semiconductor stacked body is formed.Type: ApplicationFiled: September 20, 2011Publication date: April 5, 2012Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.Inventors: Satoshi TORIUMI, Shinobu FURUKAWA
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Patent number: 8138101Abstract: The present invention is provided in order to remove contamination due to contaminant impurities of the interfaces of each film which forms a TFT, which is the major factor that reduces the reliability of TFTs. By connecting a washing chamber and a film formation chamber, film formation can be carried out without exposing TFTs to the air during the time from washing step to the film formation step and it becomes possible to maintain the cleanliness of the interfaces of each film which form the TFT.Type: GrantFiled: April 17, 2007Date of Patent: March 20, 2012Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Taketomi Asami, Mitsuhiro Ichijo, Satoshi Toriumi, Takashi Ohtsuki, Shunpei Yamazaki
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Publication number: 20120033156Abstract: A liquid crystal display device which includes a pair of substrates, a pixel including a liquid crystal element between the pair of substrates, a lighting portion provided on the outer side of the pair of substrates, a first polarizing member between the pair of substrates and the lighting portion, a reflective member provided outside the lightning portion, a second polarizing member on a side opposite to the first polarizing member with the pair of substrates provided therebetween, and a first optical sensor and a second optical sensor. The first optical sensor has a function of detecting illuminance of external light, and the second optical sensor has a function of detecting a color tone of polarized light emitted from the pixel portion. The lightning portion can emits light having a predetermined wavelength depending on the color tone of the pixel portion which is detected by the second optical sensor.Type: ApplicationFiled: August 4, 2011Publication date: February 9, 2012Inventors: Shunpei YAMAZAKI, Satoshi TORIUMI, Toshiyuki ISA
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Publication number: 20110263080Abstract: To provide a manufacturing method of a microcrystalline semiconductor film, the manufacturing method comprises the steps of forming a first semiconductor film over a substrate by generating plasma by performing continuous discharge under an atmosphere containing a deposition gas; forming a second semiconductor film over the first semiconductor film by generating plasma by performing pulsed discharge under the atmosphere containing the deposition gas; forming a third semiconductor film over the second semiconductor film by generating plasma by performing continuous discharge under the atmosphere containing the deposition gas; and forming a fourth semiconductor film over the third semiconductor film by generating plasma by performing pulsed discharge under the atmosphere containing the deposition gas.Type: ApplicationFiled: April 25, 2011Publication date: October 27, 2011Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.Inventor: Satoshi TORIUMI
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Publication number: 20110220907Abstract: In an inverted staggered thin film transistor, a microcrystalline silicon film and a pair of silicon carbide films are provided between a gate insulating film and wirings serving as a source wiring and a drain wiring. The microcrystalline silicon film is formed on the gate insulating film side and the pair of silicon carbide films are formed on the wiring side. In such a manner, a semiconductor device having favorable electric characteristics can be manufactured with high productivity.Type: ApplicationFiled: March 11, 2011Publication date: September 15, 2011Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.Inventors: Hidekazu MIYAIRI, Koji DAIRIKI, Satoshi TORIUMI