Patents by Inventor Satoshi Toriumi
Satoshi Toriumi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20110220905Abstract: In an inverted staggered thin film transistor, a microcrystalline silicon film and a silicon carbide film are provided between a gate insulating film and wirings serving as a source wiring and a drain wiring. The microcrystalline silicon film is formed on the gate insulating film side and the silicon carbide film is formed on the wiring side. In such a manner, a semiconductor device having favorable electric characteristics can be manufactured with high productivity.Type: ApplicationFiled: March 11, 2011Publication date: September 15, 2011Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.Inventors: Hidekazu MIYAIRI, Koji DAIRIKI, Satoshi TORIUMI
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Publication number: 20110215332Abstract: A threshold voltage of a thin film transistor is adjusted. The thin film transistor is manufactured through the steps of: introducing a semiconductor material gas into a treatment chamber; forming a semiconductor film in the treatment chamber over a gate insulating layer provided covering a gate electrode; evacuating the semiconductor material gas in the treatment chamber; introducing rare gas into the treatment chamber; performing plasma treatment on the semiconductor film in the treatment chamber; forming an impurity semiconductor film over the semiconductor film; processing the semiconductor film and the impurity semiconductor film into island shapes, so that a semiconductor stack is formed; forming source and drain electrodes in contact with an impurity semiconductor layer included in the semiconductor stack. Argon is preferably used as the rare gas. The rare gas element is preferably contained in the semiconductor film at 2.5×1018 cm?3 or more.Type: ApplicationFiled: February 25, 2011Publication date: September 8, 2011Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.Inventor: Satoshi TORIUMI
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Publication number: 20110193087Abstract: To provide a photoelectric conversion device with improved photoelectric conversion characteristics and cost competitiveness. A photoelectric conversion device including a semiconductor junction has a semiconductor layer in which a needle-like crystal is made to grow over an impurity semiconductor layer. The impurity semiconductor layer is formed of a microcrystalline semiconductor and includes an impurity imparting one conductivity type. An amorphous semiconductor layer is deposited on a microcrystalline semiconductor layer by setting the flow rate of a dilution gas (typically silane) to 1 time to 6 times the flow rate of a semiconductor source gas (typically hydrogen) at the time of deposition. Thus, a crystal with a three-dimensional shape tapered in a direction of the deposition of a film, i.e., in a direction from the microcrystalline semiconductor layer to the amorphous semiconductor layer is made to grow.Type: ApplicationFiled: February 9, 2011Publication date: August 11, 2011Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.Inventors: Shunpei YAMAZAKI, Satoshi TORIUMI, Tomokazu YOKOI, Makoto FURUNO
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Publication number: 20110175208Abstract: An object of the present invention is to provide a semiconductor device including an insulating layer with a high dielectric strength voltage, a low dielectric constant, and low hygroscopicity. Another object of the present invention is to provide an electronic appliance with high performance and high reliability, which uses the semiconductor device. An insulator containing nitrogen, such as silicon oxynitride or silicon nitride oxide, and an insulator containing nitrogen and fluorine, such as silicon oxynitride added with fluorine or silicon nitride oxide added with fluorine, are alternately deposited so that an insulating layer is formed. By sandwiching an insulator containing nitrogen and fluorine between insulators containing nitrogen, the insulator containing nitrogen and fluorine can be prevented from absorbing moisture and thus a dielectric strength voltage can be increased. Further, an insulator contains fluorine so that a dielectric constant can be reduced.Type: ApplicationFiled: April 1, 2011Publication date: July 21, 2011Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.Inventors: Satoshi TORIUMI, Noriyoshi SUZUKI
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Patent number: 7955994Abstract: An object of the present invention is to provide a semiconductor device including an insulating layer with a high dielectric strength voltage, a low dielectric constant, and low hygroscopicity. Another object of the present invention is to provide an electronic appliance with high performance and high reliability, which uses the semiconductor device. An insulator containing nitrogen, such as silicon oxynitride or silicon nitride oxide, and an insulator containing nitrogen and fluorine, such as silicon oxynitride added with fluorine or silicon nitride oxide added with fluorine, are alternately deposited so that an insulating layer is formed. By sandwiching an insulator containing nitrogen and fluorine between insulators containing nitrogen, the insulator containing nitrogen and fluorine can be prevented from absorbing moisture and thus a dielectric strength voltage can be increased. Further, an insulator contains fluorine so that a dielectric constant can be reduced.Type: GrantFiled: October 1, 2008Date of Patent: June 7, 2011Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Satoshi Toriumi, Noriyoshi Suzuki
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Publication number: 20110129969Abstract: A stack including at least an insulating layer, a first electrode, and a first impurity semiconductor layer is provided over a supporting substrate; a first semiconductor layer to which an impurity element imparting one conductivity type is added is formed over the first impurity semiconductor layer; a second semiconductor layer to which an impurity element imparting the one conductivity type is added is formed over the first semiconductor layer under a condition different from that of the first semiconductor layer; crystallinity of the first semiconductor layer and crystallinity of the second semiconductor layer are improved by a solid-phase growth method to form a second impurity semiconductor layer; an impurity element imparting the one conductivity type and an impurity element imparting a conductivity type different from the one conductivity type are added to the second impurity semiconductor layer; and a gate electrode layer is formed via a gate insulating layer.Type: ApplicationFiled: February 10, 2011Publication date: June 2, 2011Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.Inventors: Sho KATO, Satoshi TORIUMI, Fumito ISAKA, Hideto OHNUMA
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Patent number: 7951656Abstract: A stack including at least an insulating layer, a first electrode, and a first impurity semiconductor layer is provided over a supporting substrate; a first semiconductor layer to which an impurity element imparting one conductivity type is added is formed over the first impurity semiconductor layer; a second semiconductor layer to which an impurity element imparting the one conductivity type is added is formed over the first semiconductor layer under a condition different from that of the first semiconductor layer; crystallinity of the first semiconductor layer and crystallinity of the second semiconductor layer are improved by a solid-phase growth method to form a second impurity semiconductor layer; an impurity element imparting the one conductivity type and an impurity element imparting a conductivity type different from the one conductivity type are added to the second impurity semiconductor layer; and a gate electrode layer is formed via a gate insulating layer.Type: GrantFiled: May 18, 2009Date of Patent: May 31, 2011Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Sho Kato, Satoshi Toriumi, Fumito Isaka, Hideto Ohnuma
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Patent number: 7947523Abstract: An embrittlement layer is formed in the single crystal semiconductor substrate and a first impurity semiconductor layer, a first electrode, and an insulating layer are formed on one surface of the single crystal semiconductor substrate. After attaching the insulating layer and a supporting substrate to each other to bond the single crystal semiconductor substrate and the supporting substrate, the single crystal semiconductor substrate is separated along the embrittlement layer to form a stack including a first single crystal semiconductor layer. A first semiconductor layer and a second semiconductor layer are formed over the first single crystal semiconductor layer. A second single crystal semiconductor layer is formed by solid phase growth. A second impurity semiconductor layer having a conductivity type opposite to that of the first impurity semiconductor layer is formed on the second single crystal semiconductor layer. A second electrode is formed on the second impurity semiconductor layer.Type: GrantFiled: April 16, 2009Date of Patent: May 24, 2011Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Sho Kato, Satoshi Toriumi, Fumito Isaka
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Publication number: 20110101363Abstract: A separation layer containing a halogen element is formed over a glass substrate by a plasma CVD method; a semiconductor element is formed over the separation layer; and separation is then performed inside the separation layer or at its interface, so that the large-area glass substrate and the semiconductor element are detached from each other. In order to perform detachment at the interface between the glass substrate and the separation layer, the separation layer may have concentration gradient of the halogen element, and the halogen element is contained more near the interface between the separation layer and the glass substrate than in the other areas.Type: ApplicationFiled: December 28, 2010Publication date: May 5, 2011Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.Inventor: Satoshi TORIUMI
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Patent number: 7932097Abstract: A method of manufacturing an analytical sample by a secondary ion mass spectrometry method is provided, which comprises a step of forming a separation layer over a substrate, a step of forming one of a thin film and a thin-film stack body to be analyzed over the separation layer, a step of forming an opening portion in one of the thin film and the thin-film stack body, a step of attaching a supporting body to one of a surface of the thin film and a surface of a top layer of the thin-film stack body, and a step of separating one of the thin film and the thin-film stack body from the substrate.Type: GrantFiled: October 20, 2010Date of Patent: April 26, 2011Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventor: Satoshi Toriumi
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Publication number: 20110059562Abstract: An object is to provide a manufacturing method of a microcrystalline semiconductor film with favorable quality over a large-area substrate. After forming a gate insulating film over a gate electrode, in order to improve quality of a microcrystalline semiconductor film formed in an initial stage, glow discharge plasma is generated by supplying high-frequency powers with different frequencies, and a lower part of the film near an interface with the gate insulating film is formed under a first film formation condition, which is low in film formation rate but results in a good quality film. Thereafter, an upper part of the film is deposited under a second film formation condition with higher film formation rate, and further, a buffer layer is stacked on the microcrystalline semiconductor film.Type: ApplicationFiled: November 12, 2010Publication date: March 10, 2011Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.Inventors: Shunpei YAMAZAKI, Sachiaki TEDUKA, Satoshi TORIUMI, Makoto FURUNO, Yasuhiro JINBO, Koji DAIRIKI, Hideaki KUWABARA
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Publication number: 20110053358Abstract: An object of one embodiment of the present invention is to provide a technique for manufacturing a dense crystalline semiconductor film (e.g., a microcrystalline semiconductor film) without a cavity between crystal grains. A plasma region is formed between a first electrode and a second electrode by supplying high-frequency power of 60 MHz or less to the first electrode under a condition where a pressure of a reactive gas in a reaction chamber of a plasma CVD apparatus is set to 450 Pa to 13332 Pa, and a distance between the first electrode and the second electrode of the plasma CVD apparatus is set to 1 mm to 20 mm; crystalline deposition precursors are formed in a gas phase including the plasma region; a crystal nucleus of 5 nm to 15 nm is formed by depositing the deposition precursors; and a microcrystalline semiconductor film is formed by growing a crystal from the crystal nucleus.Type: ApplicationFiled: August 20, 2010Publication date: March 3, 2011Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.Inventors: Satoshi TORIUMI, Ryota TAJIMA, Takashi OHTSUKI, Tetsuhiro TANAKA, Ryo TOKUMARU, Mitsuhiro ICHIJO, Kazutaka KURIKI, Tomokazu YOKOI, Toshiya ENDO, Shunpei YAMAZAKI
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Patent number: 7897482Abstract: A separation layer containing a halogen element is formed over a glass substrate by a plasma CVD method; a semiconductor element is formed over the separation layer; and separation is then performed inside the separation layer or at its interface, so that the large-area glass substrate and the semiconductor element are detached from each other. In order to perform detachment at the interface between the glass substrate and the separation layer, the separation layer may have concentration gradient of the halogen element, and the halogen element is contained more near the interface between the separation layer and the glass substrate than in the other areas.Type: GrantFiled: May 19, 2008Date of Patent: March 1, 2011Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventor: Satoshi Toriumi
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Patent number: 7888167Abstract: To provide a photoelectric conversion device with improved photoelectric conversion characteristics and cost competitiveness. A photoelectric conversion device including a semiconductor junction has a semiconductor layer in which a needle-like crystal is made to grow over an impurity semiconductor layer. The impurity semiconductor layer is formed of a microcrystalline semiconductor and includes an impurity imparting one conductivity type. An amorphous semiconductor layer is deposited on a microcrystalline semiconductor layer by setting the flow rate of a dilution gas (typically silane) to 1 time to 6 times the flow rate of a semiconductor source gas (typically hydrogen) at the time of deposition. Thus, a crystal with a three-dimensional shape tapered in a direction of the deposition of a film, i.e., in a direction from the microcrystalline semiconductor layer to the amorphous semiconductor layer is made to grow.Type: GrantFiled: April 13, 2009Date of Patent: February 15, 2011Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Shunpei Yamazaki, Satoshi Toriumi, Tomokazu Yokoi, Makoto Furuno
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Publication number: 20110034215Abstract: An object of the present invention is to prevent the deterioration of a TFT (thin film transistor). The deterioration of the TFT by a BT test is prevented by forming a silicon oxide nitride film between the semiconductor layer of the TFT and a substrate, wherein the silicon oxide nitride film ranges from 0.3 to 1.6 in a ratio of the concentration of N to the concentration of Si.Type: ApplicationFiled: October 22, 2010Publication date: February 10, 2011Inventors: Masahiko Hayakawa, Mitsunori Sakama, Satoshi Toriumi
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Publication number: 20110031390Abstract: A method of manufacturing an analytical sample by a secondary ion mass spectrometry method is provided, which comprises a step of forming a separation layer over a substrate, a step of forming one of a thin film and a thin-film stack body to be analyzed over the separation layer, a step of forming an opening portion in one of the thin film and the thin-film stack body, a step of attaching a supporting body to one of a surface of the thin film and a surface of a top layer of the thin-film stack body, and a step of separating one of the thin film and the thin-film stack body from the substrate.Type: ApplicationFiled: October 20, 2010Publication date: February 10, 2011Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.Inventor: Satoshi TORIUMI
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Patent number: 7846741Abstract: A method of manufacturing an analytical sample by a secondary ion mass spectrometry method is provided, which comprises a step of forming a separation layer over a substrate, a step of forming one of a thin film and a thin-film stack body to be analyzed over the separation layer, a step of forming an opening portion in one of the thin film and the thin-film stack body, a step of attaching a supporting body to one of a surface of the thin film and a surface of a top layer of the thin-film stack body, and a step of separating one of the thin film and the thin-film stack body from the substrate.Type: GrantFiled: March 18, 2010Date of Patent: December 7, 2010Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventor: Satoshi Toriumi
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Patent number: 7833845Abstract: An object is to provide a manufacturing method of a microcrystalline semiconductor film with favorable quality over a large-area substrate. After forming a gate insulating film over a gate electrode, in order to improve quality of a microcrystalline semiconductor film formed in an initial stage, glow discharge plasma is generated by supplying high-frequency powers with different frequencies, and a lower part of the film near an interface with the gate insulating film is formed under a first film formation condition, which is low in film formation rate but results in a good quality film. Thereafter, an upper part of the film is deposited under a second film formation condition with higher film formation rate, and further, a buffer layer is stacked on the microcrystalline semiconductor film.Type: GrantFiled: August 12, 2008Date of Patent: November 16, 2010Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Shunpei Yamazaki, Sachiaki Teduka, Satoshi Toriumi, Makoto Furuno, Yasuhiro Jinbo, Koji Dairiki, Hideaki Kuwabara
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Patent number: 7821071Abstract: An object of the present invention is to prevent the deterioration of a TFT (thin film transistor). The deterioration of the TFT by a BT test is prevented by forming a silicon oxide nitride film between the semiconductor layer of the TFT and a substrate, wherein the silicon oxide nitride film ranges from 0.3 to 1.6 in a ratio of the concentration of N to the concentration of Si.Type: GrantFiled: March 6, 2009Date of Patent: October 26, 2010Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Masahiko Hayakawa, Mitsunori Sakama, Satoshi Toriumi
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Publication number: 20100171034Abstract: A method of manufacturing an analytical sample by a secondary ion mass spectrometry method is provided, which comprises a step of forming a separation layer over a substrate, a step of forming one of a thin film and a thin-film stack body to be analyzed over the separation layer, a step of forming an opening portion in one of the thin film and the thin-film stack body, a step of attaching a supporting body to one of a surface of the thin film and a surface of a top layer of the thin-film stack body, and a step of separating one of the thin film and the thin-film stack body from the substrate.Type: ApplicationFiled: March 18, 2010Publication date: July 8, 2010Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.Inventor: Satoshi Toriumi