Patents by Inventor SEAN T. MA

SEAN T. MA has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20210280708
    Abstract: Described herein are transistor arrangements fabricated by forming a metal gate cut as a trench that is non-selective to the gate sidewalls, in an etch process that can remove both the gate electrode materials and the surrounding dielectrics. Such an etch process may provide improvements in terms of accuracy, cost-efficiency, and device performance, compared to conventional approaches to forming metal gate cuts. In addition, such a process may be used to provide power rails, if the trench of a metal gate cut is to be at least partially filled with an electrically conductive material. Because the electrically conductive material is in the trench and may be in between the fins, as opposed to being provided over the fins, such power rails may be referred to as “recessed.” Providing recessed power rails may provide improvements in terms of reduced metal line resistance and reduced voltage droop.
    Type: Application
    Filed: March 9, 2020
    Publication date: September 9, 2021
    Applicant: Intel Corporation
    Inventors: Andy Chih-Hung Wei, Sean T. Ma, Piyush Mohan Sinha
  • Patent number: 11107890
    Abstract: An apparatus is described. The apparatus includes a FINFET device having a channel. The channel is composed of a first semiconductor material that is epitaxially grown on a subfin structure beneath the channel. The subfin structure is composed of a second semiconductor material that is different than the first semiconductor material. The subfin structure is epitaxially grown on a substrate composed of a third semiconductor material that is different than the first and second semiconductor materials. The subfin structure has a doped region to substantially impede leakage currents between the channel and the substrate.
    Type: Grant
    Filed: June 30, 2016
    Date of Patent: August 31, 2021
    Assignee: Intel Corporation
    Inventors: Gilbert Dewey, Matthew V. Metz, Willy Rachmady, Anand S. Murthy, Chandra S. Mohapatra, Tahir Ghani, Sean T. Ma, Jack T. Kavalieros
  • Patent number: 11075119
    Abstract: An apparatus is provided which comprises: a fin; a layer formed on the fin, the layer dividing the fin in a first section and a second section; a first device formed on the first section of the fin; and a second device formed on the second section of the fin.
    Type: Grant
    Filed: March 30, 2017
    Date of Patent: July 27, 2021
    Assignee: Intel Corporation
    Inventors: Aaron D. Lilak, Sean T. Ma, Justin R. Weber, Patrick Morrow, Rishabh Mehandru
  • Patent number: 11049773
    Abstract: A transistor device comprising a channel disposed on a substrate between a source and a drain, a gate electrode disposed on the channel, wherein the channel comprises a channel material that is separated from a body of the same material on a substrate. A method comprising forming a trench in a dielectric layer on an integrated circuit substrate, the trench comprising dimensions for a transistor body including a width; depositing a spacer layer in a portion of the trench, the spacer layer narrowing the width of the trench; forming a channel material in the trench through the spacer layer; recessing the dielectric layer to define a first portion of the channel material exposed and a second portion of the channel material in the trench; and separating the first portion of the channel material from the second portion of the channel material.
    Type: Grant
    Filed: September 30, 2016
    Date of Patent: June 29, 2021
    Assignee: Intel Corporation
    Inventors: Gilbert Dewey, Matthew V. Metz, Sean T. Ma, Cheng-Ying Huang, Tahir Ghani, Anand S. Murthy, Harold W. Kennel, Nicholas G. Minutillo, Jack T. Kavalieros, Willy Rachmady
  • Patent number: 10957769
    Abstract: Monolithic FETs including a fin of a first III-V semiconductor material offering high carrier mobility is clad with a second III-V semiconductor material having a wider bandgap. The wider bandgap cladding may advantageously reduce band-to-band tunneling (BTBT) leakage current while transistor is in an off-state while the lower bandgap core material may advantageously provide high current conduction while transistor is in an on-state. In some embodiments, a InGaAs cladding material richer in Ga is grown over an InGaAs core material richer in In. In some embodiments, the semiconductor cladding is a few nanometers thick layer epitaxially grown on surfaces of the semiconductor core. The cladded fin may be further integrated into a gate-last finFET fabrication process. Other embodiments may be described and/or claimed.
    Type: Grant
    Filed: June 17, 2016
    Date of Patent: March 23, 2021
    Assignee: Intel Corporation
    Inventors: Sean T. Ma, Chandra S. Mohapatra, Gilbert Dewey, Willy Rachmady, Harold W. Kennel, Matthew V. Metz, Jack T. Kavalieros, Anand S. Murthy, Tahir Ghani
  • Patent number: 10903364
    Abstract: Embodiments are generally directed to a semiconductor device with released source and drain. An embodiment of a method includes etching a buffer layer of a semiconductor device to form a gate trench under a gate channel portion of a channel layer of the device; filling the gate trench with an oxide material to form an oxide isolation layer; etching one or more source/drain contact trenches in an interlayer dielectric (ILD) layer for source and drain regions of the device; etching the oxide isolation layer within the one or more source/drain contact trenches to form one or more cavities under a source/drain channel in the source and drain regions, wherein the etching of each contact trench is to expose all sides of the source/drain channel; and depositing contact metal in the one or more contact trenches, including depositing the contact metal in the cavities under the source/drain channel.
    Type: Grant
    Filed: July 2, 2016
    Date of Patent: January 26, 2021
    Assignee: Intel Corporation
    Inventors: Willy Rachmady, Sanaz K. Gardner, Chandra S. Mohapatra, Matthew V. Metz, Gilbert Dewey, Sean T. Ma, Jack T. Kavalieros, Anand S. Murthy, Tahir Ghani
  • Patent number: 10892335
    Abstract: Disclosed herein are tri-gate and all-around-gate transistor arrangements, and related methods and devices. For example, in some embodiments, a transistor arrangement may include a channel material disposed over a substrate; a gate electrode of a first tri-gate or all-around-gate transistor, disposed over a first part of the channel material; and a gate electrode of a second tri-gate or all-around-gate transistor, disposed over a second part of the channel material. The transistor arrangement may further include a device isolation structure made of a fixed charge dielectric material disposed over a third part of the channel material, the third part being between the first part and the second part of the channel material.
    Type: Grant
    Filed: December 1, 2016
    Date of Patent: January 12, 2021
    Assignee: Intel Corporation
    Inventors: Sean T. Ma, Willy Rachmady, Gilbert W. Dewey, Aaron D. Lilak, Justin R. Weber, Harold W. Kennel, Cheng-Ying Huang, Matthew V. Metz, Jack T. Kavalieros, Anand S. Murthy, Tahir Ghani
  • Patent number: 10886408
    Abstract: Techniques are disclosed for forming group III-V material transistors employing nitride-based dopant diffusion barrier layers. The techniques can include growing the dilute nitride-based barrier layer as a relatively thin layer of III-V material in the sub-channel (or sub-fin) region of a transistor, near the substrate/III-V material interface, for example. Such a nitride-based barrier layer can be used to trap atoms from the substrate at vacancy sites within the III-V material. Therefore, the barrier layer can arrest substrate atoms from diffusing in an undesired manner by protecting the sub-channel layer from being unintentionally doped due to subsequent processing in the transistor fabrication. In addition, by forming the barrier layer pseudomorphically, the lattice mismatch of the barrier layer with the sub-channel layer in the heterojunction stack becomes insignificant. In some embodiments, the group III-V alloyed with nitrogen (N) material may include an N concentration of less than 5, 2, or 1.
    Type: Grant
    Filed: September 29, 2016
    Date of Patent: January 5, 2021
    Assignee: INTEL CORPORATION
    Inventors: Chandra S. Mohapatra, Harold W. Kennel, Glenn A. Glass, Willy Rachmady, Anand S. Murthy, Gilbert Dewey, Jack T. Kavalieros, Tahir Ghani, Matthew V. Metz, Sean T. Ma
  • Patent number: 10879365
    Abstract: In various embodiments, the disclosure describes transistors having non-vertical gates. In one embodiment, the non-vertical gates can have a curved or wide angle gate in order to reduce the electric field crowing on the drain side of the gate edge and/or portions having corners and thereby reduce leakage current in the transistor. In one embodiment, the non-vertical gate can be generated by one or more etching steps (for example, isotropic etching steps) of an underlying channel during the fabrication of a transistor having the non-vertical gate. In one embodiment, the non-vertical gate can be generated by one or more directional etching steps that may expose various facets having predetermined orientations of a source and/or drain associated with the transistor.
    Type: Grant
    Filed: March 31, 2017
    Date of Patent: December 29, 2020
    Assignee: Intel Corporation
    Inventors: Cheng-Ying Huang, Sean T. Ma, Willy Rachmady, Gilbert Dewey, Matthew V. Metz, Harold W. Kennel, Jack T. Kavalieros, Anand S. Murthy, Tahir Ghani
  • Publication number: 20200403033
    Abstract: A memory structure includes conductive lines extending horizontally in a spaced apart fashion within a vertical stack above a base or substrate. The vertical stack includes a plurality of conductive lines, the first and second conductive lines being part of the plurality. A gate structure extends vertically through the first and second conductive lines. The gate structure includes a body of semiconductor material and a dielectric, where the dielectric is between the body and the conductive lines. An isolation material is on at least one side of the vertical stack and in contact with the conductive lines. The vertical stack defines a void located vertically between at the first and second conductive lines in the vertical stack and laterally between the gate structure and the isolation material. The void may extend along a substantial length (e.g., 20 nm or more) of the first and second conductive lines.
    Type: Application
    Filed: June 20, 2019
    Publication date: December 24, 2020
    Applicant: Intel Corporation
    Inventors: Aaron D. Lilak, Patrick R. Morrow, Hui Jae Yoo, Sean T. Ma, Scott B. Clendenning, Abhishek A. Sharma, Ehren Mannebach, Urusa Alaan
  • Patent number: 10861939
    Abstract: Semiconductor devices, computing devices, and related methods are disclosed herein. A semiconductor device includes a seed material, an epitaxial material in contact with the seed material, and at least one quantum region including an elastic stiffness that is greater than an elastic stiffness of the epitaxial material. The epitaxial material has lattice parameters that are different from lattice parameters of the seed material by at least a threshold amount. Lattice parameters of the quantum region are within the threshold amount of the lattice parameters of the epitaxial material. A method includes disposing an epitaxial material on a seed material, disposing a quantum region on the epitaxial material, and disposing the epitaxial material on the quantum region.
    Type: Grant
    Filed: September 30, 2016
    Date of Patent: December 8, 2020
    Assignee: Intel Corporation
    Inventors: Matthew Metz, Gilbert Dewey, Harold W. Kennel, Cheng-Ying Huang, Sean T. Ma, Willy Rachmady
  • Publication number: 20200321435
    Abstract: Monolithic FETs including a fin of a first semiconductor composition disposed on a sub-fin of a second composition. In some examples, an InGaAs fin is grown over GaAs sub-fin. The sub-fin may be epitaxially grown from a seeding surface disposed within a trench defined in an isolation dielectric. The sub-fin may be planarized with the isolation dielectric. The fin may then be epitaxially grown from the planarized surface of the sub-fin. A gate stack may be disposed over the fin with the gate stack contacting the planarized surface of the isolation dielectric so as to be self-aligned with the interface between the fin and sub-fin. Other embodiments may be described and/or claimed.
    Type: Application
    Filed: June 17, 2016
    Publication date: October 8, 2020
    Applicant: Intel Corporation
    Inventors: Sean T. Ma, Matthew V. Metz, Willy Rachmady, Gilbert Dewey, Chandra S. Mohapatra, Jack T. Kavalieros, Anand S. Murthy, Tahir Ghani
  • Publication number: 20200321439
    Abstract: Monolithic FETs including a fin of a first III-V semiconductor material offering high carrier mobility is clad with a second III-V semiconductor material having a wider bandgap. The wider bandgap cladding may advantageously reduce band-to-band tunneling (BTBT) leakage current while transistor is in an off-state while the lower bandgap core material may advantageously provide high current conduction while transistor is in an on-state. In some embodiments, a InGaAs cladding material richer in Ga is grown over an InGaAs core material richer in In. In some embodiments, the semiconductor cladding is a few nanometers thick layer epitaxially grown on surfaces of the semiconductor core. The cladded fin may be further integrated into a gate-last finFET fabrication process. Other embodiments may be described and/or claimed.
    Type: Application
    Filed: June 17, 2016
    Publication date: October 8, 2020
    Applicant: Intel Corporation
    Inventors: Sean T. Ma, Chandra S. Mohapatra, Gilbert Dewey, Willy Rachmady, Harold W. Kennel, Matthew V. Metz, Jack T. Kavalieros, Anand S. Murthy, Tahir Ghani
  • Patent number: 10797150
    Abstract: An apparatus including a non-planar body on a substrate, the body including a channel on a blocking material, and a gate stack on the body, the gate stack including a first gate electrode material including a first work function disposed on the channel material and a second gate electrode material including a second work function different from the first work function disposed on the channel material and on the blocking material. A method including forming a non-planar body on a substrate, the non-planar body including a channel on a blocking material, and forming a gate stack on the body, the gate stack including a first gate electrode material including a first work function disposed on the channel and a second gate electrode material including a second work function different from the first work function disposed on the channel and on the blocking material.
    Type: Grant
    Filed: December 17, 2015
    Date of Patent: October 6, 2020
    Assignee: Intel Corporation
    Inventors: Sean T. Ma, Willy Rachmady, Matthew V. Metz, Chandra S. Mohapatra, Gilbert Dewey, Nadia M. Rahhal-Orabi, Jack T. Kavalieros, Anand S. Murthy, Tahir Ghani
  • Publication number: 20200312973
    Abstract: This disclosure illustrates a transistor with dual gate workfunctions. The transistor with dual gate workfunctions may comprise a source region, a drain region, a channel between the source region and the drain region, and a gate to control a conductivity of the channel. The gate may comprise a first portion with a first workfunction and a second portion with a second workfunction. One of the portions is nearer the source region than the other portion. The workfunction of the portion nearer the source provides a lower thermionic barrier than the workfunction of the portion further away from the source.
    Type: Application
    Filed: December 21, 2017
    Publication date: October 1, 2020
    Inventors: Sean T. MA, Abhishek SHARMA, Gilbert DEWEY, Van H. LE, Jack T. KAVALIEROS, Tahir GHANI, Benjamin CHU-KUNG, Shriram SHIVARAMAN
  • Publication number: 20200295127
    Abstract: Disclosed herein are stacked transistors with different crystal orientations in different device strata, as well as related methods and devices. In some embodiments, an integrated circuit structure may include stacked strata of transistors, wherein the channel materials in at least some of the strata have different crystal orientations.
    Type: Application
    Filed: March 13, 2019
    Publication date: September 17, 2020
    Applicant: Intel Corporation
    Inventors: Ehren Mannebach, Aaron D. Lilak, Anh Phan, Cheng-Ying Huang, Gilbert W. Dewey, Patrick Morrow, Rishabh Mehandru, Roza Kotlyar, Sean T. Ma, Willy Rachmady
  • Publication number: 20200287024
    Abstract: Transistors having a plurality of channel semiconductor structures, such as fins, over a dielectric material. A source and drain are coupled to opposite ends of the structures and a gate stack intersects the plurality of structures between the source and drain. Lateral epitaxial overgrowth (LEO) may be employed to form a super-lattice of a desired periodicity from a sidewall of a fin template structure that is within a trench and extends from the dielectric material. Following LEO, the super-lattice structure may be planarized with surrounding dielectric material to expose a top of the super-lattice layers. Alternating ones of the super-lattice layers may then be selectively etched away, with the retained layers of the super-lattice then laterally separated from each other by a distance that is a function of the super-lattice periodicity. A gate dielectric and a gate electrode may be formed over the retained super-lattice layers for a channel of a transistor.
    Type: Application
    Filed: December 27, 2017
    Publication date: September 10, 2020
    Applicant: INTEL CORPORATION
    Inventors: Gilbert Dewey, Sean T. Ma, Tahir Ghani, Willy Rachmady, Cheng-Ying Huang, Anand S. Murthy, Harold W. Kennel, Nicholas G. Minutillo, Matthew V. Metz
  • Publication number: 20200287036
    Abstract: Embodiments herein describe techniques, systems, and method for a semiconductor device. Embodiments herein may present a semiconductor device including a substrate, and a channel area above the substrate and including a first III-V material. A source area may be above the substrate and including a second III-V material. An interface between the channel area and the source area may include the first III-V material. The source area may include a barrier layer of a third III-V material above the substrate. A current is to flow between the source area and the channel area through the barrier layer. Other embodiments may be described and/or claimed.
    Type: Application
    Filed: December 30, 2017
    Publication date: September 10, 2020
    Inventors: Cheng-Ying HUANG, Willy RACHMADY, Matthew V. METZ, Gilbert DEWEY, Sean T. MA, Jack T. KAVALIEROS
  • Publication number: 20200279931
    Abstract: An apparatus is provided which comprises: a source and a drain with a channel region therebetween, the channel region comprising a semiconductor material, and a gate dielectric layer over at least a portion of the channel region, wherein the gate dielectric layer comprises a first thickness proximate to the source and a second thickness proximate to the drain, wherein the second thickness is greater than the first thickness, and wherein at least a portion of the gate dielectric layer comprises a linearly varying thickness over the channel region. Other embodiments are also disclosed and claimed.
    Type: Application
    Filed: December 27, 2017
    Publication date: September 3, 2020
    Applicant: Intel Corporation
    Inventors: Dipanjan Basu, Sean T. Ma, Willy Rachmady, Jack T. Kavalieros
  • Publication number: 20200279910
    Abstract: Material systems for source region, drain region, and a semiconductor body of transistor devices in which the semiconductor body is electrically insulated from an underlying substrate are selected to reduce or eliminate a band to band tunneling (“BTBT”) effect between different energetic bands of the semiconductor body and one or both of the source region and the drain region. This can be accomplished by selecting a material for the semiconductor body with a band gap that is larger than a band gap for material(s) selected for the source region and/or drain region.
    Type: Application
    Filed: December 15, 2017
    Publication date: September 3, 2020
    Applicant: INTEL CORPORATION
    Inventors: Dipanjan Basu, Cory E. Weber, Justin R. Weber, Sean T. Ma, Harold W. Kennel, Seung Hoon Sung, Glenn A. Glass, Jack T. Kavalieros, Tahir Ghani