Abstract: Monolithic FETs including a fin of a first III-V semiconductor material offering high carrier mobility is clad with a second III-V semiconductor material having a wider bandgap. The wider bandgap cladding may advantageously reduce band-to-band tunneling (BTBT) leakage current while transistor is in an off-state while the lower bandgap core material may advantageously provide high current conduction while transistor is in an on-state. In some embodiments, a InGaAs cladding material richer in Ga is grown over an InGaAs core material richer in In. In some embodiments, the semiconductor cladding is a few nanometers thick layer epitaxially grown on surfaces of the semiconductor core. The cladded fin may be further integrated into a gate-last finFET fabrication process. Other embodiments may be described and/or claimed.

Abstract: Monolithic FETs including a fin of a first semiconductor composition disposed on a sub-fin of a second composition. In some examples, an InGaAs fin is grown over GaAs sub-fin. The sub-fin may be epitaxially grown from a seeding surface disposed within a trench defined in an isolation dielectric. The sub-fin may be planarized with the isolation dielectric. The fin may then be epitaxially grown from the planarized surface of the sub-fin. A gate stack may be disposed over the fin with the gate stack contacting the planarized surface of the isolation dielectric so as to be self-aligned with the interface between the fin and sub-fin. Other embodiments may be described and/or claimed.

Abstract: An apparatus including a non-planar body on a substrate, the body including a channel on a blocking material, and a gate stack on the body, the gate stack including a first gate electrode material including a first work function disposed on the channel material and a second gate electrode material including a second work function different from the first work function disposed on the channel material and on the blocking material. A method including forming a non-planar body on a substrate, the non-planar body including a channel on a blocking material, and forming a gate stack on the body, the gate stack including a first gate electrode material including a first work function disposed on the channel and a second gate electrode material including a second work function different from the first work function disposed on the channel and on the blocking material.

Abstract: This disclosure illustrates a transistor with dual gate workfunctions. The transistor with dual gate workfunctions may comprise a source region, a drain region, a channel between the source region and the drain region, and a gate to control a conductivity of the channel. The gate may comprise a first portion with a first workfunction and a second portion with a second workfunction. One of the portions is nearer the source region than the other portion. The workfunction of the portion nearer the source provides a lower thermionic barrier than the workfunction of the portion further away from the source.

Abstract: Disclosed herein are stacked transistors with different crystal orientations in different device strata, as well as related methods and devices. In some embodiments, an integrated circuit structure may include stacked strata of transistors, wherein the channel materials in at least some of the strata have different crystal orientations.

Abstract: Transistors having a plurality of channel semiconductor structures, such as fins, over a dielectric material. A source and drain are coupled to opposite ends of the structures and a gate stack intersects the plurality of structures between the source and drain. Lateral epitaxial overgrowth (LEO) may be employed to form a super-lattice of a desired periodicity from a sidewall of a fin template structure that is within a trench and extends from the dielectric material. Following LEO, the super-lattice structure may be planarized with surrounding dielectric material to expose a top of the super-lattice layers. Alternating ones of the super-lattice layers may then be selectively etched away, with the retained layers of the super-lattice then laterally separated from each other by a distance that is a function of the super-lattice periodicity. A gate dielectric and a gate electrode may be formed over the retained super-lattice layers for a channel of a transistor.

Abstract: Embodiments herein describe techniques, systems, and method for a semiconductor device. Embodiments herein may present a semiconductor device including a substrate, and a channel area above the substrate and including a first III-V material. A source area may be above the substrate and including a second III-V material. An interface between the channel area and the source area may include the first III-V material. The source area may include a barrier layer of a third III-V material above the substrate. A current is to flow between the source area and the channel area through the barrier layer. Other embodiments may be described and/or claimed.

Abstract: Material systems for source region, drain region, and a semiconductor body of transistor devices in which the semiconductor body is electrically insulated from an underlying substrate are selected to reduce or eliminate a band to band tunneling (“BTBT”) effect between different energetic bands of the semiconductor body and one or both of the source region and the drain region. This can be accomplished by selecting a material for the semiconductor body with a band gap that is larger than a band gap for material(s) selected for the source region and/or drain region.

Abstract: Embodiments include a first nanowire transistor having a first source and a first drain with a first channel in between, where the first channel includes a first III-V alloy. A first gate stack is around the first channel, where a portion of the first gate stack is between the first channel and a substrate. The first gate stack includes a gate electrode metal in contact with a gate dielectric. A second nanowire transistor is on the substrate, having a second source and a second drain with a second channel therebetween, the second channel including a second III-V alloy. A second gate stack is around the second channel, where an intervening material is between the second gate stack and the substrate, the intervening material including a third III-V alloy. The second gate stack includes the gate electrode metal in contact with the gate dielectric.

Abstract: An apparatus is provided which comprises: a source and a drain with a channel region therebetween, the channel region comprising a semiconductor material, and a gate dielectric layer over at least a portion of the channel region, wherein the gate dielectric layer comprises a first thickness proximate to the source and a second thickness proximate to the drain, wherein the second thickness is greater than the first thickness, and wherein at least a portion of the gate dielectric layer comprises a linearly varying thickness over the channel region. Other embodiments are also disclosed and claimed.

Abstract: A transistor includes a body of semiconductor material with a gate structure in contact with a portion of the body. A source region contacts the body adjacent the gate structure and a drain region contacts the body adjacent the gate structure such that the portion of the body is between the source region and the drain region. A first isolation region is under the source region and has a top surface in contact with a bottom surface of the source region. A second isolation region is under the drain region and has a top surface in contact with a bottom surface of the drain region. Depending on the transistor configuration, a major portion of the inner-facing sidewalls of the first and second isolation regions contact respective sidewalls of either a subfin structure (e.g., FinFET transistor configurations) or a lower portion of a gate structure (e.g., gate-all-around transistor configuration).

Abstract: Group III-V semiconductor devices having dual workfunction gate electrodes and their methods of fabrication are described. In an example, an integrated circuit structure includes a gallium arsenide layer on a substrate. A channel structure is on the gallium arsenide layer. The channel structure includes indium, gallium and arsenic. A source structure is at a first end of the channel structure and a drain structure is at a second end of the channel structure. A gate structure is over the channel structure, the gate structure having a first workfunction material laterally adjacent a second workfunction material. The second workfunction material has a different workfunction than the first workfunction material.

Abstract: Embodiments disclosed herein include three-dimensional 3D arrays of memory cells and methods of forming such devices. In an embodiment a memory device comprises, a substrate surface, and a three-dimensional (3D) array of memory cells over the substrate surface. In an embodiment each memory cell comprises a transistor and a capacitor. In an embodiment the transistor of each memory cell comprises, a semiconductor channel, with a first end of the semiconductor channel electrically coupled to a bit line that runs substantially parallel to the substrate surface, and a second end of the semiconductor channel is electrically coupled to the capacitor. The transistor may also comprise a gate dielectric on a surface of the semiconductor channel between the first end and the second end of the semiconductor channel. In an embodiment, the gate dielectric is contacted by a word line that runs substantially perpendicular to the substrate surface.

Abstract: A back-gated thin-film transistor (TFT) includes a gate electrode, a gate dielectric on the gate electrode, an active layer on the gate dielectric and having source and drain regions and a semiconductor region physically connecting the source and drain regions, a capping layer on the semiconductor region, and a charge trap layer on the capping layer. In an embodiment, a memory cell includes this back-gated TFT and a capacitor, the gate electrode being electrically connected to a wordline and the source region being electrically connected to a bitline, the capacitor having a first terminal electrically connected to the drain region, a second terminal, and a dielectric medium electrically separating the first and second terminals. In another embodiment, an embedded memory includes wordlines extending in a first direction, bitlines extending in a second direction crossing the first direction, and several such memory cells at crossing regions of the wordlines and bitlines.

Abstract: Group III-V semiconductor devices having asymmetric source and drain structures and their methods of fabrication are described. In an example, an integrated circuit structure includes a gallium arsenide layer on a substrate. A channel structure is on the gallium arsenide layer. The channel structure includes indium, gallium and arsenic. A source structure is at a first end of the channel structure and a drain structure is at a second end of the channel structure. The drain structure has a wider band gap than the source structure. A gate structure is over the channel structure.

Abstract: Embodiments herein describe techniques for a semiconductor device including a memory cell vertically above a substrate. The memory cell includes a metal-insulator-metal (MIM) capacitor at a lower device portion, and a transistor at an upper device portion above the lower device portion. The MIM capacitor includes a first plate, and a second plate separated from the first plate by a capacitor dielectric layer. The first plate includes a first group of metal contacts coupled to a metal electrode vertically above the substrate. The first group of metal contacts are within one or more metal layers above the substrate in a horizontal direction in parallel to a surface of the substrate. Furthermore, the metal electrode of the first plate of the MIM capacitor is also a source electrode of the transistor. Other embodiments may be described and/or claimed.

Abstract: Disclosed herein are tri-gate and all-around-gate transistor arrangements, and related methods and devices. For example, in some embodiments, a transistor arrangement may include a channel material disposed over a substrate; a gate electrode of a first tri-gate or all-around-gate transistor, disposed over a first part of the channel material; and a gate electrode of a second tri-gate or all-around-gate transistor, disposed over a second part of the channel material. The transistor arrangement may further include a device isolation structure made of a fixed charge dielectric material disposed over a third part of the channel material, the third part being between the first part and the second part of the channel material.

Abstract: An embodiment includes an apparatus comprising: a substrate; a thin film transistor (TFT) comprising: source, drain, and gate contacts; a semiconductor material, comprising a channel, between the substrate and the gate contact; a gate dielectric layer between the gate contact and the channel; and an additional layer between the channel and the substrate; wherein (a)(i) the channel includes carriers selected from the group consisting of hole carriers or electron carriers, (a)(ii) the additional layer includes an insulator material that includes charged particles having a polarity equal to a polarity of the carriers. Other embodiments are described herein.

Abstract: An embodiment includes a transistor comprising: first, second, and third layers each including a group III-V material; a channel included in the second layer, which is between the first and third layers; and a gate having first and second gate portions; wherein (a)(i) the first and third layers are doped, (a)(ii) the channel is between the first and second gate portions and the second gate portion is between the channel and a substrate, (a)(iii) a first axis intersects the first, second, and third layers but not the first gate portion, and (a)(iv) a second axis, parallel to the first axis, intersects the first and second gate portions and the channel. Other embodiments are described herein.

Abstract: An electronic device comprises a first layer on a buffer layer on a substrate. A source/drain region is deposited on the buffer layer. The first layer comprises a first semiconductor. The source/drain region comprises a second semiconductor. The second semiconductor has a bandgap that is smaller than a bandgap of the first semiconductor. A gate electrode is deposited on the first layer.