Patents by Inventor SEAN T. MA
SEAN T. MA has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11569238Abstract: Embodiments herein describe techniques for a semiconductor device including a memory cell vertically above a substrate. The memory cell includes a metal-insulator-metal (MIM) capacitor at a lower device portion, and a transistor at an upper device portion above the lower device portion. The MIM capacitor includes a first plate, and a second plate separated from the first plate by a capacitor dielectric layer. The first plate includes a first group of metal contacts coupled to a metal electrode vertically above the substrate. The first group of metal contacts are within one or more metal layers above the substrate in a horizontal direction in parallel to a surface of the substrate. Furthermore, the metal electrode of the first plate of the MIM capacitor is also a source electrode of the transistor. Other embodiments may be described and/or claimed.Type: GrantFiled: December 17, 2018Date of Patent: January 31, 2023Assignee: Intel CorporationInventors: Aaron Lilak, Willy Rachmady, Gilbert Dewey, Kimin Jun, Hui Jae Yoo, Patrick Morrow, Sean T. Ma, Ahn Phan, Abhishek Sharma, Cheng-Ying Huang, Ehren Mannebach
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Patent number: 11557658Abstract: Transistors having a plurality of channel semiconductor structures, such as fins, over a dielectric material. A source and drain are coupled to opposite ends of the structures and a gate stack intersects the plurality of structures between the source and drain. Lateral epitaxial overgrowth (LEO) may be employed to form a super-lattice of a desired periodicity from a sidewall of a fin template structure that is within a trench and extends from the dielectric material. Following LEO, the super-lattice structure may be planarized with surrounding dielectric material to expose a top of the super-lattice layers. Alternating ones of the super-lattice layers may then be selectively etched away, with the retained layers of the super-lattice then laterally separated from each other by a distance that is a function of the super-lattice periodicity. A gate dielectric and a gate electrode may be formed over the retained super-lattice layers for a channel of a transistor.Type: GrantFiled: December 27, 2017Date of Patent: January 17, 2023Assignee: Intel CorporationInventors: Gilbert Dewey, Sean T. Ma, Tahir Ghani, Willy Rachmady, Cheng-Ying Huang, Anand S. Murthy, Harold W. Kennel, Nicholas G. Minutillo, Matthew V. Metz
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Publication number: 20230006065Abstract: Techniques are disclosed for an integrated circuit including a ferroelectric gate stack including a ferroelectric layer, an interfacial oxide layer, and a gate electrode. The ferroelectric layer can be voltage activated to switch between two ferroelectric states. Employing such a ferroelectric layer provides a reduction in leakage current in an off-state and provides an increase in charge in an on-state. The interfacial oxide layer can be formed between the ferroelectric layer and the gate electrode. Alternatively, the ferroelectric layer can be formed between the interfacial oxide layer and the gate electrode.Type: ApplicationFiled: August 30, 2022Publication date: January 5, 2023Applicant: Intel CorporationInventors: Gilbert DEWEY, Willy RACHMADY, Jack T. KAVALIEROS, Cheng-Ying HUANG, Matthew V. METZ, Sean T. MA, Harold KENNEL, Tahir GHANI
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Patent number: 11538808Abstract: Disclosed herein are memory cells and memory arrays, as well as related methods and devices. For example, in some embodiments, a memory device may include: a support having a surface; and a three-dimensional array of memory cells on the surface of the support, wherein individual memory cells include a transistor and a capacitor, and a channel of the transistor in an individual memory cell is oriented parallel to the surface.Type: GrantFiled: September 7, 2018Date of Patent: December 27, 2022Assignee: Intel CorporationInventors: Sean T. Ma, Aaron D. Lilak, Abhishek A. Sharma, Van H. Le, Seung Hoon Sung, Gilbert W. Dewey, Benjamin Chu-Kung, Jack T. Kavalieros, Tahir Ghani
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Patent number: 11508847Abstract: Described herein are transistor arrangements fabricated by forming a metal gate cut as a trench that is non-selective to the gate sidewalls, in an etch process that can remove both the gate electrode materials and the surrounding dielectrics. Such an etch process may provide improvements in terms of accuracy, cost-efficiency, and device performance, compared to conventional approaches to forming metal gate cuts. In addition, such a process may be used to provide power rails, if the trench of a metal gate cut is to be at least partially filled with an electrically conductive material. Because the electrically conductive material is in the trench and may be in between the fins, as opposed to being provided over the fins, such power rails may be referred to as “recessed.” Providing recessed power rails may provide improvements in terms of reduced metal line resistance and reduced voltage droop.Type: GrantFiled: March 9, 2020Date of Patent: November 22, 2022Assignee: Intel CorporationInventors: Andy Chih-Hung Wei, Sean T. Ma, Piyush Mohan Sinha
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Publication number: 20220359658Abstract: Discussed herein is device contact sizing in integrated circuit (IC) structures. In some embodiments, an IC structure may include: a first source/drain (S/D) contact in contact with a first S/D region, and a second S/D contact in contact with a second S/D region, wherein the first S/D region and the second S/D region have a same length, and the first S/D contact and the second S/D contact have different lengths.Type: ApplicationFiled: July 22, 2022Publication date: November 10, 2022Applicant: Intel CorporationInventors: Guillaume Bouche, Andy Chih-Hung Wei, Sean T. Ma
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Publication number: 20220344459Abstract: Disclosed herein are source/drain regions in integrated circuit (IC) structures, as well as related methods and components. For example, in some embodiments, an IC structure may include: an array of channel regions, including a first channel region and an adjacent second channel region; a first source/drain region proximate to the first channel region; a second source/drain region proximate to the second channel region; and an insulating material region at least partially between the first source/drain region and the second source/drain region.Type: ApplicationFiled: July 11, 2022Publication date: October 27, 2022Applicant: Intel CorporationInventors: Sean T. Ma, Andy Chih-Hung Wei, Guillaume Bouche
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Patent number: 11482524Abstract: Discussed herein is gate spacing in integrated circuit (IC) structures, as well as related methods and components. For example, in some embodiments, an IC structure may include: a first gate metal having a longitudinal axis; a second gate metal, wherein the longitudinal axis of the first gate metal is aligned with a longitudinal axis of the second gate metal; a first dielectric material continuously around the first gate metal; and a second dielectric material continuously around the second gate metal, wherein the first dielectric material and the second dielectric material are present between the first gate metal and the second gate metal.Type: GrantFiled: March 26, 2020Date of Patent: October 25, 2022Assignee: Intel CorporationInventors: Guillaume Bouche, Andy Chih-Hung Wei, Sean T. Ma
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Publication number: 20220328697Abstract: Described is a thin film transistor which comprises: a dielectric comprising a dielectric material; a first structure adjacent to the dielectric, the first structure comprising a first material; a second structure adjacent to the first structure, the second structure comprising a second material wherein the second material is doped; a second dielectric adjacent to the second structure; a gate comprising a metal adjacent to the second dielectric; a spacer partially adjacent to the gate and the second dielectric; and a contact adjacent to the spacer.Type: ApplicationFiled: May 27, 2022Publication date: October 13, 2022Applicant: Intel CorporationInventors: Abhishek A. Sharma, Sean T. Ma, Van H. Le, Jack T. Kavalieros, Gilbert Dewey
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Patent number: 11469323Abstract: Techniques are disclosed for an integrated circuit including a ferroelectric gate stack including a ferroelectric layer, an interfacial oxide layer, and a gate electrode. The ferroelectric layer can be voltage activated to switch between two ferroelectric states. Employing such a ferroelectric layer provides a reduction in leakage current in an off-state and provides an increase in charge in an on-state. The interfacial oxide layer can be formed between the ferroelectric layer and the gate electrode. Alternatively, the ferroelectric layer can be formed between the interfacial oxide layer and the gate electrode.Type: GrantFiled: September 25, 2018Date of Patent: October 11, 2022Assignee: Intel CorporationInventors: Gilbert Dewey, Willy Rachmady, Jack T. Kavalieros, Cheng-Ying Huang, Matthew V. Metz, Sean T. Ma, Harold Kennel, Tahir Ghani
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Patent number: 11450738Abstract: Disclosed herein are source/drain regions in integrated circuit (IC) structures, as well as related methods and components. For example, in some embodiments, an IC structure may include: a channel region including a first semiconductor wire and a second semiconductor wire; and a source/drain region proximate to the channel region, wherein the source/drain region includes a first semiconductor portion proximate to an end of the first semiconductor wire, the source/drain region includes a second semiconductor portion proximate to an end of the second semiconductor wire, and the source/drain region includes a contact metal at least partially between the first semiconductor portion and the second semiconductor portion.Type: GrantFiled: March 27, 2020Date of Patent: September 20, 2022Assignee: Intel CorporationInventors: Sean T. Ma, Anand S. Murthy, Glenn A. Glass, Biswajeet Guha
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Patent number: 11450736Abstract: Disclosed herein are source/drain regions in integrated circuit (IC) structures, as well as related methods and components. For example, in some embodiments, an IC structure may include: an array of channel regions, including a first channel region and an adjacent second channel region; a first source/drain region proximate to the first channel region; a second source/drain region proximate to the second channel region; and an insulating material region at least partially between the first source/drain region and the second source/drain region.Type: GrantFiled: March 25, 2020Date of Patent: September 20, 2022Assignee: Intel CorporationInventors: Sean T. Ma, Andy Chih-Hung Wei, Guillaume Bouche
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Patent number: 11444204Abstract: Techniques and mechanisms for improved performance characteristics of a transistor device. In an embodiment, a transistor of an integrated circuit comprises a source, a drain, a gate, a gate dielectric and a semiconductor structure which adjoins the gate dielectric. The semiconductor structure is configured to provide a conductive channel between the source and drain. The semiconductor structure includes first, second and third portions, the second portion between the source and the gate, and the third portion between the drain and the gate, wherein the first portion connects the second portion and third portion to one another. A thickness of the first portion is less than another thickness of one of the second portion or the third portion. In another embodiment, the locations of thicker portions of semiconductor structure mitigate overall transistor capacitance, while a thinner intermediary portion of the semiconductor structure promotes good sub-threshold swing characteristics.Type: GrantFiled: March 28, 2018Date of Patent: September 13, 2022Assignee: Intel CorporationInventors: Abhishek A. Sharma, Van H. Le, Sean T. Ma, Jack Kavalieros, Benjamin Chu-Kung
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Patent number: 11444159Abstract: An electronic device comprises a channel layer on a buffer layer on a substrate. The channel layer has a first portion and a second portion adjacent to the first portion. The first portion comprises a first semiconductor. The second portion comprises a second semiconductor that has a bandgap greater than a bandgap of the first semiconductor.Type: GrantFiled: June 30, 2017Date of Patent: September 13, 2022Assignee: Intel CorporationInventors: Sean T. Ma, Gilbert Dewey, Willy Rachmady, Matthew V. Metz, Cheng-Ying Huang, Harold W. Kennel, Jack T. Kavalieros, Anand S. Murthy, Tahir Ghani
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Patent number: 11430866Abstract: Discussed herein is device contact sizing in integrated circuit (IC) structures. In some embodiments, an IC structure may include: a first source/drain (S/D) contact in contact with a first S/D region, and a second S/D contact in contact with a second S/D region, wherein the first S/D region and the second S/D region have a same length, and the first S/D contact and the second S/D contact have different lengths.Type: GrantFiled: March 26, 2020Date of Patent: August 30, 2022Assignee: Intel CorporationInventors: Guillaume Bouche, Andy Chih-Hung Wei, Sean T. Ma
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Patent number: 11424335Abstract: Group III-V semiconductor devices having dual workfunction gate electrodes and their methods of fabrication are described. In an example, an integrated circuit structure includes a gallium arsenide layer on a substrate. A channel structure is on the gallium arsenide layer. The channel structure includes indium, gallium and arsenic. A source structure is at a first end of the channel structure and a drain structure is at a second end of the channel structure. A gate structure is over the channel structure, the gate structure having a first workfunction material laterally adjacent a second workfunction material. The second workfunction material has a different workfunction than the first workfunction material.Type: GrantFiled: September 26, 2017Date of Patent: August 23, 2022Assignee: Intel CorporationInventors: Sean T. Ma, Willy Rachmady, Gilbert Dewey, Cheng-Ying Huang, Dipanjan Basu
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Publication number: 20220231121Abstract: Disclosed herein are isolation regions in integrated circuit (IC) structures, as well as related methods and components. For example, in some embodiments, an IC component may include: a first region including silicon; a second region including alternating layers of a second material and a third material, wherein the second material includes silicon and germanium, the third material includes silicon, and individual ones of the layers in the second region has a thickness that is less than 3 nanometers; and a third region including alternating layers of the second material and the third material, wherein individual ones of the layers in the third region has a thickness that is greater than 3 nanometers, and the second region is between the first region and the third region.Type: ApplicationFiled: April 6, 2022Publication date: July 21, 2022Applicant: Intel CorporationInventors: Guillaume Bouche, Sean T. Ma, Andy Chih-Hung Wei
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Patent number: 11367789Abstract: A buffer layer is deposited on a substrate. A first III-V semiconductor layer is deposited on the buffer layer. A second III-V semiconductor layer is deposited on the first III-V semiconductor layer. The second III-V semiconductor layer comprises a channel portion and a source/drain portion. The first III-V semiconductor layer acts as an etch stop layer to etch a portion of the second III-V semiconductor layer to form the source/drain portion.Type: GrantFiled: September 26, 2016Date of Patent: June 21, 2022Assignee: Intel CorporationInventors: Cheng-Ying Huang, Willy Rachmady, Matthew V. Metz, Gilbert Dewey, Jack T. Kavalieros, Sean T. Ma, Harold Kennel
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Patent number: 11362188Abstract: An apparatus is provided which comprises: a source and a drain with a channel region therebetween, the channel region comprising a semiconductor material, and a gate dielectric layer over at least a portion of the channel region, wherein the gate dielectric layer comprises a first thickness proximate to the source and a second thickness proximate to the drain, wherein the second thickness is greater than the first thickness, and wherein at least a portion of the gate dielectric layer comprises a linearly varying thickness over the channel region. Other embodiments are also disclosed and claimed.Type: GrantFiled: December 27, 2017Date of Patent: June 14, 2022Assignee: Intel CorporationInventors: Dipanjan Basu, Sean T. Ma, Willy Rachmady, Jack T. Kavalieros
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Patent number: 11362215Abstract: Described is a thin film transistor which comprises: a dielectric comprising a dielectric material; a first structure adjacent to the dielectric, the first structure comprising a first material; a second structure adjacent to the first structure, the second structure comprising a second material wherein the second material is doped; a second dielectric adjacent to the second structure; a gate comprising a metal adjacent to the second dielectric; a spacer partially adjacent to the gate and the second dielectric; and a contact adjacent to the spacer.Type: GrantFiled: March 30, 2018Date of Patent: June 14, 2022Assignee: INTEL CORPORATIONInventors: Abhishek A. Sharma, Sean T. Ma, Van H. Le, Jack T. Kavalieros, Gilbert Dewey