Patents by Inventor SEAN T. MA
SEAN T. MA has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20200006510Abstract: In various embodiments, the disclosure describes transistors having non-vertical gates. In one embodiment, the non-vertical gates can have a curved or wide angle gate in order to reduce the electric field crowing on the drain side of the gate edge and/or portions having corners and thereby reduce leakage current in the transistor. In one embodiment, the non-vertical gate can be generated by one or more etching steps (for example, isotropic etching steps) of an underlying channel during the fabrication of a transistor having the non-vertical gate. In one embodiment, the non-vertical gate can be generated by one or more directional etching steps that may expose various facets having predetermined orientations of a source and/or drain associated with the transistor.Type: ApplicationFiled: March 31, 2017Publication date: January 2, 2020Applicant: Intel CorporationInventors: Cheng-Ying Huang, Sean T. Ma, Willy Rachmady, Gilbert Dewey, Matthew V. Metz, Harold W. Kennel, Jack T. Kavalieros, Anand S. Murthy, Tahir Ghani
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Publication number: 20190341481Abstract: An apparatus is described. The apparatus includes a FINFET transistor. The FINFET transistor comprises a tapered subfin structure having a sidewall surface area that is large enough to induce aspect ratio trapping of lattice defects along sidewalls of the subfin structure so that the defects are substantially prevented from reaching said FINFET transistor's channel.Type: ApplicationFiled: June 30, 2016Publication date: November 7, 2019Inventors: Gilbert DEWEY, Willy RACHMADY, Matthew V. METZ, Jack T. KAVALIEROS, Chandra S. MOHAPATRA, Sean T. MA, Tahir GHANI, Anand S. MURTHY
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Publication number: 20190326175Abstract: An apparatus is provided which comprises: a fin; a layer formed on the fin, the layer dividing the fin in a first section and a second section; a first device formed on the first section of the fin; and a second device formed on the second section of the fin.Type: ApplicationFiled: March 30, 2017Publication date: October 24, 2019Applicant: Intel CorporationInventors: Aaron D. Lilak, Sean T. Ma, Justin R. Weber, Patrick Morrow, Rishabh Mehandru
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Publication number: 20190305138Abstract: Described is a thin film transistor which comprises: a dielectric comprising a dielectric material; a first structure adjacent to the dielectric, the first structure comprising a first material; a second structure adjacent to the first structure, the second structure comprising a second material wherein the second material is doped; a second dielectric adjacent to the second structure; a gate comprising a metal adjacent to the second dielectric; a spacer partially adjacent to the gate and the second dielectric; and a contact adjacent to the spacer.Type: ApplicationFiled: March 30, 2018Publication date: October 3, 2019Applicant: Intel CorporationInventors: Abhishek A. Sharma, Sean T. Ma, Van H. Le, Jack T. Kavalieros, Gilbert Dewey
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Publication number: 20190305101Abstract: Techniques and mechanisms for improved performance characteristics of a transistor device. In an embodiment, a transistor of an integrated circuit comprises a source, a drain, a gate, a gate dielectric and a semiconductor structure which adjoins the gate dielectric. The semiconductor structure is configured to provide a conductive channel between the source and drain. The semiconductor structure includes first, second and third portions, the second portion between the source and the gate, and the third portion between the drain and the gate, wherein the first portion connects the second portion and third portion to one another. A thickness of the first portion is less than another thickness of one of the second portion or the third portion. In another embodiment, the locations of thicker portions of semiconductor structure mitigate overall transistor capacitance, while a thinner intermediary portion of the semiconductor structure promotes good sub-threshold swing characteristics.Type: ApplicationFiled: March 28, 2018Publication date: October 3, 2019Applicant: Intel CorporationInventors: Abhishek A. Sharma, Van H. Le, Sean T. Ma, Jack Kavalieros, Benjamin Chu-Kung
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Publication number: 20190296145Abstract: A buffer layer is deposited on a substrate. A first III-V semiconductor layer is deposited on the buffer layer. A second III-V semiconductor layer is deposited on the first III-V semiconductor layer. The second III-V semiconductor layer comprises a channel portion and a source/drain portion. The first III-V semiconductor layer acts as an etch stop layer to etch a portion of the second III-V semiconductor layer to form the source/drain portion.Type: ApplicationFiled: September 26, 2016Publication date: September 26, 2019Inventors: Cheng-Ying HUANG, Willy RACHMADY, Matthew V. METZ, Gilbert DEWEY, Jack T. KAVALIEROS, Sean T. MA, Harold KENNEL
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Patent number: 10411007Abstract: Monolithic FETs including a channel region in a first semiconductor material disposed over a substrate. While a mask, such as a gate stack or sacrificial gate stack, is covering a channel region, a semiconductor spacer of a semiconductor material with a band offset relative to the channel material is grown, for example on at least a drain end of the channel region to introduce at least one charge carrier-blocking band offset between the channel semiconductor and a drain region of a third III-V semiconductor material. In some N-type transistor embodiments, the carrier-blocking band offset is a conduction band offset of at least 0.1 eV. A wider band gap and/or a blocking conduction band offset may contribute to reduced gate induced drain leakage (GIDL). Source/drain regions couple electrically to the channel region through the semiconductor spacer, which may be substantially undoped (i.e. intrinsic) or doped.Type: GrantFiled: September 25, 2015Date of Patent: September 10, 2019Assignee: Intel CorporationInventors: Gilbert Dewey, Willy Rachmady, Matthew V. Metz, Chandra S. Mohapatra, Sean T. Ma, Jack T. Kavalieros, Anand S. Murthy, Tahir Ghani
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Publication number: 20190267289Abstract: A transistor device comprising a channel disposed on a substrate between a source and a drain, a gate electrode disposed on the channel, wherein the channel comprises a channel material that is separated from a body of the same material on a substrate. A method comprising forming a trench in a dielectric layer on an integrated circuit substrate, the trench comprising dimensions for a transistor body including a width; depositing a spacer layer in a portion of the trench, the spacer layer narrowing the width of the trench; forming a channel material in the trench through the spacer layer; recessing the dielectric layer to define a first portion of the channel material exposed and a second portion of the channel material in the trench; and separating the first portion of the channel material from the second portion of the channel material.Type: ApplicationFiled: September 30, 2016Publication date: August 29, 2019Applicant: Intel CorporationInventors: Gilbert DEWEY, Matthew V. METZ, Sean T. MA, Cheng-Ying HUANG, Tahir GHANI, Anand S. MURTHY, Harold W. KENNEL, Nicholas G. MINUTILLO, Jack T. KAVALIEROS, Willy RACHMADY
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Publication number: 20190214500Abstract: An embodiment includes a transistor comprising: first, second, and third layers each including a group III-V material; a channel included in the second layer, which is between the first and third layers; and a gate having first and second gate portions; wherein (a)(i) the first and third layers are doped, (a)(ii) the channel is between the first and second gate portions and the second gate portion is between the channel and a substrate, (a)(iii) a first axis intersects the first, second, and third layers but not the first gate portion, and (a)(iv) a second axis, parallel to the first axis, intersects the first and second gate portions and the channel. Other embodiments are described herein.Type: ApplicationFiled: September 30, 2016Publication date: July 11, 2019Inventors: Cheng-Ying Huang, Matthew V. Metz, Gilbert Dewey, Willy Rachmady, Jack T. Kavalieros, Sean T. Ma
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Patent number: 10340374Abstract: Monolithic FETs including a channel region of a first semiconductor material disposed over a substrate. While a mask, such as a gate stack or sacrificial gate stack, is covering the channel region, an impurity-doped compositionally graded semiconductor is grown, for example on at least a drain end of the channel region to introduce a carrier-blocking conduction band offset and/or a wider band gap within the drain region of the transistor. In some embodiments, the compositional grade induces a carrier-blocking band offset of at least 0.25 eV. The wider band gap and/or band offset contributes to a reduced gate induced drain leakage (GIDL). The impurity-doped semiconductor may be compositionally graded back down from the retrograded composition to a suitably narrow band gap material providing good ohmic contact. In some embodiments, the impurity-doped compositionally graded semiconductor growth is integrated into a gate-last, source/drain regrowth finFET fabrication process.Type: GrantFiled: September 25, 2015Date of Patent: July 2, 2019Assignee: Intel CorporationInventors: Gilbert Dewey, Willy Rachmady, Matthew V. Metz, Chandra S. Mohapatra, Sean T. Ma, Jack T. Kavalieros, Anand S. Murthy, Tahir Ghani
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Publication number: 20190198658Abstract: Techniques are disclosed for forming group III-V material transistors employing nitride-based dopant diffusion barrier layers. The techniques can include growing the dilute nitride-based barrier layer as a relatively thin layer of III-V material in the sub-channel (or sub-fin) region of a transistor, near the substrate/III-V material interface, for example. Such a nitride-based barrier layer can be used to trap atoms from the substrate at vacancy sites within the III-V material. Therefore, the barrier layer can arrest substrate atoms from diffusing in an undesired manner by protecting the sub-channel layer from being unintentionally doped due to subsequent processing in the transistor fabrication. In addition, by forming the barrier layer pseudomorphically, the lattice mismatch of the barrier layer with the sub-channel layer in the heterojunction stack becomes insignificant. In some embodiments, the group III-V alloyed with nitrogen (N) material may include an N concentration of less than 5, 2, or 1.Type: ApplicationFiled: September 29, 2016Publication date: June 27, 2019Applicant: INTEL CORPORATIONInventors: Chandra S. Mohapatra, Harold W. Kennel, Glenn A. Glass, Willy Rachmady, Anand S. Murthy, Gilbert Dewey, Jack T. Kavalieros, Tahir Ghani, Matthew V. Metz, Sean T. Ma
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Publication number: 20190189753Abstract: Semiconductor devices, computing devices, and related methods are disclosed herein. A semiconductor device includes a seed material, an epitaxial material in contact with the seed material, and at least one quantum region including an elastic stiffness that is greater than an elastic stiffness of the epitaxial material. The epitaxial material has lattice parameters that are different from lattice parameters of the seed material by at least a threshold amount. Lattice parameters of the quantum region are within the threshold amount of the lattice parameters of the epitaxial material. A method includes disposing an epitaxial material on a seed material, disposing a quantum region on the epitaxial material, and disposing the epitaxial material on the quantum region.Type: ApplicationFiled: September 30, 2016Publication date: June 20, 2019Applicant: INTEL CORPORATIONInventors: Matthew Metz, Gilbert Dewey, Harold W. Kennel, Cheng-Ying Huang, Sean T. Ma, Willy Rachmady
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Publication number: 20190172941Abstract: Embodiments are generally directed to a semiconductor device with released source and drain. An embodiment of a method includes etching a buffer layer of a semiconductor device to form a gate trench under a gate channel portion of a channel layer of the device; filling the gate trench with an oxide material to form an oxide isolation layer; etching one or more source/drain contact trenches in an interlayer dielectric (ILD) layer for source and drain regions of the device; etching the oxide isolation layer within the one or more source/drain contact trenches to form one or more cavities under a source/drain channel in the source and drain regions, wherein the etching of each contact trench is to expose all sides of the source/drain channel; and depositing contact metal in the one or more contact trenches, including depositing the contact metal in the cavities under the source/drain channel.Type: ApplicationFiled: July 2, 2016Publication date: June 6, 2019Applicant: Intel CorporationInventors: Willy RACHMADY, Sanaz K. GARDNER, Chandra S. MOHAPATRA, Matthew V. METZ, Gilbert DEWEY, Sean T. MA, Jack T. KAVALIEROS, Anand S. MURTHY, Tahir GHANI
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Publication number: 20190172950Abstract: An integrated circuit apparatus including a body; a transistor formed on a first portion of the body, the transistor including a gate stack and a channel defined in the body between a source and a drain; and a plug formed in a second portion of the body, the plug including a material operable to impart a stress on the first portion of the body. A method of forming an integrated circuit device including forming a transistor body on a substrate; forming a transistor device in a first portion of the transistor body on a first side of the substrate; and dividing the transistor body into at least the first portion and a second portion with a plug in the transistor body, the plug including a material operable to impart a stress on the first portion of the body, wherein the material is introduced through a second side of the substrate.Type: ApplicationFiled: September 30, 2016Publication date: June 6, 2019Inventors: Aaron D. LILAK, Sean T. MA, Rishabh MEHANDRU, Patrick MORROW, Stephen M. CEA
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Publication number: 20190148512Abstract: An apparatus including a transistor device including a body including a channel region between a source region and a drain region; and a gate stack on the body in the channel region, wherein at least one of the source region and the drain region of the body include a contact surface between opposing sidewalls and the contact surface includes a profile such that a height dimension of the contact surface is greater at the sidewalls than at a point between the sidewalls. A method including forming a transistor device body on a circuit substrate, the transistor device body dimension defining a channel region between a source region and a drain region; forming a groove in the body in at least one of the source region and the drain region; and forming a gate stack on the body in the channel region.Type: ApplicationFiled: July 2, 2016Publication date: May 16, 2019Applicant: Intel CorporationInventors: Willy RACHMADY, Matthew V. METZ, Gilbert DEWEY, Sean T. MA, Chandra S. MOHAPATRA, Sanaz K. GARDNER, Jack T. KAVALIEROS, Anand S. MURTHY, Tahir GHANI
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Publication number: 20190140054Abstract: An apparatus is described. The apparatus includes a FINFET device having a channel. The channel is composed of a first semiconductor material that is epitaxially grown on a subfin structure beneath the channel. The subfin structure is composed of a second semiconductor material that is different than the first semiconductor material. The subfm structure is epitaxially grown on a substrate composed of a third semiconductor material that is different than the first and second semiconductor materials. The subfin structure has a doped region to substantially impede leakage currents between the channel and the substrate.Type: ApplicationFiled: June 30, 2016Publication date: May 9, 2019Inventors: Gilbert DEWEY, Matthew V. METZ, Willy RACHMADY, Anand S. MURTHY, Chandra S. MOHAPATRA, Tahir GHANI, Sean T. MA, Jack T. KAVALIEROS
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Publication number: 20190035897Abstract: An apparatus including a transistor device on a substrate including an intrinsic layer including a channel; a source and a drain on opposite sides of the channel; and a diffusion barrier between the intrinsic layer and each of the source and the drain, the diffusion barrier including a conduction band energy that is less than a conduction band energy of the channel and greater than a material of the source and drain. A method including defining an area of an intrinsic layer on a substrate for a channel of a transistor device; forming a diffusion barrier layer in an area defined for a source and a drain; and forming a source on the diffusion barrier layer in the area defined for the source and forming a drain in the area defined for the drain.Type: ApplicationFiled: April 1, 2016Publication date: January 31, 2019Inventors: Chandra S. MOHAPATRA, Harold W. KENNEL, Glenn A. GLASS, Will RACHMADY, Gilbert DEWEY, Jack T. KAVALIEROS, Anand S. MURTHY, Tahir GHANI, Matthew V. METZ, Sean T. MA
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Publication number: 20180350798Abstract: Monolithic FETs including a channel region in a first semiconductor material disposed over a substrate. While a mask, such as a gate stack or sacrificial gate stack, is covering a channel region, a semiconductor spacer of a semiconductor material with a band offset relative to the channel material is grown, for example on at least a drain end of the channel region to introduce at least one charge carrier-blocking band offset between the channel semiconductor and a drain region of a third III-V semiconductor material. In some N-type transistor embodiments, the carrier-blocking band offset is a conduction band offset of at least 0.1 eV. A wider band gap and/or a blocking conduction band offset may contribute to reduced gate induced drain leakage (GIDL). Source/drain regions couple electrically to the channel region through the semiconductor spacer, which may be substantially undoped (i.e. intrinsic) or doped.Type: ApplicationFiled: September 25, 2015Publication date: December 6, 2018Applicant: Intel CorporationInventors: Gilbert Dewey, Willy Rachmady, Matthew V. Metz, Chandra S. Mohapatra, Sean T. Ma, Jack T. Kavalieros, Anand S. Murthy, Tahir Ghani
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Publication number: 20180315827Abstract: An apparatus including a non-planar body on a substrate, the body including a channel on a blocking material, and a gate stack on the body, the gate stack including a first gate electrode material including a first work function disposed on the channel material and a second gate electrode material including a second work function different from the first work function disposed on the channel material and on the blocking material. A method including forming a non-planar body on a substrate, the non-planar body including a channel on a blocking material, and forming a gate stack on the body, the gate stack including a first gate electrode material including a first work function disposed on the channel and a second gate electrode material including a second work function different from the first work function disposed on the channel and on the blocking material.Type: ApplicationFiled: December 17, 2015Publication date: November 1, 2018Inventors: Sean T. MA, Willy RACHMADY, Matthew V. METZ, Chandra S. MOHAPATRA, Gilbert DEWEY, Nadia M. RAHHAL-ORABI, Jack T. KAVALIEROS, Anand S. MURTHY
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Publication number: 20180261694Abstract: Monolithic FETs including a channel region of a first semiconductor material disposed over a substrate. While a mask, such as a gate stack or sacrificial gate stack, is covering the channel region, an impurity-doped compositionally graded semiconductor is grown, for example on at least a drain end of the channel region to introduce a carrier-blocking conduction band offset and/or a wider band gap within the drain region of the transistor. In some embodiments, the compositional grade induces a carrier-blocking band offset of at least 0.25 eV. The wider band gap and/or band offset contributes to a reduced gate induced drain leakage (GIDL). The impurity-doped semiconductor may be compositionally graded back down from the retrograded composition to a suitably narrow band gap material providing good ohmic contact. In some embodiments, the impurity-doped compositionally graded semiconductor growth is integrated into a gate-last, source/drain regrowth finFET fabrication process.Type: ApplicationFiled: September 25, 2015Publication date: September 13, 2018Applicant: Intel CorporationInventors: Gilbert Dewey, Willy Rachmady, Matthew V. Metz, Chandra S. Mohapatra, Sean T. Ma, Jack T. Kavalieros, Anand S. Murthy, Tahir Ghani