Patents by Inventor Sei-Seung Yoon
Sei-Seung Yoon has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20150228314Abstract: A data latch includes a first stage configured to receive an input in a first voltage domain, and a second stage. The second stage includes a level shifter configured to shift the input from the first voltage domain to a second voltage domain, and an output circuit having a pull down circuit and pull up circuit arranged to generate an output in the second voltage domain, wherein the pull down circuit is responsive to the input in the first voltage domain and the pull up circuit is responsive to the input in the second voltage domain.Type: ApplicationFiled: February 10, 2014Publication date: August 13, 2015Applicant: QUALCOMM IncorporatedInventors: Xiaoliang BAI, Arun Babu PALLERLA, Sei Seung YOON
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Patent number: 9082465Abstract: A memory circuit is provided comprising a plurality of bit cells coupled to a bit line that permits accessing information from each of the plurality of bit cells. A sense inverter is coupled to an output of the bit line. A keeper circuit has an output coupled to the bit line to compensate for current leakage from the plurality of bit cells. The keeper circuit may comprise an n-channel metal-oxide-silicon (NMOS) transistor in series with a p-channel metal-oxide-silicon (PMOS) transistor.Type: GrantFiled: February 12, 2013Date of Patent: July 14, 2015Assignee: QUALCOMM IncorporatedInventors: Balachander Ganesan, Ritu Chaba, Sei Seung Yoon
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Patent number: 9082481Abstract: A static, ternary content addressable memory (TCAM) includes a key cell and a mask cell coupled to intermediate match lines. The key cell is coupled to a first pull-down transistor and a first pull-up transistor. The mask cell is coupled to a second pull-down transistor and a second pull-up transistor. The first pull-down transistor and second pull-down transistor are connected in parallel and the first pull-up transistor and second pull-up transistor are connected in series. A match line output is also coupled to the first pull-down transistor and second pull-down transistor and further coupled to the first pull-up transistor and second pull-up transistor.Type: GrantFiled: October 1, 2014Date of Patent: July 14, 2015Assignee: QUALCOMM IncorporatedInventors: Esin Terzioglu, Nishith Desai, Rakesh Vattikonda, ChangHo Jung, Sei Seung Yoon
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Patent number: 9082498Abstract: A thin gate-oxide dual-mode PMOS transistor is disclosed that has a first mode of operation in which a switched n-well for the dual-mode PMOS transistor is biased to a high voltage. The dual-mode PMOS transistor has a second mode of operation in which the switched n-well is biased to a low voltage that is lower than the high voltage. The dual-mode PMOS transistor has a size and gate-oxide thickness each having a magnitude that cannot accommodate a permanent tie to the high voltage. An n-well voltage switching circuit is configured to bias the switched n-well to prevent voltage damage to the dual-mode PMOS transistor without the use of native transistors.Type: GrantFiled: August 8, 2013Date of Patent: July 14, 2015Assignee: QUALCOMM IncorporatedInventors: Gregory Ameriada Uvieghara, Sei Seung Yoon
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Patent number: 9071239Abstract: A semiconductor apparatus is provided herein for reducing power when transmitting data between a first device and a second device in the semiconductor apparatus. Additional circuitry is added to the semiconductor apparatus to create a communication system that decreases a number of state changes for each signal line of a data bus between the first device and the second device for all communications. The additional circuitry includes a decoder coupled to receive and convert a value from the first device for transmission over the data bus to an encoder that provides a recovered (i.e., re-encoded) version of the value to the second device. One or more multiplexers may also be included in the additional circuitry to support any number of devices.Type: GrantFiled: March 13, 2013Date of Patent: June 30, 2015Assignee: QUALCOMM IncorporatedInventors: Chulmin Jung, Sei Seung Yoon, Esin Terzioglu, Hari Ananthanarayanan, Venugopal Boynapalli
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Patent number: 9064556Abstract: A pseudo dual port (PDP) memory is disclosed having a write driver that selectively precharges only one of a bit line and a complement bit line in a bit line pair responsive to a bit value to be written into an accessed bitcell while discharging a remaining one of the bit line and the complement bit line. In this fashion, the cleanup time between a read operation and a write operation during a read/write clock cycle is advantageously reduced.Type: GrantFiled: October 23, 2013Date of Patent: June 23, 2015Assignee: QUALCOMM IncorporatedInventors: Chirag Gulati, Lakshmikantha Holla Vakwadi, Sei Seung Yoon
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Publication number: 20150161067Abstract: A reduced-area interconnect allows client to client communication using an XBAR architecture. An XBAR compiler generates chip designs with XBAR data paths structured to reduce area and energy consumption. Tri-state buffers inserted into XBAR data paths are configured to direct data between clients and sources on a number of data paths corresponding to the lesser of the number of clients and the number of sources. Interface area and power consumption is reduced by eliminating paths that are not always being used.Type: ApplicationFiled: December 6, 2013Publication date: June 11, 2015Applicant: QUALCOMM IncorporatedInventors: Kevin Robert BOWLES, Hari Madhava RAO, Sei Seung YOON
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Patent number: 9030863Abstract: An integrated circuit includes one or more bit cells, a word line coupled to the one or more bit cells, and a dummy word line arranged with the word line to have a capacitance therebetween. The capacitance provides a voltage boost or reduction of the word line to assist read and write operations.Type: GrantFiled: September 26, 2013Date of Patent: May 12, 2015Assignee: QUALCOMM IncorporatedInventors: Chirag Gulati, Rakesh Kumar Sinha, Ritu Chaba, Sei Seung Yoon
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Publication number: 20150109865Abstract: A pseudo dual port (PDP) memory is disclosed having a write driver that selectively precharges only one of a bit line and a complement bit line in a bit line pair responsive to a bit value to be written into an accessed bitcell while discharging a remaining one of the bit line and the complement bit line. In this fashion, the cleanup time between a read operation and a write operation during a read/write clock cycle is advantageously reduced.Type: ApplicationFiled: October 23, 2013Publication date: April 23, 2015Applicant: QUALCOMM IncorporatedInventors: Chirag Gulati, Lakshmikantha Holla Vakwadi, Sei-Seung Yoon
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Publication number: 20150085554Abstract: A static, ternary content addressable memory (TCAM) includes a key cell and a mask cell coupled to intermediate match lines. The key cell is coupled to a first pull-down transistor and a first pull-up transistor. The mask cell is coupled to a second pull-down transistor and a second pull-up transistor. The first pull-down transistor and second pull-down transistor are connected in parallel and the first pull-up transistor and second pull-up transistor are connected in series. A match line output is also coupled to the first pull-down transistor and second pull-down transistor and further coupled to the first pull-up transistor and second pull-up transistor.Type: ApplicationFiled: October 1, 2014Publication date: March 26, 2015Inventors: Esin Terzioglu, Nishith Desai, Rakesh Vattikonda, ChangHo Jung, Sei Seung Yoon
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Publication number: 20150085568Abstract: An integrated circuit includes one or more bit cells, a word line coupled to the one or more bit cells, and a dummy word line arranged with the word line to have a capacitance therebetween. The capacitance provides a voltage boost or reduction of the word line to assist read and write operations.Type: ApplicationFiled: September 26, 2013Publication date: March 26, 2015Applicant: QUALCOMM IncorporatedInventors: Chirag GULATI, Rakesh SINHA, Ritu CHABA, Sei Seung YOON
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Publication number: 20150067290Abstract: Disclosed are various apparatuses and methods for memory access time tracking in dual-rail systems. An apparatus may include a memory coupled to a first voltage rail and having a data output, a data circuit coupled to a second voltage rail and configured to receive the data output from the memory, and a timing circuit configured to adjust an access time of the memory based on a second voltage rail level. A method may include determining a voltage rail level of a data circuit, adjusting the access time of the memory based on the voltage rail level of the data circuit, outputting data from the memory, and receiving the output data by the data circuit.Type: ApplicationFiled: September 4, 2013Publication date: March 5, 2015Applicant: QUALCOMM IncorporatedInventors: Ritu CHABA, Balachander GANESAN, ChangHo JUNG, Sei Seung YOON
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Publication number: 20150063046Abstract: Disclosed are various apparatuses and methods for a memory with a multiple word line design. A memory timing circuit may include a dummy word line including a first portion and a second portion and further including capacitative loading that is lumped in the second portion of the dummy word line, a first transistor connected to the first portion of the dummy word line and configured to charge the dummy word line, and a second transistor connected to the second portion of the dummy word line and configured to discharge the dummy word line. A method may include charging a dummy word line using a first transistor, and discharging the dummy word line using a second transistor, wherein the dummy word line includes a first portion and a second portion and further includes capacitative loading that is lumped in the second portion of the dummy word line.Type: ApplicationFiled: September 4, 2013Publication date: March 5, 2015Applicant: QUALCOMM INCORPORATEDInventors: Rakesh Kumar SINHA, Chirag GULATI, Ritu CHABA, Sei Seung YOON
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Patent number: 8971096Abstract: A multiport bitcell including a pair of cross-coupled inverters is provided with increased write speed and enhanced operating voltage range by the selective isolation of a first one of the cross-coupled inverters from a power supply and ground during a write operation. The write operation occurs through a write port that includes a transmission gate configured to couple a first node driven by the first cross-coupled inverter to a write bit line. A remaining second cross-coupled inverter in the bitcell is configured to drive a second node that couples to a plurality of read ports.Type: GrantFiled: July 29, 2013Date of Patent: March 3, 2015Assignee: QUALCOMM IncorporatedInventors: Changho Jung, Rakesh Vattikonda, Nishith Desai, Sei Seung Yoon
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Patent number: 8958226Abstract: A static, ternary content addressable memory (TCAM) includes a key cell and a mask cell coupled to intermediate match lines. The key cell is coupled to a first pull-down transistor and a first pull-up transistor. The mask cell is coupled to a second pull-down transistor and a second pull-up transistor. The first pull-down transistor and second pull-down transistor are connected in parallel and the first pull-up transistor and second pull-up transistor are connected in series. A match line output is also coupled to the first pull-down transistor and second pull-down transistor and further coupled to the first pull-up transistor and second pull-up transistor.Type: GrantFiled: December 28, 2012Date of Patent: February 17, 2015Assignee: QUALCOMM IncorporatedInventors: Esin Terzioglu, Nishith Desai, Rakesh Vattikonda, ChangHo Jung, Sei Seung Yoon
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Publication number: 20150043265Abstract: A thin gate-oxide dual-mode PMOS transistor is disclosed that has a first mode of operation in which a switched n-well for the dual-mode PMOS transistor is biased to a high voltage. The dual-mode PMOS transistor has a second mode of operation in which the switched n-well is biased to a low voltage that is lower than the high voltage. The dual-mode PMOS transistor has a size and gate-oxide thickness each having a magnitude that cannot accommodate a permanent tie to the high voltage. An n-well voltage switching circuit is configured to bias the switched n-well to prevent voltage damage to the dual-mode PMOS transistor without the use of native transistors.Type: ApplicationFiled: August 8, 2013Publication date: February 12, 2015Applicant: QUALCOMM IncorporatedInventors: Gregory Ameriada Uvieghara, Sei Seung Yoon
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Publication number: 20150029782Abstract: A multiport bitcell including a pair of cross-coupled inverters is provided with increased write speed and enhanced operating voltage range by the selective isolation of a first one of the cross-coupled inverters from a power supply and ground during a write operation. The write operation occurs through a write port that includes a transmission gate configured to couple a first node driven by the first cross-coupled inverter to a write bit line. A remaining second cross-coupled inverter in the bitcell is configured to drive a second node that couples to a plurality of read ports.Type: ApplicationFiled: July 29, 2013Publication date: January 29, 2015Applicant: QUALCOMM IncorporatedInventors: Changho Jung, Rakesh Vattikonda, Nishith Desai, Sei Seung Yoon
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Publication number: 20150029778Abstract: A mask-programmed read-only memory (MROM) has a plurality of column line pairs, each having a bit line and a complement bit line. The MROM includes a plurality of memory cells corresponding to a plurality of intersections between the column line pairs and a plurality of word liens. Each memory cell includes a high Vt transistor and a low Vt transistor.Type: ApplicationFiled: July 29, 2013Publication date: January 29, 2015Applicant: QUALCOMM IncorporatedInventors: Sei Seung Yoon, Chulmin Jung, Esin Terzioglu, Steven Millendorf
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Patent number: 8934278Abstract: A method within a hybrid ternary content addressable memory (TCAM) includes comparing a first portion of a search word to a first portion of a stored word in a first TCAM stage. The method further includes interfacing an output of the first TCAM stage to an input of the second TCAM stage. The method also includes comparing a second portion of the search word to a second portion of the stored word in a second TCAM stage when the first portion of the search word matches the first portion of the stored word. The first TCAM stage is different from the second TCAM stage.Type: GrantFiled: December 28, 2012Date of Patent: January 13, 2015Assignee: QUALCOMM IncorporatedInventors: Rakesh Vattikonda, Nishith Desai, ChangHo Jung, Sei Seung Yoon, Esin Terzioglu
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Patent number: 8929153Abstract: Disclosed are various apparatuses and methods for a memory with a multiple read word line design. A memory may include a plurality of bit cells arranged in a row, a first read word line connected to a first subset of the plurality of bit cells, and a second read word line connected to a second subset of the plurality of bit cells, wherein the first and second subsets are located in the same row of bit cells. A method may include asserting, during a first read operation, a first read word line connected to a first subset of a plurality of bit cells arranged in a row of bit cells, and asserting, during a second read operation, a second read word line connected to a second subset of the plurality of bit cells, wherein the first and second subsets are located in the same row of bit cells.Type: GrantFiled: August 23, 2013Date of Patent: January 6, 2015Assignee: QUALCOMM IncorporatedInventors: Chirag Gulati, Rakesh Kumar Sinha, Ritu Chaba, Sei Seung Yoon