Patents by Inventor Seiichi Nakatani

Seiichi Nakatani has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20100164061
    Abstract: A semiconductor chip comprising a capacitor capable of effectively controlling the voltage drop of an LSI is provided. A semiconductor substrate is provided with an element electrode having at least its surface constituted of an aluminum electrode. The surface of the aluminum electrode is roughened. An oxide film is provided on the aluminum electrode. A conductive film is provided on the oxide film. The aluminum electrode, oxide film and conductive film form a capacitor.
    Type: Application
    Filed: August 24, 2007
    Publication date: July 1, 2010
    Inventors: Koichi Hirano, Tetsuyoshi Ogura, Seiichi Nakatani
  • Publication number: 20100148376
    Abstract: A flip chip mounting process includes the steps of supplying a resin (13) containing solder powder and a convection additive (12) onto a wiring substrate (10) having a plurality of electrode terminals (11), then bringing a semiconductor chip (20) having a plurality of connecting terminals (11) into contact with a surface of the supplied resin (13), and then heating the wiring substrate (10) to a temperature that enables the solder powder to melt. The heating step is carried out at a temperature that is higher than the boiling point of the convection additive (12) to allow the boiling convection additive (12) to move within the resin (12). During this heating step, the melted solder powder is allowed to self-assemble into the region between each electrode terminal (11) of the wiring substrate (10) and each connecting terminal (21) of the semiconductor chip to form an electrical connection between each electrode terminal (11) and each connecting terminal (21).
    Type: Application
    Filed: March 4, 2010
    Publication date: June 17, 2010
    Inventors: Seiji Karashima, Yoshihisa Yamashita, Satoru Tomekawa, Takashi Kitae, Seiichi Nakatani
  • Patent number: 7732920
    Abstract: The flip chip mounted body of the present invention includes: a circuit board (213) having a plurality of connection terminals (211); a semiconductor chip (206) having a plurality of electrode terminals (207) that are disposed opposing the connection terminals (211); and a porous sheet (205) having a box shape that is provided on an opposite side of a formation surface of the electrode terminal (207) of the semiconductor chip (206), is folded on an outer periphery of the semiconductor chip (206) on the formation surface side of the electrode terminal (207) and is in contact with the circuit board (213), wherein the connection terminal (211) of the circuit board (213) and the electrode terminal (207) of the semiconductor chip (206) are connected electrically via a solder layer (215), and the circuit board (213) and the semiconductor chip (206) are fixed by a resin (217).
    Type: Grant
    Filed: March 14, 2006
    Date of Patent: June 8, 2010
    Assignee: Panasonic Corporation
    Inventors: Seiichi Nakatani, Takashi Kitae, Yoshihisa Yamashita, Takashi Ichiryu, Seiji Karashima
  • Publication number: 20100133664
    Abstract: A module that can not only achieve the reduction in size and manufacturing cost but also be impervious to noise due to electromagnetic waves, and a mounted structure using the same are provided. A module (1) includes a substrate (12) and a plurality of semiconductor packages (11a, 11b), each including a semiconductor chip (10), mounted on the substrate (12). Each of the plurality of semiconductor packages (11a, 11b) includes a first radio communication element (16) for transmitting and receiving a signal between the semiconductor chips (10) in the plurality of semiconductor packages (11a, 11b) by radio communication, and the first radio communication element (16) is constituted independently of the semiconductor chip (10).
    Type: Application
    Filed: January 4, 2010
    Publication date: June 3, 2010
    Applicant: PANASONIC CORPORATION
    Inventors: Seiichi Nakatani, Tsutomu Mitani
  • Patent number: 7726545
    Abstract: A flip chip mounting process or a bump-forming process according to the present invention is characterized in that electrically-conductive particles are fixed on electrodes formed on an electronic component. A composition comprising solder powder, a convection additive and a resin component is supplied onto a surface of the electronic component, the surface is provided with the electrodes. The supplied composition is heated up to a temperature enabling the solder powder to melt. As a result, the convection additive boils or is decomposed so as to generate a gas. The generated gas produces a convection phenomenon within the supplied composition. Since the convection phenomenon promotes the movement of the solder powder, the solder powder can move freely within the composition. The electrically-conductive particles serve as nuclei for the solder powder to self-assemble and grow.
    Type: Grant
    Filed: March 13, 2006
    Date of Patent: June 1, 2010
    Assignee: Panasonic Corporation
    Inventors: Takashi Ichiryu, Seiichi Nakatani, Seiji Karashima, Yoshihiro Tomita, Koichi Hirano, Toshio Fujii
  • Patent number: 7714444
    Abstract: The present invention provides a conductive resin composition for connecting electrodes electrically, in which metal particles are dispersed in a flowing medium, wherein the flowing medium includes a first flowing medium that has relatively high wettability with the metal particles and a second flowing medium that has relatively low wettability with the metal particles, and the first flowing medium and the second flowing medium are dispersed in a state of being incompatible with each other. Thereby, a flip chip packaging method that can be applied to flip chip packaging of LSI and has high productivity and high reliability is provided.
    Type: Grant
    Filed: April 16, 2009
    Date of Patent: May 11, 2010
    Assignee: Panasonic Corporation
    Inventors: Seiichi Nakatani, Seiji Karashima, Takashi Kitae, Susumu Sawada
  • Patent number: 7713787
    Abstract: A mounted body (100) of the present invention includes: a semiconductor element (10) having a surface (10a) on which element electrodes (12) are formed and a rear surface (10b) opposing the surface (10a); and a mounting board (30) on which wiring patterns (35) each having an electrode terminal (32) are formed. The rear surface (10b) of the semiconductor element (10) is in contact with the mounting board (30), and the element electrodes (12) of the semiconductor element (10) are connected electrically to the electrode terminals (32) of the wiring pattern (35) formed on the mounting board (30) via solder connectors (20) formed of solder particles assembled into a bridge shape. With this configuration, fine pitch connection between the element electrodes of the semiconductor element and the electrode terminals of the mounting board becomes possible.
    Type: Grant
    Filed: February 21, 2006
    Date of Patent: May 11, 2010
    Assignee: Panasonic Corporation
    Inventors: Toshiyuki Kojima, Seiichi Nakatani, Yoshihisa Yamashita, Takashi Kitae, Shingo Komatsu
  • Patent number: 7689129
    Abstract: A parallel computation apparatus as a multiprocessor includes functional modules as a plurality of processors having an optical communication function and capable of mutually cooperating, and an optical transmission line interconnecting the plurality of processors. Among the plurality of functional modules, the first functional module having a first information processing capacity has a function of determining whether information processing of a first information processing amount can be completed based on the first information processing capacity, and outputting a second information processing amount obtained by subtracting an information processing amount based on the first information processing capacity from the first information processing amount to at least one of the other functional modules.
    Type: Grant
    Filed: August 10, 2005
    Date of Patent: March 30, 2010
    Assignee: Panasonic Corporation
    Inventors: Seiji Karashima, Seiichi Nakatani, Yoshiyuki Saito
  • Publication number: 20100044091
    Abstract: An electrode structure 100 on which a solder bump is placed includes an electrode pattern 50 made of an electrode-constituting material selected from the group consisting of Cu, Al, Cr, and Ti, a Ni layer 52 formed on a part of the electrode pattern 50, a Pd layer 54 formed on at least a part of a region other than the part of the electrode pattern 50, and an Au layer 56 formed on the Ni layer 52 and the Pd layer 54.
    Type: Application
    Filed: November 27, 2007
    Publication date: February 25, 2010
    Applicant: PANASONIC CORPORATION
    Inventors: Yasushi Taniguchi, Seiichi Nakatani, Takashi Kitae, Seiji Karashima, Kenichi Hotehama
  • Patent number: 7667974
    Abstract: A module that can not only achieve the reduction in size and manufacturing cost but also be impervious to noise due to electromagnetic waves, and a mounted structure using the same are provided. A module (1) includes a substrate (12) and a plurality of semiconductor packages (11a, 11b), each including a semiconductor chip (10), mounted on the substrate (12). Each of the plurality of semiconductor packages (11a, 11b) includes a first radio communication element (16) for transmitting and receiving a signal between the semiconductor chips (10) in the plurality of semiconductor packages (11a, 11b) by radio communication, and the first radio communication element (16) is constituted independently of the semiconductor chip (10).
    Type: Grant
    Filed: January 20, 2005
    Date of Patent: February 23, 2010
    Assignee: Panasonic Corporation
    Inventors: Seiichi Nakatani, Tsutomu Mitani
  • Publication number: 20100012936
    Abstract: A layered film of a three-layer clad foil formed with a first metal layer 23, a second metal layer 25, and an inorganic insulating layer 35 interposed therebetween is prepared. After the second metal layer 25 is partially etched to form a gate electrode 20g, the first metal layer 23 is partially etched to form source/drain electrodes 20s, 20d in a region corresponding to the gate electrode 20g. A semiconductor layer 40 is then formed in contact with the source/drain electrodes 20s, 20d and on the gate electrode 20g with the inorganic insulating layer 35 interposed therebetween. The inorganic insulating layer 35 on the gate electrode 20g functions as a gate insulating film 30, and the semiconductor layer 40 between the source/drain electrodes 20s, 20d on the inorganic insulating layer 35 functions as a channel.
    Type: Application
    Filed: October 1, 2008
    Publication date: January 21, 2010
    Inventors: Koichi Hirano, Seiichi Nakatani, Shingo Komatsu, Yoshihisa Yamashita, Takashi Ichiryu
  • Publication number: 20100011572
    Abstract: A process for producing an electronic component assembly, comprising the steps of: (1) preparing a first electronic component whose surface (A) is provided with a plurality of electrodes (a) and a second electronic component whose surface (B) is provided with a plurality of electrodes (b) wherein at least one concave portion is formed in the surface (A) (except for a surface region on which the electrodes (a) are provided) and/or the surface (B) (except for a surface region on which the electrodes (b) are provided); (2) supplying a resin that comprises a solder powder onto the surface (A) of the first electronic component; (3) bringing the second electronic component into contact with a surface of the resin such that the plurality of electrodes (a) of the first electronic component are opposed to the plurality of electrodes (b) of the second electronic component; and (4) heating the first electronic component and/or the second electronic component, and thereby forming solder connections from the solder powder
    Type: Application
    Filed: April 24, 2008
    Publication date: January 21, 2010
    Inventors: Takashi Kitae, Seiichi Nakatani, Seiji Karashima
  • Publication number: 20100007033
    Abstract: A resin containing a conductive particle and a gas bubble generating agent is supplied in a space between the substrates each having a plurality of electrodes. The resin is then heated to melt the conductive particle contained in the resin and generate gas bubbles from the gas bubble generating agent. A step portion is formed on at least one of the substrates. In the process of heating the resin, the resin is pushed aside by the growing gas bubbles, and as a result of that, the conductive particle contained in the resin is led to a space between the electrodes, and a connector is formed in the space. At the same time, the resin is led to a space between parts of the substrates at which the step portion is formed, and cured to fix the distance between the substrates.
    Type: Application
    Filed: July 6, 2009
    Publication date: January 14, 2010
    Inventors: Takashi KITAE, Seiji Karashima, Susumu Sawada, Seiichi Nakatani
  • Publication number: 20100001411
    Abstract: A resin containing conductive particles and a gas bubble generating agent is supplied between a first substrate and a second substrate, and then the resin is heated to generate gas bubbles from the gas bubble generating agent contained in the resin so that the resin is self-assembled between electrodes. Then, the resin is further heated to melt the conductive particles contained in the resin, thereby forming connectors between electrodes. A partition member sealing the gap between the substrates is provided near a peripheral portion of the resin, and gas bubbles in the resin are discharged to the outside through the peripheral portion of the resin where the partition member is absent.
    Type: Application
    Filed: June 23, 2009
    Publication date: January 7, 2010
    Inventors: Susumu SAWADA, Seiichi NAKATANI, Seiji KARASHIMA, Takashi KITAE
  • Patent number: 7640654
    Abstract: A pickup device comprising a pickup surface to which an electronic component retaining liquid is to be applied and capable of adjusting a wet area of the electronic component retaining liquid on the pickup surface is prepared, and the electronic component retaining liquid is applied to the pickup surface in a first step. The electronic component is retained on the pickup surface via the electronic component retaining liquid in a state where the wet area is extended in a second step.
    Type: Grant
    Filed: February 2, 2007
    Date of Patent: January 5, 2010
    Assignee: Panasonic Corporation
    Inventors: Seiichi Nakatani, Seiji Karashima, Takashi Kitae
  • Patent number: 7640659
    Abstract: [Problem] To provide a conductive pattern formation method in which a fine pattern can be formed in a simple way at low cost. [Means for Solving Problem] A flat plate having a convex pattern on its surface is provided so as to oppose a substrate, a fluid body including conductive particles and a gas bubble generating agent is supplied into a gap between the substrate and the flat plate, and thereafter, the fluid body is heated for generating gas bubbles from the gas bubble generating agent included in the fluid body. The fluid body is forced out of the gas bubbles as the gas bubbles generated from the gas bubble generating agent grow, so as to self-assemble between the convex pattern formed on the flat plate and the substrate owing to interfacial force, and an aggregate of the conductive particles included in the fluid body having self-assembled is made into a conductive pattern formed on the substrate.
    Type: Grant
    Filed: August 11, 2005
    Date of Patent: January 5, 2010
    Assignee: Panasonic Corporation
    Inventors: Seiji Karashima, Takashi Kitae, Seiichi Nakatani
  • Patent number: 7638883
    Abstract: A flip chip mounting method which is applicable to the flip chip mounting of a next-generation LSI and high in productivity and reliability as well as a bump forming method are provided. After a resin 14 containing a solder powder 16 and a gas bubble generating agent is supplied to a space between a circuit board 21 having a plurality of connecting terminals 11 and a semiconductor chip 20 having a plurality of electrode terminals 12, the resin 14 is heated to generate gas bubbles 30 from the gas bubble generating agent contained in the resin 14. The resin 14 is pushed toward the outside of the generated gas bubbles 30 by the growth thereof and self-assembled between the connecting terminals 11 and the electrode terminals 12. By further heating the resin 14 and melting the solder powder 16 contained in the resin 14 self-assembled between the terminals, connectors 22 are formed between the terminals to complete a flip chip mounting body.
    Type: Grant
    Filed: April 30, 2008
    Date of Patent: December 29, 2009
    Assignee: Panasonic Corporation
    Inventors: Seiji Karashima, Takashi Kitae, Seiichi Nakatani
  • Patent number: 7611040
    Abstract: A method for forming solder bumps for realizing high density mounting and a highly reliable method for mounting a semiconductor device is provided. A flat plate having a plurality of projections or recesses thereon is prepared; the flat plate is aligned to oppose an electronic component and a resin composition including a solder powder is supplied to a gap between the flat plate and the electronic component; the resin composition is annealed to melt the solder powder included in the resin composition for growing the solder powder up to the level of the surface of the flat plate by allowing the melted solder powder to self-assemble on terminals, so as to form solder bumps on the terminals; and the flat plate is removed after cooling and solidifying the solder bumps. Thus, the solder bumps having pits corresponding to the projections or having protrusions corresponding to the recesses are formed.
    Type: Grant
    Filed: April 25, 2006
    Date of Patent: November 3, 2009
    Assignee: Panasonic Corporation
    Inventors: Takashi Kitae, Seiichi Nakatani, Toshiyuki Kojima, Shingo Komatsu, Yoshihisa Yamashita
  • Publication number: 20090230546
    Abstract: A mounted body of the present invention includes: a multilayer semiconductor chip 20 including a plurality of semiconductor chips 10 (10a, 10b) that are stacked; and a mounting board 13 on which the multilayer semiconductor chip 20 is mounted. In this mounted body, each of the semiconductor chips 10 (10a, 10b) in the multilayer semiconductor chip 20 has a plurality of element electrodes 12 (12a, 12b) on a chip surface 21 (21a, 21b) facing toward the mounting board 13. On the mounting board 13, electrode terminals 14 are formed so as to correspond to the plurality of element electrodes (12a, 12b), respectively, and the electrode terminals 14 of the mounting board and the element electrodes (12a, 12b) are connected electrically to each other via solder bump formed as a result of assembly of solder particles. With this configuration, a mounted body on which a stacked package is mounted can be manufactured easily.
    Type: Application
    Filed: February 28, 2006
    Publication date: September 17, 2009
    Applicant: MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD
    Inventors: Shingo Komatsu, Seiichi Nakatani, Seiji Karashima, Toshiyuki Kojima, Takashi Kitae, Yoshihisa Yamashita
  • Publication number: 20090229120
    Abstract: In a method for forming bumps 19 on electrodes 32 of a wiring board 31, a fluid 14 containing conductive particles 16 and a gas bubble generating agent is supplied onto a first region 17 including the electrodes 32 on the wiring board 31. Then, a substrate 40 which has a protruding surface 13 having the same area as that of the first region 17 and formed on a main surface 18 of the substrate 40 having a larger area than that of the first region 17 is disposed so that the protruding surface 13 faces the first region 17 of the wiring board 31. Then, the fluid 14 is heated to generate gas bubbles 30 from the gas bubble generating agent contained in the fluid 14.
    Type: Application
    Filed: February 22, 2007
    Publication date: September 17, 2009
    Inventors: Yasushi Taniguchi, Seiichi Nakatani, Seiji Karashima, Takashi Kitae, Susumu Matsuoka, Masayoshi Koyama