Patents by Inventor Seiichi Nakatani

Seiichi Nakatani has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20070257362
    Abstract: There is provided a process for forming bumps wherein a plurality of fine bumps are uniformly formed with high productivity. In this process, a resin (13) comprising solder powder and a convection additive (12) is supplied onto a substrate (10) having a plurality of electrodes (11) thereon. And subsequently the substrate (10) is heated to a temperature that enables the solder powder to melt while keeping a flat plate (14) in contact with a surface of the supplied resin (13). During this heating step, the molten solder powder is allowed to self-assemble onto the electrodes (11) so that a plurality of solder balls resulting from the grown molten solder powder are concurrently formed on the electrodes (11) in self-alignment manner. Finally, by moving the flat plate (14) away from the surface of the supplied resin (13), followed by removing such resin (13), there is provided the substrate (10) wherein the bumps (16) are formed on the plurality of the electrodes.
    Type: Application
    Filed: August 30, 2005
    Publication date: November 8, 2007
    Inventors: Seiji Karashima, Yoshihisa Yamashita, Satoru Tomekawa, Takashi Kitae, Seiichi Nakatani
  • Publication number: 20070243664
    Abstract: [Problem] To provide a flip-chip mounting method and a bump formation method applicable to flip-chip mounting of a next generation LSI and having high productivity and high reliability. [Means for Solving Problem] A semiconductor chip 20 having a plurality of electrode terminals 12 is held to oppose a circuit board 21 having a plurality of connection terminals 11 with a given gap provided therebetween, and the semiconductor chip 20 and the circuit board 21 in this state are dipped in a dipping bath 40 containing a melted resin 14 including melted solder particles for a given period of time. In this dipping process, the melted solder particles self-assemble between the connection terminals 11 of the circuit board 21 and the electrode terminals 12 of the semiconductor chip 20, so as to form connectors 22 between these terminals.
    Type: Application
    Filed: March 7, 2006
    Publication date: October 18, 2007
    Inventors: Koichi Hirano, Seiji Karashima, Takashi Ichiryu, Yoshihiro Tomita, Seiichi Nakatani
  • Publication number: 20070224735
    Abstract: A fabrication method for an optical transmission channel board includes a first step of forming on a substrate a layer containing an electrically conductive material, and a second step of patterning said layer containing an electrically conductive material formed on said substrate, and thereby forming circuit patterns at least a part of which is used as an electric circuit and at least a part of which positionally regulates an optical transmission channel.
    Type: Application
    Filed: May 18, 2007
    Publication date: September 27, 2007
    Applicant: Matsushita Electric Industrial Co., Ltd.
    Inventors: Seiji Karashima, Seiichi Nakatani, Yasuhiro Sugaya, Toshiyuki Asahi, Takashi Ichiryu
  • Publication number: 20070216023
    Abstract: The present invention provides a conductive resin composition for connecting electrodes electrically, in which metal particles are dispersed in a flowing medium, wherein the flowing medium includes a first flowing medium that has relatively high wettability with the metal particles and a second flowing medium that has relatively low wettability with the metal particles, and the first flowing medium and the second flowing medium are dispersed in a state of being incompatible with each other. Thereby, a flip chip packaging method that can be applied to flip chip packaging of LSI and has high productivity and high reliability is provided.
    Type: Application
    Filed: March 8, 2007
    Publication date: September 20, 2007
    Applicant: Matsushita Electric Industrial Co., Ltd.
    Inventors: Seiichi Nakatani, Seiji Karashima, Takashi Kitae, Susumu Sawada
  • Patent number: 7258549
    Abstract: A connection member can be produced without a via-forming step. The connection member includes an insulating substrate which has an upper surface, a lower surface opposed to the upper surface, and a side surface which connects these surfaces; and at least one wiring which extends from the upper surface to the lower surface through the side surface.
    Type: Grant
    Filed: February 18, 2005
    Date of Patent: August 21, 2007
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Toshiyuki Asahi, Seiji Karashima, Takashi Ichiryu, Seiichi Nakatani, Tousaku Nishiyama, Koichi Hirano, Osamu Shibata, Takeshi Nakayama, Yoshiyuki Saito
  • Publication number: 20070175024
    Abstract: A pickup device comprising a pickup surface to which an electronic component retaining liquid is to be applied and capable of adjusting a wet area of the electronic component retaining liquid on the pickup surface is prepared, and the electronic component retaining liquid is applied to the pickup surface in a first step. The electronic component is retained on the pickup surface via the electronic component retaining liquid in a state where the wet area is extended in a second step.
    Type: Application
    Filed: February 2, 2007
    Publication date: August 2, 2007
    Inventors: Seiichi Nakatani, Seiji Karashima, Takashi Kitae
  • Patent number: 7248482
    Abstract: A module with a built-in circuit component of the present invention includes an electric insulating layer, a pair of wiring layers provided on both principal planes of the electric insulating layer, a plurality of via conductors electrically connecting the pair of wiring layers and passing through the electric insulating layer in a thickness direction thereof, and a circuit component buried in the electric insulating layer, wherein the plurality of via conductors are disposed in a circumferential portion of the electric insulating layer in accordance with a predetermined rule. The plurality of via conductors are placed at an interval, for example, so as to form at least one straight line, in a cut surface of the electric insulating layer in a direction parallel to a principal plane thereof.
    Type: Grant
    Filed: May 12, 2004
    Date of Patent: July 24, 2007
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Toshiyuki Asahi, Yutaka Taguchi, Yasuhiro Sugaya, Seiichi Nakatani, Toshio Fujii
  • Patent number: 7247178
    Abstract: A miniature solid electrolytic capacitor is provided, which is suitable for being disposed within an electrically insulating layer, and is connected to other component using an electrically conductive adhesive with a connection resistance at an anode low and with connection reliability improved. Specifically, the electrolytic capacitor includes a valve metal element for an anode 10 having a capacitor forming part 10A and an electrode lead part 10B, a dielectric oxide film 11 formed on the valve element, a solid electrolyte layer 12 formed on the dielectric oxide film 11 and a charge collecting element for a cathode 13 formed on the solid electrolyte layer 12, wherein at least one through hole 15 is formed in the electrode lead part 10B so as to expose a core 10C of the valve metal element, and an exposed portion 10D of the core is used for connecting portion.
    Type: Grant
    Filed: September 20, 2006
    Date of Patent: July 24, 2007
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Koichi Hirano, Tsunenori Yoshida, Hiroyuki Handa, Yoshihisa Yamashita, Seiichi Nakatani
  • Patent number: 7242823
    Abstract: An optical transmission board is provided. The optical transmission board includes an optical transmission channel, a retention board for retaining the optical transmission channel and circuit patterns. The circuit patterns are formed on the retention board and a part of the circuit patterns is used as an electric circuit. The optical transmission channel is positionally regulated by the part of the circuit patterns.
    Type: Grant
    Filed: January 21, 2005
    Date of Patent: July 10, 2007
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Seiji Karashima, Seiichi Nakatani, Yasuhiro Sugaya, Toshiyuki Asahi, Takashi Ichiryu
  • Publication number: 20070151756
    Abstract: A flexible substrate comprises a film, a first insulating resin layer on a front face of the film, a second insulating resin layer on a rear face of the film, a front-sided wiring pattern embedded in the first insulating resin layer, and a rear-sided wiring pattern embedded in the second insulating resin layer. A surface of the front-sided wiring pattern is flush with a surface of the first insulating resin layer, and a surface of the rear-sided wiring pattern is flush with a surface of the second insulating resin layer. A part of at least one of the front-sided wiring pattern and the rear-sided wiring pattern is dented toward a part of the other of the at least one of the front-sided wiring pattern and the rear-sided wiring pattern such that a portion of the front-sided wiring pattern and a portion of the rear-sided wiring pattern are jointed to each other to form a junction.
    Type: Application
    Filed: March 2, 2007
    Publication date: July 5, 2007
    Inventors: Yoshihisa Yamashita, Hiroki Yabe, Takashi Ichiryu, Seiichi Nakatani, Satoru Tomekawa, Toshio Fujii, Seiji Karashima
  • Publication number: 20070124926
    Abstract: In a circuit board according to the present invention, on a substrate, in at least a portion of a phase change layer including a phase change material that is capable of changing alternately between an electrically insulating state and an electrically conductive state, a conductive path is formed that has been put into an electrically conductive state by a phase change in the phase change layer, wherein the phase change material includes a chalcogenide semiconductor, changes between the electrically insulating state and the electrically conductive state by irradiation of laser light, goes into the electrically conductive state in a crystalline phase, and goes into the electrically insulating state in an amorphous phase.
    Type: Application
    Filed: February 13, 2007
    Publication date: June 7, 2007
    Applicant: Matsushita Electric Industrial Co., Ltd.
    Inventors: Yukihiro Ishimaru, Seiichi Nakatani, Yoshiyuki Saito
  • Publication number: 20070119617
    Abstract: A component built-in module of the present invention includes: a first wiring pattern; an electronic component mounted on the first wiring pattern; a second wiring pattern; an electrical insulating sheet with the electrical component built therein, the electrical insulating sheet being disposed between the first wiring pattern and the second wiring pattern; and a via conductor formed in a via hole penetrating through the electrical insulating sheet, the via conductor connecting electrically the first wiring pattern and the second wiring pattern. A side face of the via conductor defines a continuous line in an axis direction of the via conductor. Thus, a component built-in module having excellent reliability concerning electrical connection can be provided.
    Type: Application
    Filed: September 27, 2004
    Publication date: May 31, 2007
    Applicant: MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.
    Inventors: Yoshitake Hayashi, Masayoshi Koyama, Satoru Yuhaku, Kazuo Otani, Susumu Matsuoka, Seiichi Nakatani
  • Patent number: 7205483
    Abstract: A flexible substrate comprises a film, a first insulating resin layer on a front face of the film, a second insulating resin layer on a rear face of the film, a front-sided wiring pattern embedded in the first insulating resin layer, and a rear-sided wiring pattern embedded in the second insulating resin layer. A surface of the front-sided wiring pattern is flush with a surface of the first insulating resin layer, and a surface of the rear-sided wiring pattern is flush with a surface of the second insulating resin layer. A part of at least one of the front-sided wiring pattern and the rear-sided wiring pattern is dented toward a part of the other of the at least one of the front-sided wiring pattern and the rear-sided wiring pattern such that a portion of the front-sided wiring pattern and a portion of the rear-sided wiring pattern are jointed to each other to form a junction.
    Type: Grant
    Filed: March 15, 2005
    Date of Patent: April 17, 2007
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Yoshihisa Yamashita, Hiroki Yabe, Takashi Ichiryu, Seiichi Nakatani, Satoru Tomekawa, Toshio Fujii, Seiji Karashima
  • Publication number: 20070081314
    Abstract: An electronic component packaging structure, includes: circuit boards each having a wiring at least on a surface thereof; and an electronic component package secured between the circuit boards. The electronic component package includes at least one electronic component embedded within an electrical insulating encapsulation resin molded member made of an inorganic filler and a resin, the at least one electronic component being selected from an active component and a passive component, protruding electrodes are arranged on both faces of the electrical insulating encapsulation resin molded member, and the electronic component is connected electrically with at least a part of the protruding electrodes. This configuration allows circuit boards to be connected with each other and a high-density and high-performance structure.
    Type: Application
    Filed: October 18, 2006
    Publication date: April 12, 2007
    Applicant: Matsushita Electric Industrial Co., Ltd.
    Inventor: Seiichi NAKATANI
  • Patent number: 7198996
    Abstract: A component built-in module including a core layer formed of an electric insulating material, and an electric insulating layer and a plurality of wiring patterns, which are formed on at least one surface of the core layer. The electric insulating material of the core layer is formed of a mixture including at least an inorganic filler and a thermosetting resin. At least one or more of active components and/or passive components are contained in an internal portion of the core layer. The core layer has a plurality of wiring patterns and a plurality of inner vias formed of a conductive resin. The electric insulating material formed of the mixture including at least an inorganic filler and a thermosetting resin of the core layer has a modulus of elasticity at room temperature in the range from 0.6 GPa to 10 GPa. Thus, it is possible to provide a thermal conductive component built-in module capable of filling the inorganic filler with high density; burying the active component such as a semiconductor etc.
    Type: Grant
    Filed: June 14, 2005
    Date of Patent: April 3, 2007
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Seiichi Nakatani, Yasuhiro Sugaya, Toshiyuki Asahi, Shingo Komatsu
  • Publication number: 20070069393
    Abstract: A double-sided or multilayer wiring board having high-density wiring is obtained by embedding a spherical semiconductor element in an electrically insulating substrate which composes the wiring board, and a thin electronic device can be provided using such a wiring board. Furthermore, a flexible double-sided or multilayer wiring board which is capable of being housed in a limited space while keeping a desired form can be provided by embedding the spherical semiconductor element, and a thin electronic device can be provided using a variety of such wiring boards by imparting different types of flexibility to desired parts of such a wiring board as required.
    Type: Application
    Filed: July 22, 2004
    Publication date: March 29, 2007
    Inventors: Toshiyuki Asahi, Yukihiro Ishimaru, Tousaku Nishiyama, Seiichi Nakatani, Yasuhiro Sugaya
  • Publication number: 20070035013
    Abstract: In a module including circuit elements, a plurality of wires, which are generally two-dimensionally formed, are multi-layered via electrically insulating material, which comprises a mixture including at least filler and electrically insulating resin. One or more circuit elements are electrically connected to the wires, and at least a part of those circuit elements is embedded in the electrically insulating material. The module further includes a heat sink member that has a higher thermal conductivity than the electrically insulating material, and that, when viewed from the direction of multi-layering the wires, overlaps with a circuit element, which is one of those circuit elements, exhibiting the highest temperature rise at least in the module.
    Type: Application
    Filed: May 7, 2004
    Publication date: February 15, 2007
    Inventors: Hiroyuki Handa, Seiichi Nakatani, Koichi Hirano, Osamu Inoue, Akihiro Ishikawa, Tsunenori Yoshida
  • Publication number: 20070022590
    Abstract: A miniature solid electrolytic capacitor is provided, which is suitable for being disposed within an electrically insulating layer, and is connected to other component using an electrically conductive adhesive with a connection resistance at an anode low and with connection reliability improved. Specifically, the electrolytic capacitor includes a valve metal element for an anode 10 having a capacitor forming part 10A and an electrode lead part 10B, a dielectric oxide film 11 formed on the valve element, a solid electrolyte layer 12 formed on the dielectric oxide film 11 and a charge collecting element for a cathode 13 formed on the solid electrolyte layer 12, wherein at least one through hole 15 is formed in the electrode lead part 10B so as to expose a core 10C of the valve metal element, and an exposed portion 10D of the core is used for connecting portion.
    Type: Application
    Filed: September 20, 2006
    Publication date: February 1, 2007
    Inventors: Koichi Hirano, Tsunenori Yoshida, Hiroyuki Handa, Yoshihisa Yamashita, Seiichi Nakatani
  • Patent number: 7157789
    Abstract: An example of a semiconductor device of the present invention includes a first semiconductor element including a first element body portion and a first element electrode that is provided on a first face of the first element body portion; a wiring board including an insulating substrate and a first wiring layer that is formed on one principal face of the insulating substrate, the wiring board being disposed such that the one principal face of the wiring board is opposed to a second face of the first element body portion; a first film that covers at least a portion of a face of the first semiconductor element that includes the surface of the first element electrode and at least a portion of a face on the first semiconductor element side of the wiring board; and a second wiring layer that is formed on a face on the wiring board side of the first film and that includes a first conductor having first and second ends.
    Type: Grant
    Filed: May 24, 2005
    Date of Patent: January 2, 2007
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Koichi Hirano, Yoshiyuki Yamamoto, Seiichi Nakatani, Toshiyuki Kojima, Shingo Komatsu
  • Publication number: 20060290009
    Abstract: A semiconductor device (1) of the present invention includes a semiconductor element (103) including electrode parts (104), and a wiring substrate (108) including an insulation layer (101), electrode-part-connection electrodes (102) provided in the insulation layer (101), and external electrodes (107) that is provided in the insulation layer (101) and that is connected electrically with the electrode-part-connection electrodes (102), in which the electrode parts (104) and the electrode-part-connection electrodes (102) are connected electrically with each other. The insulation layer (101) has an elastic modulus measured according to JIS K6911 of not less than 0.1 GP a and not more than 5 GPa, and the electrodes (104) and the electrode-part-connection electrodes (102) are connected by metal joint.
    Type: Application
    Filed: August 1, 2006
    Publication date: December 28, 2006
    Applicant: Matsushita Electric Industrial Co., Ltd.
    Inventors: Yasuhiro Sugaya, Toshiyuki Asahi, Shingo Komatsu, Yoshiyuki Yamamoto, Seiichi Nakatani