Abstract: Disclosed herein is an apparatus for evaluating the safety of a building. The apparatus includes first and second measurement instruments which measure earthquake accelerations of the top and bottom stories, a fast Fourier transform unit which performs fast Fourier transform on the earthquake accelerations, an integration unit which double-integrates the measured earthquake accelerations and creates drift data of the top story and the bottom story, a maximum inter-story drift ratio calculation unit which calculates a maximum inter-story drift ratio, a natural frequency change rate calculation unit which determines a natural frequency of the building, and compares the natural frequency with an ambient natural frequency of the building so as to calculate a natural frequency change rate, and a building safety evaluation unit which compares the maximum inter-story drift ratio and the frequency change rate with preset evaluation criteria and outputs a result of evaluation in the safety of the building.

Abstract: Semiconductor devices include lower interconnections, upper interconnections crossing over the lower interconnections, selection components disposed at crossing points of the lower interconnections and the upper interconnections, respectively, and memory components disposed between the selection components and the upper interconnections. Each of the selection components may include a semiconductor pattern having a first sidewall and a second sidewall. The first sidewall of the semiconductor pattern may have a first upper width and a first lower width that is greater than the first upper width. The second sidewall of the semiconductor pattern may have a second upper width and a second lower width that is substantially equal to the second upper width.

Abstract: A semiconductor device includes a lower interconnection having second conductivity-type impurities on a substrate having first conductivity-type impurities. A switching device is on the lower interconnection. A first blocking layer is provided between the lower interconnection and the switching device. The first blocking layer includes carbon (C), germanium (Ge), or a combination thereof. A second blocking layer may be provided between the substrate and the lower interconnection.

Abstract: An information providing method and an electronic apparatus thereof are provided. According to the information providing method of the electronic apparatus, when a video call is made, a user making the video call is identified, at least one piece of information-of-interest of the identified user is acquired based on user's usage information on social network services (SNSs), and the at least one piece of information-of-interest is displayed on a video call screen.

Abstract: A semiconductor device and method of forming a semiconductor device is disclosed. The method includes forming a first ion-implanted layer having an amorphous state in a substrate; forming an impurity region of a first conductive type in the substrate; forming a semiconductor pattern on the substrate; forming a first doped region of the first conductive type in the semiconductor pattern; and forming a second doped region of a second conductive type contrary to the first conductive type in the semiconductor pattern. The first ion-implanted layer is formed by implanting carbons ions or germanium ions in the substrate.

Abstract: In methods of manufacturing a recessed channel array transistor, a recess may be formed in an active region of a substrate. A plasma oxidation process may be performed on the substrate to form a preliminary gate oxide layer on an inner surface of the recess and an upper surface of the substrate. Moistures may be absorbed in a surface of the preliminary gate oxide layer to form a gate oxide layer. A gate electrode may be formed on the gate oxide layer to fill up the recess. Source/drain regions may be formed in an upper surface of the substrate at both sides of the gate electrode. Thus, the oxide layer may have a uniform thickness distribution and a dense structure.

Abstract: A method for verifying an operation of a reconfigurable processor is provided. The method includes generating an random test program using a test description and an architecture description, executing the generated random test program in a reconfigurable processor and in a simulator, and then comparing type of output values in the execution result.

Abstract: A method of managing data of a flash memory is provided. The method comprises: assigning a logical area of the flash memory as a user block area in which user storage data is stored, and a free block area in which the user storage data is temporarily stored when changing the user storage data; and, when a first data unit of user storage data received from a host is different from a second data unit used while mapping a physical address and a logical address of the flash memory where the user storage data is stored, assigning a predetermined logical area of the flash memory as a cache block area in which the user storage data received from the host is temporarily stored.

Abstract: A method of transmitting a downlink control signal is disclosed, by which localized allocation and distributed allocation are efficiently used in transmitting a downlink control signal. The present invention includes multiplexing the downlink control signal in a manner of if there exists downlink data transmission to a prescribed UE, applying localized allocation to a transmission of the downlink control signal including the scheduling information on the uplink data transmission of the UE and applying distributed allocation to another transmission of the downlink control signal and transmitting the multiplexed downlink control signal.

Abstract: Methods of forming integrated circuit devices include forming an electrically conductive layer containing silicon on a substrate and forming a mask pattern on the electrically conductive layer. The electrically conductive layer is selectively etched to define a first sidewall thereon, using the mask pattern as an etching mask. The first sidewall of the electrically conductive layer may be exposed to a nitrogen plasma to thereby form a first silicon nitride layer on the first sidewall. The electrically conductive layer is then selectively etched again to expose a second sidewall thereon that is free of the first silicon nitride layer. The mask pattern may be used again as an etching mask during this second step of selectively etching the electrically conductive layer.

Abstract: A method of transmitting a scheduling request signal, wherein the scheduling request signal is used to request a radio resource for uplink transmission in a wireless communication system is provided. The method includes configuring a physical uplink control channel (PUCCH) for transmission of a scheduling request signal in a subframe, the subframe comprising two consecutive slots, a slot comprising a plurality of single carrier-frequency division multiple access (SC-FDMA) symbols, the scheduling request signal being carried by a presence or absence of transmission of the PUCCH, wherein at least one SC-FDMA symbol is assigned for transmission of a sounding reference signal, and transmitting the scheduling request signal and the sounding reference signal in the subframe. Scheduling request signal can be transmitted without interference with other control signals such as sounding reference signal that are transmitted on the same control channel with the scheduling request signal.

Abstract: In semiconductor devices, methods of forming the same, the semiconductor device include a first gate structure having a first gate oxide layer pattern, a first polysilicon layer pattern containing atoms larger than silicon and a first hard mask layer pattern on substrates under tensile stress. N-type impurity regions are formed under the surface of the substrate on both sides of the first gate structure. A second gate structure having a second gate oxide layer pattern, a second polysilicon layer pattern containing atoms smaller than silicon and a second hard mask layer pattern on substrates under compressive stress. Additionally, P-type impurity regions are formed under the surface of the substrate on both sides of the second gate structure. The semiconductor devices have good device properties.

Abstract: Methods of forming integrated circuit devices include forming an electrically conductive layer containing silicon on a substrate and forming a mask pattern on the electrically conductive layer. The electrically conductive layer is selectively etched to define a first sidewall thereon, using the mask pattern as an etching mask. The first sidewall of the electrically conductive layer may be exposed to a nitrogen plasma to thereby form a first silicon nitride layer on the first sidewall. The electrically conductive layer is then selectively etched again to expose a second sidewall thereon that is free of the first silicon nitride layer. The mask pattern may be used again as an etching mask during this second step of selectively etching the electrically conductive layer.

Abstract: Methods of forming integrated circuit devices include forming an electrically conductive layer containing silicon on a substrate and forming a mask pattern on the electrically conductive layer. The electrically conductive layer is selectively etched to define a first sidewall thereon, using the mask pattern as an etching mask. The first sidewall of the electrically conductive layer may be exposed to a nitrogen plasma to thereby form a first silicon nitride layer on the first sidewall. The electrically conductive layer is then selectively etched again to expose a second sidewall thereon that is free of the first silicon nitride layer. The mask pattern may be used again as an etching mask during this second step of selectively etching the electrically conductive layer.

Abstract: Provided are a method of forming an insulating layer and a method of manufacturing a transistor using the method. The method of forming the insulating layer includes forming a preliminary insulating layer including silicon oxide (SiO2) on a silicon (Si)-containing substrate. A reactive gas containing ammonia (NH3) gas is supplied to the preliminary insulating layer. Nitrogen radicals (N*) and hydrogen radicals (H*) are generated from the ammonia gas using plasma. The hydrogen radicals combine with oxygen of the preliminary insulating layer, and the nitrogen radicals combine with the silicon oxide so that an insulating layer including hydroxides (OH) and silicon oxynitride (SiON) can be formed.

Abstract: A method of transmitting a downlink control signal is disclosed, by which localized allocation and distributed allocation are efficiently used in transmitting a downlink control signal. The present invention includes multiplexing the downlink control signal in a manner of if there exists downlink data transmission to a prescribed UE, applying localized allocation to a transmission of the downlink control signal including the scheduling information on the uplink data transmission of the UE and applying distributed allocation to another transmission of the downlink control signal and transmitting the multiplexed downlink control signal.

Abstract: In methods of manufacturing a recessed channel array transistor, a recess may be formed in an active region of a substrate. A plasma oxidation process may be performed on the substrate to form a preliminary gate oxide layer on an inner surface of the recess and an upper surface of the substrate. Moistures may be absorbed in a surface of the preliminary gate oxide layer to form a gate oxide layer. A gate electrode may be formed on the gate oxide layer to fill up the recess. Source/drain regions may be formed in an upper surface of the substrate at both sides of the gate electrode. Thus, the oxide layer may have a uniform thickness distribution and a dense structure.

Abstract: Methods of transmitting a control signal using efficient multiplexing are disclosed. One of the method includes the steps of multiplexing a plurality of 1-bit control signals within a prescribed time-frequency domain by code division multiple access (CDMA) and transmitting the multiplexed control signals, wherein a plurality of the 1-bit control signals include a plurality of the 1-bit control signals for a specific transmitting side. Accordingly, reliability on 1-bit control signal transmission can be enhanced.

Abstract: Methods of transmitting a control signal using efficient multiplexing are disclosed. One of the method includes the steps of multiplexing a plurality of 1-bit control signals within a prescribed time-frequency domain by code division multiple access (CDMA) and transmitting the multiplexed control signals, wherein a plurality of the 1-bit control signals include a plurality of the 1-bit control signals for a specific transmitting side. Accordingly, reliability on 1-bit control signal transmission can be enhanced.