Abstract: A method of transmitting a downlink control signal is disclosed, by which localized allocation and distributed allocation are efficiently used in transmitting a downlink control signal. The present invention includes multiplexing the downlink control signal in a manner of if there exists downlink data transmission to a prescribed UE, applying localized allocation to a transmission of the downlink control signal including the scheduling information on the uplink data transmission of the UE and applying distributed allocation to another transmission of the downlink control signal and transmitting the multiplexed downlink control signal.

Abstract: A method of transmitting a scheduling request signal, wherein the scheduling request signal is used to request a radio resource for uplink transmission in a wireless communication system is provided. The method includes configuring a physical uplink control channel (PUCCH) for transmission of a scheduling request signal in a subframe, the subframe comprising two consecutive slots, a slot comprising a plurality of single carrier-frequency division multiple access (SC-FDMA) symbols, the scheduling request signal being carried by a presence or absence of transmission of the PUCCH, wherein at least one SC-FDMA symbol is assigned for transmission of a sounding reference signal, and transmitting the scheduling request signal and the sounding reference signal in the subframe. Scheduling request signal can be transmitted without interference with other control signals such as sounding reference signal that are transmitted on the same control channel with the scheduling request signal.

Abstract: A method of transmitting a control signal using efficient multiplexing is disclosed. The present invention includes the steps of multiplexing a plurality of 1-bit control signals within a prescribed time-frequency domain by code division multiple access (CDMA) and transmitting the multiplexed control signals, wherein a plurality of the 1-bit control signals include a plurality of the 1-bit control signals for a specific transmitting side. Accordingly, reliability on 1-bit control signal transmission can be enhanced.

Abstract: Provided is a probe card and method of fabricating the same. This method comprises forming soldering bumpers electrically connected to conductive patterns on a substrate, forming probes connected to the conductive patterns and supported by the soldering bumpers, and then melting the soldering bumpers to fixing the probes to the substrate. Forming the soldering bumpers includes a step of forming the soldering bumpers in the same pattern and size by means of a photolithography process.

Abstract: A fin field effect transistor includes a fin protruding from a semiconductor substrate, a gate insulating layer formed so as to cover upper and lateral surfaces of the fin, and a gate electrode formed across the fin so as to cover the gate insulating layer. An upper edge of the fin is rounded so that an electric field concentratedly applied to the upper edge of the fin through the gate electrode is dispersed. A thickness of a portion of the gate insulating layer formed on an upper surface of the fin is greater than a thickness of a portion of the gate insulating layer formed on a lateral surface of the fin, in order to reduce an electric field applied through the gate electrode.

Abstract: A method of transmitting a control signal using efficient multiplexing is disclosed. The present invention includes the steps of multiplexing a plurality of 1-bit control signals within a prescribed time-frequency domain by code division multiple access (CDMA) and transmitting the multiplexed control signals, wherein a plurality of the 1-bit control signals include a plurality of the 1-bit control signals for a specific transmitting side. Accordingly, reliability on 1-bit control signal transmission can be enhanced.

Abstract: Methods of transmitting a control signal using efficient multiplexing are disclosed. One of the method includes the steps of multiplexing a plurality of 1-bit control signals within a prescribed time-frequency domain by code division multiple access (CDMA) and transmitting the multiplexed control signals, wherein a plurality of the 1-bit control signals include a plurality of the 1-bit control signals for a specific transmitting side. Accordingly, reliability on 1-bit control signal transmission can be enhanced.

Abstract: Provided are a method of forming an insulating layer and a method of manufacturing a transistor using the method. The method of forming the insulating layer includes forming a preliminary insulating layer including silicon oxide (SiO2) on a silicon (Si)-containing substrate. A reactive gas containing ammonia (NH3) gas is supplied to the preliminary insulating layer. Nitrogen radicals (N*) and hydrogen radicals (H*) are generated from the ammonia gas using plasma. The hydrogen radicals combine with oxygen of the preliminary insulating layer, and the nitrogen radicals combine with the silicon oxide so that an insulating layer including hydroxides (OH) and silicon oxynitride (SiON) can be formed.

Abstract: In semiconductor devices, methods of forming the same, the semiconductor device include a first gate structure having a first gate oxide layer pattern, a first polysilicon layer pattern containing atoms larger than silicon and a first hard mask layer pattern on substrates under tensile stress. N-type impurity regions are formed under the surface of the substrate on both sides of the first gate structure. A second gate structure having a second gate oxide layer pattern, a second polysilicon layer pattern containing atoms smaller than silicon and a second hard mask layer pattern on substrates under compressive stress. Additionally, P-type impurity regions are formed under the surface of the substrate on both sides of the second gate structure. The semiconductor devices have good device properties.

Abstract: An electrostatic discharge (ESD) protection circuit protects a gate oxide of elements in an internal circuit against ESD. During an ESD test, if the sum of driving voltages of ESD protectors connected between a power pad and a ground pad is higher than the gate oxide breakdown voltage of elements in the internal circuit, the structure of the ESD protector is changed or another ESD protector is additionally provided so as to protect the gate oxide of the elements in the internal circuit against ESD.

Abstract: Provided are a substrate of a probe card for installing a plurality of probes thereon to inspect an object by contacting the probes to the object, and a method for repairing the substrate. The substrate includes main channels electrically connected to the probes; and at least one spare channel for replacing the main channels when at least one of the main channels is damaged. Therefore, when some of the main channels of the probe substrate are damaged, the damaged main channels can be repaired using the spare channels and then the probe substrate can be reused, thereby reducing costs required for unnecessary replacement.

Abstract: A method of managing data of a flash memory is provided. The method comprises: assigning a logical area of the flash memory as a user block area in which user storage data is stored, and a free block area in which the user storage data is temporarily stored when changing the user storage data; and, when a first data unit of user storage data received from a host is different from a second data unit used while mapping a physical address and a logical address of the flash memory where the user storage data is stored, assigning a predetermined logical area of the flash memory as a cache block area in which the user storage data received from the host is temporarily stored.

Abstract: A fin field effect transistor includes a fin protruding from a semiconductor substrate, a gate insulating layer formed so as to cover upper and lateral surfaces of the fin, and a gate electrode formed across the fin so as to cover the gate insulating layer. An upper edge of the fin is rounded so that an electric field concentratedly applied to the upper edge of the fin through the gate electrode is dispersed. A thickness of a portion of the gate insulating layer formed on an upper surface of the fin is greater than a thickness of a portion of the gate insulating layer formed on a lateral surface of the fin, in order to reduce an electric field applied through the gate electrode.

Abstract: A method of transmitting a control signal using efficient multiplexing is disclosed. The present invention includes the steps of multiplexing a plurality of 1-bit control signals within a prescribed time-frequency domain by code division multiple access (CDMA) and transmitting the multiplexed control signals, wherein a plurality of the 1-hit control signals include a plurality of the 1-bit control signals for a specific transmitting side. Accordingly, reliability on 1-bit control signal transmission can be enhanced.

Abstract: Methods of transmitting a control signal using efficient multiplexing are disclosed. One of the method includes the steps of multiplexing a plurality of 1-hit control signals within a prescribed time-frequency domain by code division multiple access (CDMA) and transmitting the multiplexed control signals, wherein a plurality of the 1-bit control signals include a plurality of the 1-bit control signals for a specific transmitting side. Accordingly, reliability on 1-bit control signal transmission can be enhanced.

Abstract: A method of transmitting a downlink control signal is disclosed, by which localized allocation and distributed allocation are efficiently used in transmitting a downlink control signal. The present invention includes multiplexing the downlink control signal in a manner of if there exists downlink data transmission to a prescribed UE, applying localized allocation to a transmission of the downlink control signal including the scheduling information on the uplink data transmission of the UE and applying distributed allocation to another transmission of the downlink control signal and transmitting the multiplexed downlink control signal.

Abstract: A recessed channel array transistor may include a substrate, a gate oxide layer, a gate electrode and source/drain regions. The substrate may have an active region and an isolation region. A recess may be formed in the active region. The gate oxide layer may be formed on the recess and the substrate. The gate oxide layer may include a first portion on an intersection between a side end of the recess and a sidewall of the active region and a second portion on a side surface of the recess. The first portion may include a thickness greater than about 70% of a thickness of the second portion. The gate electrode may be formed on the gate oxide layer. The source/drain regions may be formed in the substrate. Thus, the recessed channel array transistor may have a decreased leakage current and an increased on-current.

Abstract: An electrostatic discharge (ESD) protection circuit protects a gate oxide of elements in an internal circuit against ESD. During an ESD test, if the sum of driving voltages of ESD protectors connected between a power pad and a ground pad is higher than the gate oxide breakdown voltage of elements in the internal circuit, the structure of the ESD protector is changed or another ESD protector is additionally provided so as to protect the gate oxide of the elements in the internal circuit against ESD.

Abstract: Methods of forming integrated circuit devices include forming an electrically conductive layer containing silicon on a substrate and forming a mask pattern on the electrically conductive layer. The electrically conductive layer is selectively etched to define a first sidewall thereon, using the mask pattern as an etching mask. The first sidewall of the electrically conductive layer may be exposed to a nitrogen plasma to thereby form a first silicon nitride layer on the first sidewall. The electrically conductive layer is then selectively etched again to expose a second sidewall thereon that is free of the first silicon nitride layer. The mask pattern may be used again as an etching mask during this second step of selectively etching the electrically conductive layer.

Abstract: A semiconductor device may include an isolation layer, gate electrodes, an insulating interlayer, an impurity region, a capping layer and a plug. The isolation layer may be formed in the substrate. The gate electrodes may be formed on the substrate. The insulating interlayer may be formed on the gate electrodes. The insulating interlayer may have a contact hole between the gate electrodes. The impurity region may be in the substrate exposed through the contact hole. The capping layer may be on the impurity region. The plug may be on the capping layer. Thus, the impurities may not be lost from the impurity region.