Patents by Inventor Shang-Wen Chang

Shang-Wen Chang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20250241052
    Abstract: A semiconductor structure includes a first semiconductor fin and a second semiconductor fin adjacent to the first semiconductor fin. The first and the second semiconductor fins extend lengthwise along a first direction over a substrate. A metal gate structure is disposed over the first and second semiconductor fins, the metal gate structure extending lengthwise along a second direction perpendicular to the first direction. A first epitaxial source/drain (S/D) feature is disposed over the first semiconductor fin, and a second epitaxial S/D feature is disposed over the second semiconductor fin. An interlayer dielectric (ILD) layer is disposed over the first and the second epitaxial S/D features. And an S/D contact is disposed directly above the first and second epitaxial S/D features. The S/D contact directly contacts the first epitaxial S/D feature, and the S/D contact is isolated from the second epitaxial S/D feature by the ILD layer.
    Type: Application
    Filed: April 7, 2025
    Publication date: July 24, 2025
    Inventors: Yi-Hsiung Lin, Yi-Hsun Chiu, Shang-Wen Chang
  • Patent number: 12327765
    Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a first epitaxial structure and a second epitaxial structure spaced apart from the first epitaxial structure. The semiconductor device structure also includes a conductive contact electrically connected to the first epitaxial structure and a first conductive via over the conductive contact. The semiconductor device structure further includes a second conductive via directly above the second epitaxial structure. The second conductive via is longer than the first conductive via.
    Type: Grant
    Filed: May 17, 2023
    Date of Patent: June 10, 2025
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Yi-Hsiung Lin, Yi-Hsun Chiu, Shang-Wen Chang
  • Publication number: 20250174496
    Abstract: Semiconductor devices and methods are provided which facilitate performing physical failure analysis (PFA) testing from a backside of the devices. In at least one example, a device is provided that includes a semiconductor device layer including a plurality of diffusion regions. A first interconnection structure is disposed on a first side of the semiconductor device layer, and the first interconnection structure includes at least one electrical contact. A second interconnection structure is disposed on a second side of the semiconductor device layer, and the second interconnection structure includes a plurality of backside power rails. Each of the backside power rails at least partially overlaps a respective diffusion region of the plurality of diffusion regions and defines openings which expose portions of the respective diffusion region at the second side of the semiconductor device layer.
    Type: Application
    Filed: January 23, 2025
    Publication date: May 29, 2025
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chih-Chao CHOU, Yi-Hsun CHIU, Shang-Wen CHANG, Ching-Wei TSAI, Chih-Hao WANG
  • Patent number: 12272605
    Abstract: A semiconductor structure includes a first semiconductor fin and a second semiconductor fin adjacent to the first semiconductor fin. The first and the second semiconductor fins extend lengthwise along a first direction over a substrate. A metal gate structure is disposed over the first and second semiconductor fins, the metal gate structure extending lengthwise along a second direction perpendicular to the first direction. A first epitaxial source/drain (S/D) feature is disposed over the first semiconductor fin, and a second epitaxial S/D feature is disposed over the second semiconductor fin. An interlayer dielectric (ILD) layer is disposed over the first and the second epitaxial S/D features. And an S/D contact is disposed directly above the first and second epitaxial S/D features. The S/D contact directly contacts the first epitaxial S/D feature, and the S/D contact is isolated from the second epitaxial S/D feature by the ILD layer.
    Type: Grant
    Filed: June 16, 2023
    Date of Patent: April 8, 2025
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Yi-Hsiung Lin, Yi-Hsun Chiu, Shang-Wen Chang
  • Patent number: 12266594
    Abstract: A method of making a semiconductor device includes manufacturing a first transistor over a first side of a substrate. The method further includes depositing a spacer material against a sidewall of the first transistor. The method further includes recessing the spacer material to expose a first portion of the sidewall of the first transistor. The method further includes manufacturing a first electrical connection to the transistor, a first portion of the electrical connection contacts a surface of the first transistor farthest from the substrate, and a second portion of the electrical connect contacts the first portion of the sidewall of the first transistor. The method further includes manufacturing a self-aligned interconnect structure (SIS) extending along the spacer material, wherein the spacer material separates a portion of the SIS from the first transistor, and the first electrical connection directly contacts the SIS.
    Type: Grant
    Filed: November 22, 2023
    Date of Patent: April 1, 2025
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chih-Yu Lai, Chih-Liang Chen, Chi-Yu Lu, Shang-Syuan Ciou, Hui-Zhong Zhuang, Ching-Wei Tsai, Shang-Wen Chang
  • Publication number: 20250081594
    Abstract: A semiconductor device structure, along with methods of forming such, are described. The structure includes a first and second gate electrode layers, and a dielectric feature disposed between the first and second gate electrode layers. The dielectric feature has a first surface. The structure further includes a first conductive layer disposed on the first gate electrode layer. The first conductive layer has a second surface. The structure further includes a second conductive layer disposed on the second gate electrode layer. The second conductive layer has a third surface, and the first, second, and third surfaces are coplanar. The structure further includes a third conductive layer disposed over the first conductive layer, a fourth conductive layer disposed over the second conductive layer, and a dielectric layer disposed on the first surface of the dielectric feature. The dielectric layer is disposed between the third conductive layer and the fourth conductive layer.
    Type: Application
    Filed: November 20, 2024
    Publication date: March 6, 2025
    Inventors: Kuan-Ting PAN, Kuo-Cheng CHIANG, Shang-Wen CHANG, Ching-Wei TSAI, Kuan-Lun CHENG, Chih-Hao WANG
  • Publication number: 20250070011
    Abstract: A method includes forming first integrated circuit devices and second integrated circuit devices on a semiconductor substrate of a wafer, forming a metal layer as a part of the wafer, and forming a transistor comprising a first source/drain region connected to the first integrated circuit devices. The transistor is farther away from the semiconductor substrate than the metal layer. An electrical connector is formed on a surface of the wafer, and is electrically connected to a second source/drain region of the transistor.
    Type: Application
    Filed: January 2, 2024
    Publication date: February 27, 2025
    Inventors: Chih-Chao Chou, Cheng-Chi Chuang, Chih-Hao Wang, Ching-Wei Tsai, Shang-Wen Chang
  • Patent number: 12237233
    Abstract: Semiconductor devices and methods are provided which facilitate performing physical failure analysis (PFA) testing from a backside of the devices. In at least one example, a device is provided that includes a semiconductor device layer including a plurality of diffusion regions. A first interconnection structure is disposed on a first side of the semiconductor device layer, and the first interconnection structure includes at least one electrical contact. A second interconnection structure is disposed on a second side of the semiconductor device layer, and the second interconnection structure includes a plurality of backside power rails. Each of the backside power rails at least partially overlaps a respective diffusion region of the plurality of diffusion regions and defines openings which expose portions of the respective diffusion region at the second side of the semiconductor device layer.
    Type: Grant
    Filed: May 6, 2022
    Date of Patent: February 25, 2025
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chih-Chao Chou, Yi-Hsun Chiu, Shang-Wen Chang, Ching-Wei Tsai, Chih-Hao Wang
  • Publication number: 20250062195
    Abstract: A device includes a plurality of tracks, wherein at least one of the plurality of tracks comprises a first power rail for a first voltage. The device further includes a first via in electrical contact with the power rail. The device further includes a first contact in electrical contact with the first via. The device further includes a first transistor in electrical contact with the first contact. The device further includes a second transistor in electrical isolation with the first transistor. The device further includes a second contact in electrical contact with the second transistor. The device further includes a second via in electrical contact with the second contact. The device further includes a second power rail in electrical contact with the second via, wherein the second power rail is configured to carry a second voltage.
    Type: Application
    Filed: November 5, 2024
    Publication date: February 20, 2025
    Inventors: Chih-Yu LAI, Chih-Liang CHEN, Chi-Yu LU, Shang-Syuan CIOU, Hui-Zhong ZHUANG, Ching-Wei TSAI, Shang-Wen CHANG
  • Publication number: 20250046700
    Abstract: A method includes forming a first device die and a second device die. The first device die includes a first integrated circuit, and a first bond pad at a first surface of the first device die. The first integrated circuit is electrically connected to the first bond pad. The second device die includes a power switch that includes a first source/drain region, a second source/drain region, a second bond pad electrically connecting to the first source/drain region, and a third bond pad electrically connecting to the second source/drain region. The method further includes bonding the first device die with the second device die to form a package, with the first bond pad bonding to the third bond pad, and bonding the package to a package component.
    Type: Application
    Filed: October 26, 2023
    Publication date: February 6, 2025
    Inventors: Chih-Chao Chou, Cheng-Chi Chuang, Ching-Wei Tsai, Shang-Wen Chang
  • Patent number: 12165926
    Abstract: A semiconductor device structure, along with methods of forming such, are described. The structure includes a first and second gate electrode layers, and a dielectric feature disposed between the first and second gate electrode layers. The dielectric feature has a first surface. The structure further includes a first conductive layer disposed on the first gate electrode layer. The first conductive layer has a second surface. The structure further includes a second conductive layer disposed on the second gate electrode layer. The second conductive layer has a third surface, and the first, second, and third surfaces are coplanar. The structure further includes a third conductive layer disposed over the first conductive layer, a fourth conductive layer disposed over the second conductive layer, and a dielectric layer disposed on the first surface of the dielectric feature. The dielectric layer is disposed between the third conductive layer and the fourth conductive layer.
    Type: Grant
    Filed: July 20, 2023
    Date of Patent: December 10, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Kuan-Ting Pan, Kuo-Cheng Chiang, Shang-Wen Chang, Ching-Wei Tsai, Kuan-Lun Cheng, Chih-Hao Wang
  • Publication number: 20240404881
    Abstract: A semiconductor device structure and methods of forming the same are described. In some embodiments, the method includes depositing an etch stop layer on a substrate, depositing a first substrate layer on the etch stop layer, forming a plurality of active devices on the first substrate layer, forming an interconnection structure over the active devices, flipping over the substrate, removing the substrate, removing the etch stop layer to expose the first substrate layer, and forming a cooling substrate layer on the exposed first substrate layer. The cooling substrate layer has a thermal conductivity substantially greater than a thermal conductivity of the substrate.
    Type: Application
    Filed: June 3, 2023
    Publication date: December 5, 2024
    Inventors: Chih-Chao Chou, Chih-Hao Wang, Ching-Wei Tsai, Shang-Wen Chang, Yi-Hsun Chiu
  • Publication number: 20240395671
    Abstract: A method of making a semiconductor device includes manufacturing a first transistor over a first side of a substrate. The method further includes depositing a spacer material against a sidewall of the first transistor. The method further includes recessing the spacer material to expose a first portion of the sidewall of the first transistor. The method further includes manufacturing a first electrical connection to the transistor, a first portion of the electrical connection contacts a surface of the first transistor farthest from the substrate, and a second portion of the electrical connect contacts the first portion of the sidewall of the first transistor. The method further includes manufacturing a self-aligned interconnect structure (SIS) extending along the spacer material, wherein the spacer material separates a portion of the SIS from the first transistor, and the first electrical connection directly contacts the SIS.
    Type: Application
    Filed: July 31, 2024
    Publication date: November 28, 2024
    Inventors: Chih-Yu LAI, Chih-Liang CHEN, Chi-Yu LU, Shang-Syuan CIOU, Hui-Zhong ZHUANG, Ching-Wei TSAI, Shang-Wen CHANG
  • Publication number: 20240387530
    Abstract: A device includes a first semiconductor strip and a second semiconductor strip extending longitudinally in a first direction, where the first semiconductor strip and the second semiconductor strip are spaced apart from each other in a second direction. The device also includes a power supply line located between the first semiconductor strip and the second semiconductor strip. A top surface of the power supply line is recessed in comparison to a top surface of the first semiconductor strip. A source feature is disposed on a source region of the first semiconductor strip, and a source contact electrically couples the source feature to the power supply line. The source contact includes a lateral portion contacting a top surface of the source feature, and a vertical portion extending along a sidewall of the source feature towards the power supply line to physically contact the power supply line.
    Type: Application
    Filed: July 29, 2024
    Publication date: November 21, 2024
    Inventors: Yi-Hsiung Lin, Yi-Hsun Chiu, Shang-Wen Chang
  • Patent number: 12148745
    Abstract: The disclosed circuit includes a first and a second active region (AR) spaced a spacing S along a direction in a first standard cell (SC) that spans Dl along the direction between a first and a second cell edge (CE). Each of the first and second ARs spans a first width W1 along the direction; a third and a fourth AR spaced S in a second SC that spans a second dimension Ds along the direction between a third and a fourth CE; and gate stacks extend from the fourth CE of the second SC to the first CE of the first SC, wherein Ds<Dl; each of the third and fourth ARs spans a second width W2 along the direction; W2<W1; and the third CE is aligned with and contacts the second CE. The first and second ARs have a structure different from the third and fourth ARs.
    Type: Grant
    Filed: July 20, 2023
    Date of Patent: November 19, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chih-Hao Wang, Shang-Wen Chang, Min Cao
  • Publication number: 20240379654
    Abstract: The disclosed circuit includes a first and a second active region (AR) spaced a spacing S along a direction in a first standard cell (SC) that spans Dl along the direction between a first and a second cell edge (CE). Each of the first and second ARs spans a first width W1 along the direction; a third and a fourth AR spaced S in a second SC that spans a second dimension Ds along the direction between a third and a fourth CE; and gate stacks extend from the fourth CE of the second SC to the first CE of the first SC, wherein Ds<Dl; each of the third and fourth ARs spans a second width W2 along the direction; W2<W1; and the third CE is aligned with and contacts the second CE. The first and second ARs have a structure different from the third and fourth ARs.
    Type: Application
    Filed: July 25, 2024
    Publication date: November 14, 2024
    Inventors: Chih-Hao Wang, Shang-Wen Chang, Min Cao
  • Publication number: 20240363626
    Abstract: Methods of performing backside etching processes on source/drain regions and gate structures of semiconductor devices and semiconductor devices formed by the same are disclosed. In an embodiment, a semiconductor device includes a first transistor structure; a first interconnect structure on a front-side of the first transistor structure; and a second interconnect structure on a backside of the first transistor structure, the second interconnect structure including a first dielectric layer on the backside of the first transistor structure; a contact extending through the first dielectric layer to a source/drain region of the first transistor structure; and first spacers along sidewalls of the contact between the contact and the first dielectric layer, sidewalls of the first spacers facing the first dielectric layer being aligned with sidewalls of the source/drain region of the first transistor structure.
    Type: Application
    Filed: July 9, 2024
    Publication date: October 31, 2024
    Inventors: Yi-Hsun Chiu, Ching-Wei Tsai, Yu-Xuan Huang, Cheng-Chi Chuang, Shang-Wen Chang
  • Publication number: 20240347546
    Abstract: A method of making a semiconductor device includes manufacturing a first bridge pillar; manufacturing a first transistor channel bar and first transistor source/drain electrode, the first transistor S/D electrode electrically connecting to the first bridge pillar; manufacturing a second transistor channel bar and second transistor S/D electrode; manufacturing a first metal electrode, the first bridge pillar connecting the first transistor S/D electrode and first metal electrode; manufacturing a first via connected to the first metal electrode; and manufacturing a first conductive line connected to the first via. The first transistor S/D electrode and the second transistor S/D electrode are spaced apart by a first height, the first metal electrode is separate from the second transistor S/D electrode, the first bridge pillar is separate from the second transistor S/D electrode, and the first bridge pillar has a height in the first direction substantially equal to the first height.
    Type: Application
    Filed: June 26, 2024
    Publication date: October 17, 2024
    Inventors: Chih-Yu LAI, Chih-Liang CHEN, Ching-Wei TSAI, Shang-Wen CHANG, Li-Chun TIEN
  • Patent number: 12113066
    Abstract: A device includes a first semiconductor strip and a second semiconductor strip extending longitudinally in a first direction, where the first semiconductor strip and the second semiconductor strip are spaced apart from each other in a second direction. The device also includes a power supply line located between the first semiconductor strip and the second semiconductor strip. A top surface of the power supply line is recessed in comparison to a top surface of the first semiconductor strip. A source feature is disposed on a source region of the first semiconductor strip, and a source contact electrically couples the source feature to the power supply line. The source contact includes a lateral portion contacting a top surface of the source feature, and a vertical portion extending along a sidewall of the source feature towards the power supply line to physically contact the power supply line.
    Type: Grant
    Filed: November 16, 2023
    Date of Patent: October 8, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Yi-Hsiung Lin, Yi-Hsun Chiu, Shang-Wen Chang
  • Patent number: 12107012
    Abstract: A method for forming a fin field effect transistor device structure is provided. The method includes forming a first spacer layer over a first fin structure and a second fin structure. The method also includes forming a power rail between the first fin structure and the second fin structure. The method further includes forming a second spacer layer over the first spacer layer and the power rail. In addition, the method includes forming a fin isolation structure over the power rail between the first fin structure and the second fin structure. The method also includes forming an epitaxial structure over the first fin structure and the second fin structure. The method further includes forming an inter-layer dielectric structure covering the epitaxial structure. In addition, the method includes forming an opening exposing the epitaxial structure, the power rail and the fin isolation structure. The method also includes filling the opening with a first contact structure.
    Type: Grant
    Filed: July 24, 2023
    Date of Patent: October 1, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Shang-Wen Chang, Yi-Hsiung Lin, Yi-Hsun Chiu