Patents by Inventor Shang-Wen Chang
Shang-Wen Chang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20220336325Abstract: A semiconductor device includes a substrate and a first transistor on a first side of the substrate. The semiconductor device further includes a first electrode contacting a first region of the first transistor. The semiconductor device further includes a spacer extending along a sidewall of the first transistor. The semiconductor device further includes a self-aligned interconnect structure (SIS) separated from at least a portion of the first electrode by the spacer, wherein the SIS extends through the substrate. The semiconductor device further includes a second electrode contacting a surface of the first electrode farthest from the substrate, wherein the second electrode directly contacts the SIS.Type: ApplicationFiled: April 15, 2021Publication date: October 20, 2022Inventors: Chih-Yu LAI, Chih-Liang CHEN, Chi-Yu LU, Shang-Syuan CIOU, Hui-Zhong ZHUANG, Ching-Wei TSAI, Shang-Wen CHANG
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Publication number: 20220336472Abstract: An integrated circuit (IC) includes a first p-type semiconductor fin, a first dielectric fin, a first hybrid fin, a second hybrid fin, a second dielectric fin, and a second p-type semiconductor fin disposed in this order along a first direction and oriented lengthwise along a second direction, where each of the first and the second hybrid fins has a first portion including an n-type semiconductor material and a second portion including a dielectric material. The IC further includes n-type source/drain (S/D) epitaxial features disposed over each of the first and the second p-type semiconductor fins, p-type S/D epitaxial features disposed over the first portion of each of the first and the second hybrid fins, and S/D contacts physically contacting each of the p-type S/D epitaxial features and the second portion of each of the first and the second hybrid fins.Type: ApplicationFiled: July 5, 2022Publication date: October 20, 2022Inventors: Chih-Hao Wang, Yi-Hsun Chiu, Yi-Hsiung Lin, Shang-Wen Chang
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Publication number: 20220336455Abstract: The present disclosure relates to an integrated circuit. In one implementation, the integrated circuit may include a semiconductor substrate; at least one source region comprising a first doped semiconductor material; at least one drain region comprising a second doped semiconductor material; at least one gate formed between the at least one source region and the at least one drain region; and a nanosheet formed between the semiconductor substrate and the at least one gate. The nanosheet may be configured as a routing channel for the at least one gate and may have a first region having a first width and a second region having a second width. The first width may be smaller than the second width.Type: ApplicationFiled: June 30, 2022Publication date: October 20, 2022Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Yi-Hsiung LIN, Yi-Hsun CHIU, Shang-Wen CHANG, Ching-Wei TSAI, Yu-Xuan HUANG, Kuan-Lun CHENG, Chih-Hao WANG
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Publication number: 20220328363Abstract: Methods of forming dual-side super power rails in semiconductor devices, semiconductor devices including the same, and methods of testing the semiconductor devices are disclosed. In an embodiment, a device includes a transistor structure; a front-side interconnect structure on a front side of the transistor structure; and a back-side interconnect structure on a back side of the transistor structure. The front-side interconnect structure includes a front-side power delivery network (PDN) and a front-side input/output (I/O) pin. The back-side interconnect structure includes a back-side PDN.Type: ApplicationFiled: June 25, 2021Publication date: October 13, 2022Inventors: Chih-Chao Chou, Yi-Hsun Chiu, Shang-Wen Chang, Ching-Wei Tsai, Chih-Hao Wang
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Publication number: 20220310591Abstract: A semiconductor device includes a substrate and a first active region on a first side of the substrate. The semiconductor device further includes a first gate structure surrounding a first portion of the first active region. The semiconductor device further includes a second active region on a second side of the substrate, wherein the second side is opposite the first side. The semiconductor device further includes a second gate structure surrounding a first portion of the second active region. The semiconductor device further includes a gate via extending through the substrate, wherein the gate via directly connects to the first gate structure, and the gate via directly connects to the second gate structure.Type: ApplicationFiled: March 26, 2021Publication date: September 29, 2022Inventors: Chih-Yu LAI, Chih-Liang CHEN, Chi-Yu LU, Shang-Syuan CIOU, Hui-Zhong ZHUANG, Ching-Wei TSAI, Shang-Wen CHANG
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Publication number: 20220310454Abstract: A semiconductor device structure, along with methods of forming such, are described. The structure includes a first and second gate electrode layers, and a dielectric feature disposed between the first and second gate electrode layers. The dielectric feature has a first surface. The structure further includes a first conductive layer disposed on the first gate electrode layer. The first conductive layer has a second surface. The structure further includes a second conductive layer disposed on the second gate electrode layer. The second conductive layer has a third surface, and the first, second, and third surfaces are coplanar. The structure further includes a third conductive layer disposed over the first conductive layer, a fourth conductive layer disposed over the second conductive layer, and a dielectric layer disposed on the first surface of the dielectric feature. The dielectric layer is disposed between the third conductive layer and the fourth conductive layer.Type: ApplicationFiled: June 6, 2022Publication date: September 29, 2022Inventors: Kuan-Ting PAN, Kuo-Cheng CHIANG, Shang-Wen CHANG, Ching-Wei TSAI, Kuan-Lun CHENG, Chih-Hao WANG
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Publication number: 20220302026Abstract: A semiconductor device includes a first gate structure extending along a first lateral direction. The semiconductor device includes a first interconnect structure, disposed above the first gate structure, that extends along a second lateral direction perpendicular to the first lateral direction. The first interconnect structure includes a first portion and a second portion electrically isolated from each other by a first dielectric structure. The semiconductor device includes a second interconnect structure, disposed between the first gate structure and the first interconnect structure, that electrically couples the first gate structure to the first portion of the first interconnect structure. The second interconnect structure includes a recessed portion that is substantially aligned with the first gate structure and the dielectric structure along a vertical direction.Type: ApplicationFiled: June 8, 2022Publication date: September 22, 2022Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Guo-Huei Wu, Hui-Zhong Zhuang, Chih-Liang Chen, Cheng-Chi Chuang, Shang-Wen Chang, Yi-Hsun Chiu
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Publication number: 20220302027Abstract: A semiconductor device includes a first gate structure extending along a first lateral direction. The semiconductor device includes a first interconnect structure, disposed above the first gate structure, that extends along a second lateral direction perpendicular to the first lateral direction. The first interconnect structure includes a first portion and a second portion electrically isolated from each other by a first dielectric structure. The semiconductor device includes a second interconnect structure, disposed between the first gate structure and the first interconnect structure, that electrically couples the first gate structure to the first portion of the first interconnect structure. The second interconnect structure includes a recessed portion that is substantially aligned with the first gate structure and the dielectric structure along a vertical direction.Type: ApplicationFiled: June 9, 2022Publication date: September 22, 2022Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Guo-Huei Wu, Hui-Zhong Zhuang, Chih-Liang Chen, Cheng-Chi Chuang, Shang-Wen Chang, Yi-Hsun Chiu
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Patent number: 11450751Abstract: An IC structure includes a source epitaxial structure, a drain epitaxial structure, a first silicide region, a second silicide region, a source contact, a backside via rail, a drain contact, and a front-side interconnection structure. The first silicide region is on a front-side surface and a first sidewall of the source epitaxial structure. The second silicide region is on a front-side surface of the drain epitaxial structure. The source contact is in contact with the first silicide region and has a protrusion extending past a backside surface of the source epitaxial structure. The backside via rail is in contact with the protrusion of the source contact. The drain contact is in contact with the second silicide region. The front-side interconnection structure is on a front-side surface of the source contact and a front-side surface of the drain contact.Type: GrantFiled: January 24, 2021Date of Patent: September 20, 2022Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Huan-Chieh Su, Li-Zhen Yu, Chun-Yuan Chen, Cheng-Chi Chuang, Shang-Wen Chang, Yi-Hsun Chiu, Pei-Yu Wang, Ching-Wei Tsai, Chih-Hao Wang
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Patent number: 11444018Abstract: A semiconductor device includes a first gate structure extending along a first lateral direction. The semiconductor device includes a first interconnect structure, disposed above the first gate structure, that extends along a second lateral direction perpendicular to the first lateral direction. The first interconnect structure includes a first portion and a second portion electrically isolated from each other by a first dielectric structure. The semiconductor device includes a second interconnect structure, disposed between the first gate structure and the first interconnect structure, that electrically couples the first gate structure to the first portion of the first interconnect structure. The second interconnect structure includes a recessed portion that is substantially aligned with the first gate structure and the dielectric structure along a vertical direction.Type: GrantFiled: February 27, 2020Date of Patent: September 13, 2022Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.Inventors: Guo-Huei Wu, Hui-Zhong Zhuang, Chih-Liang Chen, Cheng-Chi Chuang, Shang-Wen Chang, Yi-Hsun Chiu
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Patent number: 11437385Abstract: A static random access memory (SRAM) cell includes a first p-type semiconductor fin, a first dielectric fin, a first hybrid fin, a second hybrid fin, a second dielectric fin, and a second p-type semiconductor fin disposed in this order along a first direction and oriented lengthwise along a second direction, where each of the first and the second hybrid fins has a first portion including an n-type semiconductor material and a second portion including a dielectric material. The SRAM cell further includes n-type source/drain (S/D) epitaxial features disposed over each of the first and the second p-type semiconductor fins, p-type S/D epitaxial features disposed over the first portion of each of the first and the second hybrid fins, and S/D contacts physically contacting each of the p-type S/D epitaxial features and the second portion of each of the first and the second hybrid fins.Type: GrantFiled: July 30, 2019Date of Patent: September 6, 2022Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Chih-Hao Wang, Yi-Hsun Chiu, Yi-Hsiung Lin, Shang-Wen Chang
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Publication number: 20220262794Abstract: Methods of performing backside etching processes on source/drain regions and gate structures of semiconductor devices and semiconductor devices formed by the same are disclosed. In an embodiment, a semiconductor device includes a first transistor structure; a first interconnect structure on a front-side of the first transistor structure; and a second interconnect structure on a backside of the first transistor structure, the second interconnect structure including a first dielectric layer on the backside of the first transistor structure; a contact extending through the first dielectric layer to a source/drain region of the first transistor structure; and first spacers along sidewalls of the contact between the contact and the first dielectric layer, sidewalls of the first spacers facing the first dielectric layer being aligned with sidewalls of the source/drain region of the first transistor structure.Type: ApplicationFiled: April 29, 2022Publication date: August 18, 2022Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Yi-Hsun Chiu, Ching-Wei Tsai, Yu-Xuan Huang, Cheng-Chi Chuang, Shang-Wen Chang
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Publication number: 20220262798Abstract: Various embodiments of the present disclosure are directed towards an integrated chip (IC). The IC includes a first fin projecting vertically from a semiconductor substrate. A second fin projects vertically from the semiconductor substrate, where the second fin is spaced from the first fin, and where the first fin has a first uppermost surface that is disposed over a second uppermost surface of the second fin. A nanostructure stack is disposed over the second fin and vertically spaced from the second fin, where the nanostructure stack comprises a plurality of vertically stacked semiconductor nanostructures. A pair of first source/drain regions is disposed on the first fin, where the first source/drain regions are disposed on opposite sides of an upper portion of the first fin. A pair of second source/drain regions is disposed on the second fin, where the second source/drain regions are disposed on opposite sides of the nanostructure stack.Type: ApplicationFiled: May 2, 2022Publication date: August 18, 2022Inventors: Chih-Hao Wang, Min Cao, Shang-Wen Chang
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Patent number: 11404320Abstract: A fin field effect transistor device structure includes a first fin structure formed on a substrate. The fin field effect transistor device structure also includes a spacer layer surrounding the first fin structure. The fin field effect transistor device structure further includes a power rail formed over the substrate besides a bottom portion of the first fin structure. The fin field effect transistor device structure further includes a first contact structure formed over the first fin structure and in contact with a portion of the power rail.Type: GrantFiled: June 1, 2020Date of Patent: August 2, 2022Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Shang-Wen Chang, Yi-Hsiung Lin, Yi-Hsun Chiu
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Patent number: 11393815Abstract: The present disclosure relates to an integrated circuit. In one implementation, the integrated circuit may include a semiconductor substrate; at least one source region comprising a first doped semiconductor material; at least one drain region comprising a second doped semiconductor material; at least one gate formed between the at least one source region and the at least one drain region; and a nanosheet formed between the semiconductor substrate and the at least one gate. The nanosheet may be configured as a routing channel for the at least one gate and may have a first region having a first width and a second region having a second width. The first width may be smaller than the second width.Type: GrantFiled: August 30, 2019Date of Patent: July 19, 2022Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Yi-Hsiung Lin, Yi-Hsun Chiu, Shang-Wen Chang, Ching-Wei Tsai, Yu-Xuan Huang, Kuan-Lun Cheng, Chih-Hao Wang
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Patent number: 11355398Abstract: A semiconductor device structure, along with methods of forming such, are described. The structure includes a first and second gate electrode layers, and a dielectric feature disposed between the first and second gate electrode layers. The dielectric feature has a first surface. The structure further includes a first conductive layer disposed on the first gate electrode layer. The first conductive layer has a second surface. The structure further includes a second conductive layer disposed on the second electrode layer. The second conductive layer has a third surface, and the first, second, and third surfaces are coplanar. The structure further includes a third conductive layer disposed over the first conductive layer, a fourth conductive layer disposed over the second conductive layer, and a dielectric layer disposed on the first surface of the dielectric feature. The dielectric layer is disposed between the third conductive layer and the fourth conductive layer.Type: GrantFiled: September 21, 2020Date of Patent: June 7, 2022Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Kuan-Ting Pan, Kuo-Cheng Chiang, Shang-Wen Chang, Ching-Wei Tsai, Kuan-Lun Cheng, Chih-Hao Wang
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Patent number: 11342326Abstract: Methods of performing backside etching processes on source/drain regions and gate structures of semiconductor devices and semiconductor devices formed by the same are disclosed. In an embodiment, a semiconductor device includes a first transistor structure; a first interconnect structure on a front-side of the first transistor structure; and a second interconnect structure on a backside of the first transistor structure, the second interconnect structure including a first dielectric layer on the backside of the first transistor structure; a contact extending through the first dielectric layer to a source/drain region of the first transistor structure; and first spacers along sidewalls of the contact between the contact and the first dielectric layer, sidewalls of the first spacers facing the first dielectric layer being aligned with sidewalls of the source/drain region of the first transistor structure.Type: GrantFiled: July 30, 2020Date of Patent: May 24, 2022Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Yi-Hsun Chiu, Ching-Wei Tsai, Yu-Xuan Huang, Cheng-Chi Chuang, Shang-Wen Chang
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Patent number: 11329043Abstract: Various embodiments of the present disclosure are directed towards an integrated chip (IC). The IC includes a first fin projecting vertically from a semiconductor substrate. A second fin projects vertically from the semiconductor substrate, where the second fin is spaced from the first fin, and where the first fin has a first uppermost surface that is disposed over a second uppermost surface of the second fin. A nanostructure stack is disposed over the second fin and vertically spaced from the second fin, where the nanostructure stack comprises a plurality of vertically stacked semiconductor nanostructures. A pair of first source/drain regions is disposed on the first fin, where the first source/drain regions are disposed on opposite sides of an upper portion of the first fin. A pair of second source/drain regions is disposed on the second fin, where the second source/drain regions are disposed on opposite sides of the nanostructure stack.Type: GrantFiled: March 19, 2020Date of Patent: May 10, 2022Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chih-Hao Wang, Min Cao, Shang-Wen Chang
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Publication number: 20220130757Abstract: A method and structure for forming a local interconnect, without routing the local interconnect through an overlying metal layer. In various embodiments, a first dielectric layer is formed over a gate stack of at least one device and a second dielectric layer is formed over a contact metal layer of the at least one device. In various embodiments, a selective etching process is performed to remove the second dielectric layer and expose the contact metal layer, without substantial removal of the first dielectric layer. In some examples, a metal VIA layer is deposited over the at least one device. The metal VIA layer contacts the contact metal layer and provides a local interconnect structure. In some embodiments, a multi-level interconnect network overlying the local interconnect structure is formed.Type: ApplicationFiled: January 10, 2022Publication date: April 28, 2022Inventors: Shang-Wen CHANG, Yi-Hsiung LIN
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Publication number: 20220093471Abstract: A semiconductor device structure, along with methods of forming such, are described. The structure includes a first and second gate electrode layers, and a dielectric feature disposed between the first and second gate electrode layers. The dielectric feature has a first surface. The structure further includes a first conductive layer disposed on the first gate electrode layer. The first conductive layer has a second surface. The structure further includes a second conductive layer disposed on the second electrode layer. The second conductive layer has a third surface, and the first, second, and third surfaces are coplanar. The structure further includes a third conductive layer disposed over the first conductive layer, a fourth conductive layer disposed over the second conductive layer, and a dielectric layer disposed on the first surface of the dielectric feature. The dielectric layer is disposed between the third conductive layer and the fourth conductive layer.Type: ApplicationFiled: September 21, 2020Publication date: March 24, 2022Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Kuan-Ting PAN, Kuo-Cheng CHIANG, Shang-Wen CHANG, Ching-Wei TSAI, Kuan-Lun CHENG, Chih-Hao WANG