Patents by Inventor Shang-Wen Chang

Shang-Wen Chang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11342326
    Abstract: Methods of performing backside etching processes on source/drain regions and gate structures of semiconductor devices and semiconductor devices formed by the same are disclosed. In an embodiment, a semiconductor device includes a first transistor structure; a first interconnect structure on a front-side of the first transistor structure; and a second interconnect structure on a backside of the first transistor structure, the second interconnect structure including a first dielectric layer on the backside of the first transistor structure; a contact extending through the first dielectric layer to a source/drain region of the first transistor structure; and first spacers along sidewalls of the contact between the contact and the first dielectric layer, sidewalls of the first spacers facing the first dielectric layer being aligned with sidewalls of the source/drain region of the first transistor structure.
    Type: Grant
    Filed: July 30, 2020
    Date of Patent: May 24, 2022
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Yi-Hsun Chiu, Ching-Wei Tsai, Yu-Xuan Huang, Cheng-Chi Chuang, Shang-Wen Chang
  • Patent number: 11329043
    Abstract: Various embodiments of the present disclosure are directed towards an integrated chip (IC). The IC includes a first fin projecting vertically from a semiconductor substrate. A second fin projects vertically from the semiconductor substrate, where the second fin is spaced from the first fin, and where the first fin has a first uppermost surface that is disposed over a second uppermost surface of the second fin. A nanostructure stack is disposed over the second fin and vertically spaced from the second fin, where the nanostructure stack comprises a plurality of vertically stacked semiconductor nanostructures. A pair of first source/drain regions is disposed on the first fin, where the first source/drain regions are disposed on opposite sides of an upper portion of the first fin. A pair of second source/drain regions is disposed on the second fin, where the second source/drain regions are disposed on opposite sides of the nanostructure stack.
    Type: Grant
    Filed: March 19, 2020
    Date of Patent: May 10, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chih-Hao Wang, Min Cao, Shang-Wen Chang
  • Publication number: 20220130757
    Abstract: A method and structure for forming a local interconnect, without routing the local interconnect through an overlying metal layer. In various embodiments, a first dielectric layer is formed over a gate stack of at least one device and a second dielectric layer is formed over a contact metal layer of the at least one device. In various embodiments, a selective etching process is performed to remove the second dielectric layer and expose the contact metal layer, without substantial removal of the first dielectric layer. In some examples, a metal VIA layer is deposited over the at least one device. The metal VIA layer contacts the contact metal layer and provides a local interconnect structure. In some embodiments, a multi-level interconnect network overlying the local interconnect structure is formed.
    Type: Application
    Filed: January 10, 2022
    Publication date: April 28, 2022
    Inventors: Shang-Wen CHANG, Yi-Hsiung LIN
  • Publication number: 20220093471
    Abstract: A semiconductor device structure, along with methods of forming such, are described. The structure includes a first and second gate electrode layers, and a dielectric feature disposed between the first and second gate electrode layers. The dielectric feature has a first surface. The structure further includes a first conductive layer disposed on the first gate electrode layer. The first conductive layer has a second surface. The structure further includes a second conductive layer disposed on the second electrode layer. The second conductive layer has a third surface, and the first, second, and third surfaces are coplanar. The structure further includes a third conductive layer disposed over the first conductive layer, a fourth conductive layer disposed over the second conductive layer, and a dielectric layer disposed on the first surface of the dielectric feature. The dielectric layer is disposed between the third conductive layer and the fourth conductive layer.
    Type: Application
    Filed: September 21, 2020
    Publication date: March 24, 2022
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Kuan-Ting PAN, Kuo-Cheng CHIANG, Shang-Wen CHANG, Ching-Wei TSAI, Kuan-Lun CHENG, Chih-Hao WANG
  • Publication number: 20220068716
    Abstract: A semiconductor device structure, along with methods of forming such, are described. The structure includes a first fin, a second fin adjacent the first fin, and a third fin adjacent the second fin. The structure further includes a first source/drain epitaxial feature merged with a second source/drain epitaxial feature. The structure further includes a third source/drain epitaxial feature, and a first liner positioned at a first distance away from a first plane defined by a first sidewall of the first fin and a second distance away from a second plane defined by a second sidewall of the second fin. The first distance is substantially the same as the second distance, and the merged first and second source/drain epitaxial features is disposed over the first liner. The structure further includes a dielectric feature disposed between the second source/drain epitaxial feature and the third source/drain epitaxial feature.
    Type: Application
    Filed: August 27, 2020
    Publication date: March 3, 2022
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Kuan-Ting PAN, Kuo-Cheng CHIANG, Shi-Ning JU, Shang-Wen CHANG, Chih-Hao WANG
  • Patent number: 11222842
    Abstract: A method and structure for forming a local interconnect, without routing the local interconnect through an overlying metal layer. In various embodiments, a first dielectric layer is formed over a gate stack of at least one device and a second dielectric layer is formed over a contact metal layer of the at least one device. In various embodiments, a selective etching process is performed to remove the second dielectric layer and expose the contact metal layer, without substantial removal of the first dielectric layer. In some examples, a metal VIA layer is deposited over the at least one device. The metal VIA layer contacts the contact metal layer and provides a local interconnect structure. In some embodiments, a multi-level interconnect network overlying the local interconnect structure is formed.
    Type: Grant
    Filed: July 27, 2018
    Date of Patent: January 11, 2022
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Shang-Wen Chang, Yi-Hsiung Lin
  • Publication number: 20210398852
    Abstract: A structure and a formation method of a semiconductor device are provided. The method includes forming a first source/drain structure and a second source/drain structure over a semiconductor substrate. The method also includes forming a dielectric layer over the first source/drain structure and the second source/drain structure and forming a conductive contact on the first source/drain structure. The method further includes forming a first conductive via over the conductive contact, and the first conductive via is misaligned with the first source/drain structure. In addition, the method includes forming a second conductive via directly above the second source/drain structure, and the second conductive via is longer than the first conductive via.
    Type: Application
    Filed: September 2, 2021
    Publication date: December 23, 2021
    Inventors: Yi-Hsiung LIN, Yi-Hsun CHIU, Shang-Wen CHANG
  • Publication number: 20210399109
    Abstract: An IC structure includes a source epitaxial structure, a drain epitaxial structure, a first silicide region, a second silicide region, a source contact, a backside via rail, a drain contact, and a front-side interconnection structure. The first silicide region is on a front-side surface and a first sidewall of the source epitaxial structure. The second silicide region is on a front-side surface of the drain epitaxial structure. The source contact is in contact with the first silicide region and has a protrusion extending past a backside surface of the source epitaxial structure. The backside via rail is in contact with the protrusion of the source contact. The drain contact is in contact with the second silicide region. The front-side interconnection structure is on a front-side surface of the source contact and a front-side surface of the drain contact.
    Type: Application
    Filed: January 24, 2021
    Publication date: December 23, 2021
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Huan-Chieh SU, Li-Zhen YU, Chun-Yuan CHEN, Cheng-Chi CHUANG, Shang-Wen CHANG, Yi-Hsun CHIU, Pei-Yu WANG, Ching-Wei TSAI, Chih-Hao WANG
  • Publication number: 20210375761
    Abstract: In an embodiment, a method of forming a structure includes forming a first transistor and a second transistor over a first substrate; forming a front-side interconnect structure over the first transistor and the second transistor; etching at least a backside of the first substrate to expose the first transistor and the second transistor; forming a first backside via electrically connected to the first transistor; forming a second backside via electrically connected to the second transistor; depositing a dielectric layer over the first backside via and the second backside via; forming a first conductive line in the dielectric layer, the first conductive line being a power rail electrically connected to the first transistor through the first backside via; and forming a second conductive line in the dielectric layer, the second conductive line being a signal line electrically connected to the second transistor through the second backside via.
    Type: Application
    Filed: December 18, 2020
    Publication date: December 2, 2021
    Inventors: Shang-Wen Chang, Yi-Hsun Chiu, Cheng-Chi Chuang, Ching-Wei Tsai, Wei-Cheng Lin, Shih-Wei Peng, Jiann-Tyng Tzeng
  • Publication number: 20210376076
    Abstract: In an embodiment, a device includes: a power rail contact; an isolation region on the power rail contact; a first dielectric fin on the isolation region; a second dielectric fin adjacent the isolation region and the power rail contact; a first source/drain region on the second dielectric fin; and a source/drain contact between the first source/drain region and the first dielectric fin, the source/drain contact contacting a top surface of the first source/drain region, a side surface of the first source/drain region, and a top surface of the power rail contact.
    Type: Application
    Filed: December 18, 2020
    Publication date: December 2, 2021
    Inventors: Huan-Chieh Su, Cheng-Chi Chuang, Shang-Wen Chang, Yi-Hsun Chiu, Pei-Yu Wang, Ching-Wei Tsai, Chih-Hao Wang
  • Publication number: 20210358817
    Abstract: A semiconductor structure includes a first semiconductor fin and a second semiconductor fin adjacent to the first semiconductor fin, a first epitaxial source/drain (S/D) feature disposed over the first semiconductor fin, a second epitaxial S/D feature disposed over the second semiconductor fin, an interlayer dielectric (ILD) layer disposed over the first and the second epitaxial S/D features, and an S/D contact disposed over and contacting the first epitaxial S/D feature, where a portion of the S/D contact laterally extends over the second epitaxial S/D feature, and the portion is separated from the second epitaxial S/D feature by the ILD layer.
    Type: Application
    Filed: August 2, 2021
    Publication date: November 18, 2021
    Inventors: Yi-Hsiung Lin, Yi-Hsun Chiu, Shang-Wen Chang
  • Publication number: 20210351175
    Abstract: The disclosed circuit includes a first and a second active region (AR) spaced a spacing S along a direction in a first standard cell (SC) that spans Dl along the direction between a first and a second cell edge (CE). Each of the first and second ARs spans a first width W1 along the direction; a third and a fourth AR spaced S in a second SC that spans a second dimension Ds along the direction between a third and a fourth CE; and gate stacks extend from the fourth CE of the second SC to the first CE of the first SC, wherein Ds<Dl; each of the third and fourth ARs spans a second width W2 along the direction; W2<W1; and the third CE is aligned with and contacts the second CE. The first and second ARs have a structure different from the third and fourth ARs.
    Type: Application
    Filed: July 26, 2021
    Publication date: November 11, 2021
    Inventors: Chih-Hao Wang, Shang-Wen Chang, Min Cao
  • Publication number: 20210343712
    Abstract: A device includes a first semiconductor strip and a second semiconductor strip extending longitudinally in a first direction, where the first semiconductor strip and the second semiconductor strip are spaced apart from each other in a second direction. The device also includes a power supply line located between the first semiconductor strip and the second semiconductor strip. A top surface of the power supply line is recessed in comparison to a top surface of the first semiconductor strip. A source feature is disposed on a source region of the first semiconductor strip, and a source contact electrically couples the source feature to the power supply line. The source contact includes a lateral portion contacting a top surface of the source feature, and a vertical portion extending along a sidewall of the source feature towards the power supply line to physically contact the power supply line.
    Type: Application
    Filed: July 12, 2021
    Publication date: November 4, 2021
    Inventors: Yi-Hsiung Lin, Shang-Wen Chang, Yi-Hsun Chiu
  • Publication number: 20210335783
    Abstract: Methods of performing backside etching processes on source/drain regions and gate structures of semiconductor devices and semiconductor devices formed by the same are disclosed. In an embodiment, a semiconductor device includes a first transistor structure; a first interconnect structure on a front-side of the first transistor structure; and a second interconnect structure on a backside of the first transistor structure, the second interconnect structure including a first dielectric layer on the backside of the first transistor structure; a contact extending through the first dielectric layer to a source/drain region of the first transistor structure; and first spacers along sidewalls of the contact between the contact and the first dielectric layer, sidewalls of the first spacers facing the first dielectric layer being aligned with sidewalls of the source/drain region of the first transistor structure.
    Type: Application
    Filed: July 30, 2020
    Publication date: October 28, 2021
    Inventors: Yi-Hsun Chiu, Ching-Wei Tsai, Yu-Xuan Huang, Cheng-Chi Chuang, Shang-Wen Chang
  • Publication number: 20210296318
    Abstract: Various embodiments of the present disclosure are directed towards an integrated chip (IC). The IC includes a first fin projecting vertically from a semiconductor substrate. A second fin projects vertically from the semiconductor substrate, where the second fin is spaced from the first fin, and where the first fin has a first uppermost surface that is disposed over a second uppermost surface of the second fin. A nanostructure stack is disposed over the second fin and vertically spaced from the second fin, where the nanostructure stack comprises a plurality of vertically stacked semiconductor nanostructures. A pair of first source/drain regions is disposed on the first fin, where the first source/drain regions are disposed on opposite sides of an upper portion of the first fin. A pair of second source/drain regions is disposed on the second fin, where the second source/drain regions are disposed on opposite sides of the nanostructure stack.
    Type: Application
    Filed: March 19, 2020
    Publication date: September 23, 2021
    Inventors: Chih-Hao Wang, Min Cao, Shang-Wen Chang
  • Patent number: 11127631
    Abstract: A structure and a formation method of a semiconductor device are provided. The semiconductor device structure includes a first epitaxial structure and a second epitaxial structure over a semiconductor substrate. The semiconductor device structure also includes a first conductive via electrically connected to the first epitaxial structure through a conductive contact. The first conductive via is misaligned with the first epitaxial structure. The semiconductor device structure further includes a second conductive via electrically connected to the second epitaxial structure. The second conductive via is aligned with the second epitaxial structure.
    Type: Grant
    Filed: October 2, 2018
    Date of Patent: September 21, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Yi-Hsiung Lin, Yi-Hsun Chiu, Shang-Wen Chang
  • Patent number: 11121138
    Abstract: A semiconductor device includes a transistor and a memory pickup cell formed over a well in a substrate. The transistor includes a first fin having a first width and two first source/drain features on the first fin. The pickup cell includes a second fin having a second width and two second source/drain features on the second fin. The well, the first fin, the second fin, and the second source/drain feature are of a first conductivity type. The first source/drain features are of a second conductivity type opposite to the first conductivity type. The second width is at least three times of the first width. The pickup cell further includes a stack of semiconductor layers over the second fin and connecting the two second source/drain features.
    Type: Grant
    Filed: April 24, 2020
    Date of Patent: September 14, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Yi-Hsun Chiu, Cheng-Chi Chuang, Shang-Wen Chang
  • Publication number: 20210272895
    Abstract: A semiconductor device includes a first gate structure extending along a first lateral direction. The semiconductor device includes a first interconnect structure, disposed above the first gate structure, that extends along a second lateral direction perpendicular to the first lateral direction. The first interconnect structure includes a first portion and a second portion electrically isolated from each other by a first dielectric structure. The semiconductor device includes a second interconnect structure, disposed between the first gate structure and the first interconnect structure, that electrically couples the first gate structure to the first portion of the first interconnect structure. The second interconnect structure includes a recessed portion that is substantially aligned with the first gate structure and the dielectric structure along a vertical direction.
    Type: Application
    Filed: February 27, 2020
    Publication date: September 2, 2021
    Inventors: Guo-Huei Wu, Hui-Zhong Zhuang, Chih-Liang Chen, Cheng-Chi Chuang, Shang-Wen Chang, Yi-Hsun Chiu
  • Patent number: 11081403
    Abstract: A method includes forming an interlayer dielectric (ILD) layer over a first epitaxial source/drain (S/D) feature and a second epitaxial S/D feature, where the first epitaxial S/D feature is disposed adjacent to the second epitaxial S/D feature, forming a dummy contact feature in the ILD layer over the first epitaxial S/D feature, removing a portion of the dummy contact feature and a portion of the ILD layer disposed above the second epitaxial S/D feature to form a first trench, removing a remaining portion of the dummy contact feature to form a second trench, and forming a metal S/D contact in the first and the second trenches.
    Type: Grant
    Filed: April 24, 2019
    Date of Patent: August 3, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Yi-Hsiung Lin, Yi-Hsun Chiu, Shang-Wen Chang
  • Patent number: 11075195
    Abstract: The disclosed circuit includes a first and a second active region (AR) spaced a spacing S along a direction in a first standard cell (SC) that spans Dl along the direction between a first and a second cell edge (CE). Each of the first and second ARs spans a first width W1 along the direction; a third and a fourth AR spaced S in a second SC that spans a second dimension Ds along the direction between a third and a fourth CE; and gate stacks extend from the fourth CE of the second SC to the first CE of the first SC, wherein Ds<Dl; each of the third and fourth ARs spans a second width W2 along the direction; W2<W1; and the third CE is aligned with and contacts the second CE. The first and second ARs have a structure different from the third and fourth ARs.
    Type: Grant
    Filed: December 26, 2019
    Date of Patent: July 27, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chih-Hao Wang, Shang-Wen Chang, Min Cao