Patents by Inventor Shang-Wen Chang

Shang-Wen Chang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20230369324
    Abstract: Methods of performing backside etching processes on source/drain regions and gate structures of semiconductor devices and semiconductor devices formed by the same are disclosed. In an embodiment, a semiconductor device includes a first transistor structure; a first interconnect structure on a front-side of the first transistor structure; and a second interconnect structure on a backside of the first transistor structure, the second interconnect structure including a first dielectric layer on the backside of the first transistor structure; a contact extending through the first dielectric layer to a source/drain region of the first transistor structure; and first spacers along sidewalls of the contact between the contact and the first dielectric layer, sidewalls of the first spacers facing the first dielectric layer being aligned with sidewalls of the source/drain region of the first transistor structure.
    Type: Application
    Filed: July 25, 2023
    Publication date: November 16, 2023
    Inventors: Yi-Hsun Chiu, Ching-Wei Tsai, Yu-Xuan Huang, Cheng-Chi Chuang, Shang-Wen Chang
  • Patent number: 11810917
    Abstract: Methods of performing backside etching processes on source/drain regions and gate structures of semiconductor devices and semiconductor devices formed by the same are disclosed. In an embodiment, a semiconductor device includes a first transistor structure; a first interconnect structure on a front-side of the first transistor structure; and a second interconnect structure on a backside of the first transistor structure, the second interconnect structure including a first dielectric layer on the backside of the first transistor structure; a contact extending through the first dielectric layer to a source/drain region of the first transistor structure; and first spacers along sidewalls of the contact between the contact and the first dielectric layer, sidewalls of the first spacers facing the first dielectric layer being aligned with sidewalls of the source/drain region of the first transistor structure.
    Type: Grant
    Filed: April 29, 2022
    Date of Patent: November 7, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Yi-Hsun Chiu, Ching-Wei Tsai, Yu-Xuan Huang, Cheng-Chi Chuang, Shang-Wen Chang
  • Publication number: 20230343838
    Abstract: In a method of manufacturing a semiconductor device, a field effect transistor (FET) having a metal gate structure, a source and a drain over a substrate is formed. A first frontside contact disposed between dummy metal gate structures is formed over an isolation insulating layer. A frontside wiring layer is formed over the first frontside contact. A part of the substrate is removed from a backside of the substrate so that a bottom of the isolation insulating layer is exposed. A first opening is formed in the isolation insulating layer from the bottom of the isolation insulating layer to expose a bottom of the first frontside contact. A first backside contact is formed by filling the first opening with a conductive material to connect the first frontside contact.
    Type: Application
    Filed: July 28, 2022
    Publication date: October 26, 2023
    Inventors: Shang-Wen CHANG, Li-Zhen YU, Lin-Yu HUANG, Huan-Chieh SU
  • Patent number: 11791215
    Abstract: A fin field effect transistor device structure is provided. A fin field effect transistor device structure includes a first fin structure and a second fin structure on a substrate. The fin field effect transistor device structure also includes a spacer layer surrounding the first fin structure and the second fin structure. The fin field effect transistor device structure further includes a power rail over the spacer layer between the first fin structure and the second fin structure. In addition, the fin field effect transistor device structure includes a first contact structure covering the first fin structure and connected to the power rail.
    Type: Grant
    Filed: July 21, 2022
    Date of Patent: October 17, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Shang-Wen Chang, Yi-Hsiung Lin, Yi-Hsun Chiu
  • Publication number: 20230326808
    Abstract: A semiconductor structure includes a first semiconductor fin and a second semiconductor fin adjacent to the first semiconductor fin. The first and the second semiconductor fins extend lengthwise along a first direction over a substrate. A metal gate structure is disposed over the first and second semiconductor fins, the metal gate structure extending lengthwise along a second direction perpendicular to the first direction. A first epitaxial source/drain (S/D) feature is disposed over the first semiconductor fin, and a second epitaxial S/D feature is disposed over the second semiconductor fin. An interlayer dielectric (ILD) layer is disposed over the first and the second epitaxial S/D features. And an S/D contact is disposed directly above the first and second epitaxial S/D features. The S/D contact directly contacts the first epitaxial S/D feature, and the S/D contact is isolated from the second epitaxial S/D feature by the ILD layer.
    Type: Application
    Filed: June 16, 2023
    Publication date: October 12, 2023
    Inventors: Yi-Hsiung Lin, Yi-Hsun Chiu, Shang-Wen Chang
  • Patent number: 11784233
    Abstract: An IC structure includes a source epitaxial structure, a drain epitaxial structure, a first silicide region, a second silicide region, a source contact, a backside via rail, a drain contact, and a front-side interconnection structure. The first silicide region is on a front-side surface, a first sidewall of the source epitaxial structure, and a second sidewall of the source epitaxial structure. The second silicide region is on a front-side surface of the drain epitaxial structure. The source contact is in contact with the first silicide region and has a protrusion extending past a backside surface of the source epitaxial structure. The backside via rail is in contact with the protrusion of the source contact. The drain contact is in contact with the second silicide region. The front-side interconnection structure is on a front-side surface of the source contact and a front-side surface of the drain contact.
    Type: Grant
    Filed: August 9, 2022
    Date of Patent: October 10, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Huan-Chieh Su, Li-Zhen Yu, Chun-Yuan Chen, Cheng-Chi Chuang, Shang-Wen Chang, Yi-Hsun Chiu, Pei-Yu Wang, Ching-Wei Tsai, Chih-Hao Wang
  • Patent number: 11764213
    Abstract: A semiconductor device includes a substrate and a first active region on a first side of the substrate. The semiconductor device further includes a first gate structure surrounding a first portion of the first active region. The semiconductor device further includes a second active region on a second side of the substrate, wherein the second side is opposite the first side. The semiconductor device further includes a second gate structure surrounding a first portion of the second active region. The semiconductor device further includes a gate via extending through the substrate, wherein the gate via directly connects to the first gate structure, and the gate via directly connects to the second gate structure.
    Type: Grant
    Filed: March 26, 2021
    Date of Patent: September 19, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chih-Yu Lai, Chih-Liang Chen, Chi-Yu Lu, Shang-Syuan Ciou, Hui-Zhong Zhuang, Ching-Wei Tsai, Shang-Wen Chang
  • Patent number: 11764203
    Abstract: The disclosed circuit includes a first and a second active region (AR) spaced a spacing S along a direction in a first standard cell (SC) that spans Dl along the direction between a first and a second cell edge (CE). Each of the first and second ARs spans a first width W1 along the direction; a third and a fourth AR spaced S in a second SC that spans a second dimension Ds along the direction between a third and a fourth CE; and gate stacks extend from the fourth CE of the second SC to the first CE of the first SC, wherein Ds<Dl; each of the third and fourth ARs spans a second width W2 along the direction; W2<W1; and the third CE is aligned with and contacts the second CE. The first and second ARs have a structure different from the third and fourth ARs.
    Type: Grant
    Filed: July 26, 2021
    Date of Patent: September 19, 2023
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chih-Hao Wang, Shang-Wen Chang, Min Cao
  • Patent number: 11764154
    Abstract: An integrated circuit device includes a first-type active-region semiconductor structure, a first gate-conductor, a second-type active-region semiconductor structure that is stacked with the first-type active-region semiconductor structure, and a second gate-conductor. The integrated circuit device also includes a front-side conductive layer above the two active-region semiconductor structures and a back-side conductive layer below the two active-region semiconductor structures. The integrated circuit device also includes a front-side power rail and a front-side signal line in the front-side conductive layer and includes a back-side power rail and a back-side signal line in the back-side conductive layer. The integrated circuit device also includes a first source conductive segment connected to the front-side power rail and a second source conductive segment connected to the back-side power rail.
    Type: Grant
    Filed: July 30, 2021
    Date of Patent: September 19, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chih-Liang Chen, Guo-Huei Wu, Ching-Wei Tsai, Shang-Wen Chang, Li-Chun Tien
  • Publication number: 20230290683
    Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a first epitaxial structure and a second epitaxial structure spaced apart from the first epitaxial structure. The semiconductor device structure also includes a conductive contact electrically connected to the first epitaxial structure and a first conductive via over the conductive contact. The semiconductor device structure further includes a second conductive via directly above the second epitaxial structure. The second conductive via is longer than the first conductive via.
    Type: Application
    Filed: May 17, 2023
    Publication date: September 14, 2023
    Inventors: Yi-Hsiung LIN, Yi-Hsun CHIU, Shang-Wen CHANG
  • Publication number: 20230282519
    Abstract: A semiconductor device structure, along with methods of forming such, are described. The structure includes a first fin, a second fin adjacent the first fin, and a third fin adjacent the second fin. The structure further includes a first source/drain epitaxial feature merged with a second source/drain epitaxial feature. The structure further includes a third source/drain epitaxial feature, and a first liner positioned at a first distance away from a first plane defined by a first sidewall of the first fin and a second distance away from a second plane defined by a second sidewall of the second fin. The first distance is substantially the same as the second distance, and the merged first and second source/drain epitaxial features is disposed over the first liner. The structure further includes a dielectric feature disposed between the second source/drain epitaxial feature and the third source/drain epitaxial feature.
    Type: Application
    Filed: May 9, 2023
    Publication date: September 7, 2023
    Inventors: Kuan-Ting PAN, Kuo-Cheng CHIANG, Shi-Ning JU, Shang-Wen CHANG, Chih-Hao WANG
  • Patent number: 11735482
    Abstract: A semiconductor device structure, along with methods of forming such, are described. The structure includes a first and second gate electrode layers, and a dielectric feature disposed between the first and second gate electrode layers. The dielectric feature has a first surface. The structure further includes a first conductive layer disposed on the first gate electrode layer. The first conductive layer has a second surface. The structure further includes a second conductive layer disposed on the second gate electrode layer. The second conductive layer has a third surface, and the first, second, and third surfaces are coplanar. The structure further includes a third conductive layer disposed over the first conductive layer, a fourth conductive layer disposed over the second conductive layer, and a dielectric layer disposed on the first surface of the dielectric feature. The dielectric layer is disposed between the third conductive layer and the fourth conductive layer.
    Type: Grant
    Filed: June 6, 2022
    Date of Patent: August 22, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Kuan-Ting Pan, Kuo-Cheng Chiang, Shang-Wen Chang, Ching-Wei Tsai, Kuan-Lun Cheng, Chih-Hao Wang
  • Patent number: 11694927
    Abstract: A structure and a formation method of a semiconductor device are provided. The method includes forming a first source/drain structure and a second source/drain structure over a semiconductor substrate. The method also includes forming a dielectric layer over the first source/drain structure and the second source/drain structure and forming a conductive contact on the first source/drain structure. The method further includes forming a first conductive via over the conductive contact, and the first conductive via is misaligned with the first source/drain structure. In addition, the method includes forming a second conductive via directly above the second source/drain structure, and the second conductive via is longer than the first conductive via.
    Type: Grant
    Filed: September 2, 2021
    Date of Patent: July 4, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Yi-Hsiung Lin, Yi-Hsun Chiu, Shang-Wen Chang
  • Patent number: 11682590
    Abstract: A semiconductor structure includes a first semiconductor fin and a second semiconductor fin adjacent to the first semiconductor fin, a first epitaxial source/drain (S/D) feature disposed over the first semiconductor fin, a second epitaxial S/D feature disposed over the second semiconductor fin, an interlayer dielectric (ILD) layer disposed over the first and the second epitaxial S/D features, and an S/D contact disposed over and contacting the first epitaxial S/D feature, where a portion of the S/D contact laterally extends over the second epitaxial S/D feature, and the portion is separated from the second epitaxial S/D feature by the ILD layer.
    Type: Grant
    Filed: August 2, 2021
    Date of Patent: June 20, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Yi-Hsiung Lin, Yi-Hsun Chiu, Shang-Wen Chang
  • Patent number: 11676864
    Abstract: A semiconductor device structure, along with methods of forming such, are described. The structure includes a first fin, a second fin adjacent the first fin, and a third fin adjacent the second fin. The structure further includes a first source/drain epitaxial feature merged with a second source/drain epitaxial feature. The structure further includes a third source/drain epitaxial feature, and a first liner positioned at a first distance away from a first plane defined by a first sidewall of the first fin and a second distance away from a second plane defined by a second sidewall of the second fin. The first distance is substantially the same as the second distance, and the merged first and second source/drain epitaxial features is disposed over the first liner. The structure further includes a dielectric feature disposed between the second source/drain epitaxial feature and the third source/drain epitaxial feature.
    Type: Grant
    Filed: August 27, 2020
    Date of Patent: June 13, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Kuan-Ting Pan, Kuo-Cheng Chiang, Shi-Ning Ju, Shang-Wen Chang, Chih-Hao Wang
  • Publication number: 20230067952
    Abstract: A semiconductor device includes a base isolation layer, a first transistor with a first source electrode at a first side of the base isolation layer. A bridge pillar extends through the base isolation layer, and a metal electrode electrically connects the bridge pillar to the first source electrode. The metal electrode and the first source electrode are at the same side of the base isolation layer. A second metal electrode at an opposite side of the base isolation layer electrically connects to the bridge pillar and to a conductive line at the second side of the base isolation layer.
    Type: Application
    Filed: August 31, 2021
    Publication date: March 2, 2023
    Inventors: Chih-Yu LAI, Chih-Liang CHEN, Ching-Wei TSAI, Shang-Wen CHANG, Li-Chun TIEN
  • Publication number: 20230036522
    Abstract: An integrated circuit device includes a first-type active-region semiconductor structure, a first gate-conductor, a second-type active-region semiconductor structure that is stacked with the first-type active-region semiconductor structure, and a second gate-conductor. The integrated circuit device also includes a front-side conductive layer above the two active-region semiconductor structures and a back-side conductive layer below the two active-region semiconductor structures. The integrated circuit device also includes a front-side power rail and a front-side signal line in the front-side conductive layer and includes a back-side power rail and a back-side signal line in the back-side conductive layer. The integrated circuit device also includes a first source conductive segment connected to the front-side power rail and a second source conductive segment connected to the back-side power rail.
    Type: Application
    Filed: July 30, 2021
    Publication date: February 2, 2023
    Inventors: Chih-Liang CHEN, Guo-Huei WU, Ching-Wei TSAI, Shang-Wen CHANG, Li-Chun TIEN
  • Publication number: 20230013764
    Abstract: Semiconductor devices including backside capacitors and methods of forming the same are disclosed. In an embodiment, a semiconductor device includes a first transistor structure; a front-side interconnect structure on a front-side of the first transistor structure, the front-side interconnect structure including a front-side conductive line; a backside interconnect structure on a backside of the first transistor structure, the backside interconnect structure including a backside conductive line, the backside conductive line having a line width greater than a line width of the front-side conductive line; and a first capacitor structure coupled to the backside interconnect structure.
    Type: Application
    Filed: March 1, 2022
    Publication date: January 19, 2023
    Inventors: Chih-Chao Chou, Yi-Hsun Chiu, Shang-Wen Chang, Ching-Wei Tsai, Chih-Hao Wang, Min Cao
  • Publication number: 20230009640
    Abstract: Semiconductor devices and methods are provided which facilitate performing physical failure analysis (PFA) testing from a backside of the devices. In at least one example, a device is provided that includes a semiconductor device layer including a plurality of diffusion regions. A first interconnection structure is disposed on a first side of the semiconductor device layer, and the first interconnection structure includes at least one electrical contact. A second interconnection structure is disposed on a second side of the semiconductor device layer, and the second interconnection structure includes a plurality of backside power rails. Each of the backside power rails at least partially overlaps a respective diffusion region of the plurality of diffusion regions and defines openings which expose portions of the respective diffusion region at the second side of the semiconductor device layer.
    Type: Application
    Filed: May 6, 2022
    Publication date: January 12, 2023
    Inventors: Chih-Chao CHOU, Yi-Hsun CHIU, Shang-Wen CHANG, Ching-Wei TSAI, Chih-Hao WANG
  • Patent number: 11532556
    Abstract: The present disclosure provides one embodiment of a semiconductor structure. The semiconductor structure includes a substrate having a front side and a back side; a gate stack formed on the front side of the substrate and disposed on an active region of the substrate; a first source/drain feature formed on the active region and disposed at an edge of the gate stack; a backside power rail formed on the back side of the substrate; and a backside contact feature interposed between the backside power rail and the first source/drain feature, and electrically connecting the backside power rail to the first source/drain feature. The backside contact feature further includes a first silicide layer on the back side of the substrate.
    Type: Grant
    Filed: July 30, 2020
    Date of Patent: December 20, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Yu-Xuan Huang, Ching-Wei Tsai, Cheng-Ting Chung, Cheng-Chi Chuang, Shang-Wen Chang