Abstract: An in memory searching device, including multiple first memory cell strings, a controller, and a sensing circuit, is provided. The first memory cell strings are commonly coupled to a first common bit line. Each of the first memory strings includes multiple first data storage layers. The first data storage layers respectively include multiple first memory cell pairs. The first memory cell pairs are respectively coupled to multiple first word line pairs. The controller selects at least one of the first data storage layers to be at least one selected data storage layer, and provides search data to at least one selected word line pair corresponding to the at least one selected data storage layer. The sensing circuit senses a current on the first common bit line to generate a search result.

Abstract: A satellite communication system and a method for managing radio resource of a non-terrestrial network are provided. The method includes: transmitting, by a first satellite, a first resource scheduling assignment when leaving a service area of the non-terrestrial network; receiving, by a second satellite, a second resource scheduling assignment corresponding to the first scheduling assignment when entering the service area; and accessing, by the second satellite, the radio resource according to the second resource scheduling assignment.

Abstract: The present disclosure relates generally to ion implantation, and more particularly, to systems and processes for adjusting a ribbon beam angle of an ion implantation system. An exemplary ion implantation system includes an ion source configured to generate a ribbon beam, a wafer chuck configured to hold a wafer during implantation by the ribbon beam, a dipole magnet disposed between the ion source and the wafer chuck, and a controller. The dipole magnet includes at least two coils configured to adjust a ribbon beam angle of the ribbon beam at one or more locations along a path of the ribbon beam between the ion source and the wafer held in the wafer chuck. The controller is configured to control the ion source, the wafer chuck, and the dipole magnet.

Abstract: An imaging optical lens assembly includes five optical elements with refractive power. The five optical elements, in order from an object side to an image side along an optical path, are a first optical element, a second optical element, a third optical element, a fourth optical element, and a fifth optical element. The first optical element has an object-side surface being concave in a paraxial region thereof. The third optical element has negative refractive power.

Abstract: In some aspects of the present disclosure, a bandgap reference circuit includes a first current mirror and a first resistor coupled to the first current mirror to provide a proportional to absolute temperature (PTAT) voltage. The circuit includes a second current mirror and a bipolar junction transistor (BJT) device coupled to the second current mirror to provide a complementary to the absolute temperature (CTAT) voltage. The circuit includes an output node to provide a bandgap voltage that is a weighted sum of the PTAT voltage and the CTAT voltage. The circuit includes a second resistor coupled between the output node and a first node, wherein the first node is coupled between the first resistor and the first current mirror. The circuit includes a third resistor coupled between the output node and a second node, wherein the second node is coupled between the BJT device and the second current mirror.

Abstract: A method and system for generating a clock distribution circuit for each macro circuit in an ASIC design are disclosed herein. In some embodiments, a method for generating a clock distribution circuit receives the ASIC design specified in a hardware description language (HDL), places each macro circuit in allocated locations on a semiconductor substrate, generates a custom clock skew information for each macro circuit based on a macro clock delay model, generates a clock distribution circuit for each macro circuit placed on the semiconductor substrate based on the generated custom clock skew information, modifies the clock distribution circuit if the generated clock distribution circuit does not meet timing requirements of the ASIC design, and outputs a physical layout of the ASIC design for manufacturing under a semiconductor fabrication process.

Abstract: The present disclosure provides a crack detection unit (CDU), a semiconductor die, and a method of detecting a crack of a semiconductor die. The CDU comprises a switching circuit, a crack sensor, and a logic circuit. The switching circuit is configured to enable the crack sensor. The crack sensor is configured to be electrically connected to the switching circuit, the ground, and an operating voltage. The logic circuit is configured to be electrically connected to the switching circuit and the crack sensor, wherein the CDU is enabled based on an input of the logic circuit. The output of the logic circuit indicates whether the crack sensor contains a crack.

Abstract: An IC device includes a first anti-fuse structure including a first dielectric layer between a first gate conductor and an active area, a second anti-fuse structure including a second dielectric layer between a second gate conductor and the active area, and a first pair of conductive segments electrically connected to the first and second gate conductors and aligned along a row direction perpendicular to a column direction of the first and second gate conductors. The active area is included in a plurality of active areas, the first pair of conductive segments is included in a plurality of pairs of conductive segments, and adjacent pairs of conductive segments of the plurality of pairs of conductive segments are separated by a total of two active areas of the plurality of active areas.

Abstract: A method and system for generating a clock distribution circuit for each macro circuit in an ASIC design are disclosed herein. In some embodiments, a method for generating a clock distribution circuit receives the ASIC design specified in a hardware description language (HDL), places each macro circuit in allocated locations on a semiconductor substrate, generates a custom clock skew information for each macro circuit based on a macro clock delay model, generates a clock distribution circuit for each macro circuit placed on the semiconductor substrate based on the generated custom clock skew information, modifies the clock distribution circuit if the generated clock distribution circuit does not meet timing requirements of the ASIC design, and outputs a physical layout of the ASIC design for manufacturing under a semiconductor fabrication process.

Abstract: A memory device comprises a source region, a drain region, a channel region, a gate dielectric layer, an MTJ stack, and a metal gate. The source region and the drain region are over a substrate. The channel region is between the source region and the drain region. The gate dielectric layer is over the channel region. The MTJ stack is over the gate dielectric layer. The MTJ stack comprises a first ferromagnetic layer, a second ferromagnetic layer with a switchable magnetization, and a tunnel barrier layer between the first and second ferromagnetic layers. The metal gate is over the MTJ stack.

Abstract: A vehicle gearshift autonomous control device including a first actuator module, a second actuator module and an electronic control unit, is provided in an add-on manner to retrofit the vehicle transmission with both autonomous and human control gearshift functions. In an autonomous gearshift mode, the electronic control unit executes the vehicle gearshift autonomous control method and receives an autonomous gearshift command to drive the first actuator module to push a shift lever to implement a lateral shift selection, or to drive the second actuator module to spin a spin lever to implement a longitudinal gearshift. For vehicle security, whenever a vehicle gearshift autonomous control device failure or a human control gearshift intervention is detected in the autonomous gearshift mode, the electronic control unit shuts off the autonomous gearshift mode and switches to a human control gearshift mode to perform the human control gearshift function.

Abstract: In some aspects of the present disclosure, a bandgap reference circuit includes a first current mirror and a first resistor coupled to the first current mirror to provide a proportional to absolute temperature (PTAT) voltage. The circuit includes a second current mirror and a bipolar junction transistor (BJT) device coupled to the second current mirror to provide a complementary to the absolute temperature (CTAT) voltage. The circuit includes an output node to provide a bandgap voltage that is a weighted sum of the PTAT voltage and the CTAT voltage. The circuit includes a second resistor coupled between the output node and a first node, wherein the first node is coupled between the first resistor and the first current mirror. The circuit includes a third resistor coupled between the output node and a second node, wherein the second node is coupled between the BJT device and the second current mirror.

Abstract: The present disclosure provides a novel Lactobacillus helveticus UA881 strain and/or its probiotic composition, as well as their uses for improving intestinal permeability and metabolic disorders. These include lowering levels of triacylglyceride and cholesterol levels, improving leaky gut and metabolism disorders, degrading uric acid and purine nucleosides, relieving gout arthritis, activating antioxidant systems, and generating micro-nutrients. The novel Lactobacillus helveticus UA881 strain and/or its metabolites can be used to prepare medicaments, food products, health food, and external products for these purposes. The invention includes the Lactobacillus helveticus UA881 strain, deposited at the National Institute of Technology and Evaluation (NITE) under accession number NITE BP-03802.

Abstract: A memory structure comprises a dielectric layer, a first ferromagnetic bottom electrode, a second ferromagnetic bottom electrode, an SOT channel layer, and an MTJ structure. The dielectric layer is over the substrate. The first ferromagnetic bottom electrode extends through the dielectric layer. The second ferromagnetic bottom electrode extends through the dielectric layer, and is spaced apart from the first ferromagnetic bottom electrode. The SOT channel layer extends from the first ferromagnetic bottom electrode to the second ferromagnetic bottom electrode. The MTJ structure is over the SOT channel layer.

Abstract: The present disclosure provides a crack detection unit (CDU), a semiconductor die, and a method of detecting a crack of a semiconductor die. The CDU comprises a switching circuit, a crack sensor, and a logic circuit. The switching circuit is configured to enable the crack sensor. The crack sensor is configured to be electrically connected to the switching circuit, the ground, and an operating voltage. The logic circuit is configured to be electrically connected to the switching circuit and the crack sensor, wherein the CDU is enabled based on an input of the logic circuit. The output of the logic circuit indicates whether the crack sensor contains a crack.

Abstract: A memory device includes a first memory cell having a first polysilicon line associated with a first read word line and intersecting a first active region and a second active region, and a second polysilicon line and a first CPODE associated with a first program word line, the second polysilicon line intersecting the first active region and the first CPODE intersecting the second active region. The memory device also includes a second memory cell adjacent to the first memory cell, the second memory cell having a third polysilicon line associated with a second read word line and intersecting the first active region and the second active region, and a fourth polysilicon line and a second CPODE associated with a second program word line, the fourth polysilicon line intersecting the second active region and the second CPODE intersecting the first active region to form a cross-arrangement of CPODE.

Abstract: An anti-fuse array includes first through fourth adjacent anti-fuse bit columns, the anti-fuse bits of the first and second anti-fuse bit columns including portions of active areas of a first active area column, and the anti-fuse bits of the third and fourth anti-fuse bit columns including portions of active areas of a second active area column. Each row of a first set of conductive segment rows includes first and second conductive segments positioned between adjacent active areas of the first active area column and a third conductive segment positioned between adjacent active areas of the second active area column. Each row of a second set of conductive segments alternating with the first set of conductive segment rows includes a fourth conductive segment positioned between adjacent active areas of the first active area column and fifth and sixth conductive segments positioned between adjacent active areas of the second active area column.

Abstract: A method includes forming a memory stack over a substrate. A dielectric layer is deposited to cover the memory stack. An opening is formed in the dielectric layer. The opening does not expose the memory stack. A spin-orbit-torque (SOT) layer is formed in the opening. A free layer is formed over the dielectric layer to interconnect the memory stack and the SOT layer.

Abstract: A memory device comprises a source region, a drain region, a channel region, a gate dielectric layer, an MTJ stack, and a metal gate. The source region and the drain region are over a substrate. The channel region is between the source region and the drain region. The gate dielectric layer is over the channel region. The MTJ stack is over the gate dielectric layer. The MTJ stack comprises a first ferromagnetic layer, a second ferromagnetic layer with a switchable magnetization, and a tunnel barrier layer between the first and second ferromagnetic layers. The metal gate is over the MTJ stack.

Abstract: A circuit includes a voltage divider circuit configured to generate a feedback voltage according to an output voltage, an operational amplifier configured to output a driving signal according to the feedback voltage and a reference voltage and a pass gate circuit including multiple current paths. The current paths are controlled by the driving signal and connected in parallel between the voltage divider circuit and a power reference node.