Abstract: A method and a wash, clean and dry system are provided for washing, cleaning and drying a surface region of a human body. The system includes a toilet seat assembly with a bidet assembly having a spray canister device for spraying the surface region with a solution, such as a skin protecting barrier solution, a cleaning solution or a medicated solution. In one aspect, the spray canister device can be movably insert into and out of the toilet seat assembly and is easy to operate and use. In addition, the bidet assembly further includes a spray nozzle assembly and a drying nozzle assembly, which are adapted to wash, clean and dry the region of the human body in three dimensional moments. The removable spray canister device with the removable sleeved cover element is thus easy to carry and be re-filled with new solutions.

Abstract: An accelerator for neural network computing includes hardware engines and a buffer memory. The hardware engines include a convolution engine and at least a second engine. Each hardware engine includes circuitry to perform neural network operations. The buffer memory stores a first input tile and a second input tile of an input feature map. The second input tile overlaps with the first input tile in the buffer memory. The convolution engine is operative to retrieve the first input tile from the buffer memory, perform convolution operations on the first input tile to generate an intermediate tile of an intermediate feature map, and pass the intermediate tile to the second engine via the buffer memory.

Abstract: A memory device includes a first memory cell having a first polysilicon line associated with a first read word line and intersecting a first active region and a second active region, and a second polysilicon line and a first CPODE associated with a first program word line, the second polysilicon line intersecting the first active region and the first CPODE intersecting the second active region. The memory device also includes a second memory cell adjacent to the first memory cell, the second memory cell having a third polysilicon line associated with a second read word line and intersecting the first active region and the second active region, and a fourth polysilicon line and a second CPODE associated with a second program word line, the fourth polysilicon line intersecting the second active region and the second CPODE intersecting the first active region to form a cross-arrangement of CPODE.

Abstract: Embodiments of the disclosure relate to active cooling devices for cooling an electronic assembly positioned downstream in a computing system. In one embodiment, an electronic assembly positioned downstream of the computing system is disclosed. The electronic assembly includes a printed circuit board electrically connected to the computing system; an air duct disposed over the printed circuit board; and an active cooling device thermally coupled to the printed circuit board. The printed circuit board includes a transceiver socket configured to receive at least one optical transceiver and one or more heat-generating components disposed thereon. The at least one optical transceiver is configured to mate with an active optical cable.

Abstract: A method and system for generating a clock distribution circuit for each macro circuit in an ASIC design are disclosed herein. In some embodiments, a method for generating a clock distribution circuit receives the ASIC design specified in a hardware description language (HDL), places each macro circuit in allocated locations on a semiconductor substrate, generates a custom clock skew information for each macro circuit based on a macro clock delay model, generates a clock distribution circuit for each macro circuit placed on the semiconductor substrate based on the generated custom clock skew information, modifies the clock distribution circuit if the generated clock distribution circuit does not meet timing requirements of the ASIC design, and outputs a physical layout of the ASIC design for manufacturing under a semiconductor fabrication process.

Abstract: A depth detection apparatus includes: an emitting assembly for emitting a speckle light signal to a detection object, where the emitting assembly is configured to cause the speckle light signal to generate positive distortion; an imaging lens for imaging, to a photoelectric sensor, a depth light signal returned after the speckle light signal strikes the detection object, wherein the imaging lens is configured to cause the imaging of the depth light signal to generate negative distortion; and a photoelectric sensor for converting the depth light signal into an electrical signal, wherein a difference between an absolute value of a distortion amount of the negative distortion and an absolute value of a distortion amount of the positive distortion does not exceed 0.05, and the negative distortion and the positive distortion each are distortion having a distortion amount whose absolute value is greater than or equal to 0.03.

Abstract: A memory circuit includes a non-volatile memory cell, a sense amplifier coupled to the non-volatile memory cell, and configured to generate a first output signal, and a detection circuit coupled to the sense amplifier and the non-volatile memory cell. The detection circuit is configured to latch the first output signal and disrupt a current path between the non-volatile memory cell and the sense amplifier.

Abstract: A multi-fuse memory cell is disclosed. The circuit includes: a first fuse element electrically coupled to a first transistor, a gate of the first transistor is electrically coupled to a first selection signal; a second fuse element electrically coupled to a second transistor, a gate of the second transistor is electrically coupled to a second selection signal, both the first transistor and the second transistor are grounded; and a programming transistor electrically coupled to the first fuse element and the second fuse element, wherein a gate of the programming transistor is electrically coupled to a programming signal.

Abstract: A magnetoresistive memory device includes a plurality of bottom conductive lines, a plurality of top conductive lines, a first memory cell, and a second memory cell. The top conductive lines are over the bottom conductive lines. The first memory cell is between the bottom conductive lines and the top conductive lines and includes a first magnetic tunnel junction (MTJ) stack. The second memory cell is adjacent the first memory cell and between the bottom conductive lines and the top conductive lines. The second memory cell includes a second MTJ stack, and a top surface of the second MTJ stack is higher than a top surface of the first MTJ stack.

Abstract: A first clock signal is generated from a reference clock signal. A first frequency associated with the first clock signal is less than a reference clock frequency associated with the reference clock signal. The first clock signal is propagated towards a first component of an integrated circuit through a clock tree. A second clock signal having a second frequency is generated from the first clock signal at a terminal point of the clock tree. The second clock signal is provided to the first component.

Abstract: An electrostatic discharge (ESD) circuit includes: a cascade of NMOS transistors including a first NMOS transistor operatively cascaded to a second NMOS transistor wherein the cascade of NMOS transistors is operatively coupled to a first bus that receives an ESD pulse signal; a first single-gate-oxide ESD control circuit coupled to the first NMOS transistor and configured to turn on the first NMOS transistor during an ESD event, the first single-gate-oxide control circuit coupled between the first bus at a first voltage and a first node at a second voltage, wherein the first voltage is higher than the second voltage; a second single-gate-oxide control circuit operatively coupled to the second NMOS transistor and configured to turn on the second NMOS transistor during an ESD event and to turn off the second NMOS transistor during a normal operation, wherein the second single-gate-oxide control circuit is coupled between the first node at the second voltage and a second bus at a ground voltage, wherein the seco

Abstract: A method of making a semiconductor device includes operations directed toward electrically connecting a component to a first fuse, wherein the first fuse is on a first conductive level a first distance from the component; identifying a conductive element for omission between the first fuse and a second fuse; and electrically connecting the component to the second fuse, wherein the second fuse is on a second conductive level a second distance from the component, the second distance is greater than the first distance, and the electrically connecting the component to the second fuse comprises electrically connecting the component to the second fuse without forming the identified conductive element.

Abstract: A fusible structure includes a metal line with different portions having different thicknesses. Thinner portions of the metal line are designed to be destructively altered at lower voltages while thicker portions of the metal line are designed to be destructively altered at lower voltages. Furthermore, one or more dummy structures are disposed proximal to the thinner portions of the metal line. In some embodiments, dummy structures are placed with sufficient proximity so as to protect against metal sputtering when metal line is destructively altered.

Abstract: A layout method includes: forming a layout structure of a memory array having first and second rows, each including a plurality of storage cells, wherein at least one of the storage cells includes a fuse; disposing a word line between the first and second rows; disposing a plurality of control electrodes across the word line for connecting the storage cells of the first row and the storage cells of the second row respectively; disposing a first cut layer on a first control electrode of the control electrodes located on a first side of the word line; and disposing a second cut layer on a second control electrode of the control electrodes located on a second side of the word line; wherein the first side of the word line is opposite to the second side of the word line.

Abstract: A method of sidelink communications by a plurality of user equipment (UE) without the control of a base station in a wireless communication system is disclosed. In one embodiment, the UE being a scheduler end is configured to allocate the resources for initial/repeated transmissions and ACK/NACK messages, and also transmit information regarding the allocated resources to both the UEs being a transmitter end and a receiver end. In one embodiment, retransmission is performed when none of the scheduler and transmitter ends has received the ACK message sent by the receiver end, so as to minimize redundant retransmission in consideration of transmission reliability. In one embodiment, retransmission is performed when at least one of the scheduler and transmitters end has received the NACK message sent by the receiver end before the retransmission timer has reached to zero, so as to minimize transmission latency.

Abstract: A magnetoresistive memory device includes a memory stack, a spin-orbit-torque (SOT) layer, and a free layer. The memory stack includes a pinned layer, a spacer layer over the pinned layer, a reference layer over the spacer layer, and a tunnel barrier layer over the reference layer. The SOT layer has a top surface substantially coplanar with a top surface of the tunnel barrier layer of the memory stack. The free layer interconnects the SOT layer and the tunnel barrier layer.

Abstract: A device includes a dielectric layer, an interlayer metal pad in the dielectric layer, a first capacitor over the interlayer metal pad, and a second capacitor over the dielectric layer. The first capacitor includes a first bottom capacitor electrode over and in contact with the interlayer metal pad, a first top capacitor electrode, and a first inter-electrode dielectric layer between the first bottom capacitor electrode and the first top capacitor electrode. The second capacitor includes a second bottom capacitor electrode over and in contact with the dielectric layer, a second top capacitor electrode, and a second inter-electrode dielectric layer between the second bottom capacitor electrode and the second top capacitor electrode.

Abstract: A semiconductor device includes a component having a functionality. The semiconductor device further includes an interconnect structure electrically connected to the component. The interconnect structure is configured to electrically connect the component to a signal. The interconnect structure includes a first column of conductive elements and a second column of conductive elements. The interconnect structure further includes a first fuse on a first conductive level a first distance from the component, wherein the first fuse electrically connects the first column of conductive elements to the second column of conductive elements. The interconnect structure further includes a second fuse on a second conductive level a second distance from the component, wherein the second fuse electrically connects the first column of conductive elements to the second column of conductive elements, and the second distance is different from the first distance.

Abstract: A method and a wash, clean and dry system are provided for washing, cleaning and drying a surface region of a human body. The system includes a toilet seat assembly with a bidet assembly having a spray canister device for spraying the surface region with a solution, such as a skin protecting barrier solution, a cleaning solution or a medicated solution. In one aspect, the spray canister device can be movably insert into and out of the toilet seat assembly and is easy to operate and use. In addition, the bidet assembly further includes a spray nozzle assembly and a drying nozzle assembly, which are adapted to wash, clean and dry the region of the human body in three dimensional moments. The removable spray canister device with the removable sleeved cover element is thus easy to carry and be re-filled with new solutions.

Abstract: A layout method includes: forming a layout structure of a memory array having a first row, wherein the first row comprises a plurality of storage cells; disposing a word line; disposing a plurality of control electrodes for connecting the plurality of storage cells of the first row to the word line; and disposing a first cut layer on a first portion of a first control electrode of the plurality of control electrodes.