Abstract: An integrated circuit includes a semiconductor substrate and a plurality of circuit elements in or on the substrate. The circuit elements are defined by standard layout cells selected from a cell library. The circuit elements including a plurality of flip-flops. Each flip-flop has a data input terminal, a data output terminal, a clock input terminal, and a clock output terminal. A first one of the flip-flops directly abuts a second flip-flop such that the clock output terminal of the first flip-flop electrically connects with the clock input terminal of the second flip-flop.

Abstract: A method of making a semiconductor device includes operations directed toward electrically connecting a component to a first fuse, wherein the first fuse is on a first conductive level a first distance from the component; identifying a conductive element for omission between the first fuse and a second fuse; and electrically connecting the component to the second fuse, wherein the second fuse is on a second conductive level a second distance from the component, the second distance is greater than the first distance, and the electrically connecting the component to the second fuse comprises electrically connecting the component to the second fuse without forming the identified conductive element.

Abstract: A method of balancing workloads among processing elements (PEs) in a neural network processor can include receiving first weights and second weights of a neural network. The first and second weights are associated with a first and a second output channel (OC), respectively. A first PE computes a partial sum (PSUM) of an output activation of the first OC based on the non-zero weights in the first weights. A second PE computes a PSUM of an output activation of the second OC based on the non-zero weights in the second weights. A controller can allocate one or more non-zero weights of the first weights to the second PE for computing the PSUM of the output activation of the first OC to balance a workload.

Abstract: Memories are provided. A memory includes a first memory array, a second memory array and a read circuit. The first memory array is configured to store first data. The second memory array is configured to store second data that is complementary to the first data. The read circuit includes a decoding circuit, a sensing circuit and an output buffer. The decoding circuit is configured to provide a first signal according to the first data and a second signal according to the second data in response to an address signal. The sensing circuit is configured to provide a first sensing signal according to a reference signal and the first signal, and a second sensing signal according to the reference signal and the second signal. The output buffer is configured to provide the first sensing signal or the second sensing signal as an output according to a control signal.

Abstract: An instant hot water dispenser system includes a main body, having a water flow control valve seat, a water inlet and a water outlet, the water flow control valve seat being provided with a first flow control valve and a second flow control valve; a faucet being provided with a first pull member, a second pull member and a water outlet pipe; a first heating unit having a first water storage space and a heater; a second heating unit having a circulating water path and an instantaneous heater, the instantaneous heater being configured to instantaneously heat a water supply in the circulating water path to a predetermined temperature; a processing unit electrically connected to a control interface, the processing unit being further electrically connected to the water flow control valve seat, the first heating unit and the second heating unit.

Abstract: The invention provides a bias voltage to the component (such as the Faraday cup) for reducing the generation of particles, such as the implanted ions and/or the combination of the implanted ions and the material of the component, and preventing particles peeling away the component. The strength of the biased voltage should not significantly affect the implantation of ions into the wafer and should significantly prevent the emission of radiation and/or electrons away the biased component. How to provide and adjust the biased voltage is not limited, both the extra voltage source and the amended Pre-Amplifier are acceptable. Moreover, due to the electric field generated by the Faraday cup is modified by the biased voltage, the ion beam divergence close to the Faraday cup may be reduced such that the potential difference between the ion beam measured by the profiler and received by the Faraday cup may be minimized.

Abstract: An IoT system includes a computing module for controlling an integral function of the system and including an analysis unit and a machine learning unit. The analysis unit is capable of operational analysis and creating a predictive model and creating a predictive model according to the data analyzed. The machine learning unit has an algorithm function to create a corresponding learning model. An IoT module is electrically connected to the computing module to serve as an intermediate role. At least one detection unit is electrically connected to the IoT module and disposed in soil to detect data of environmental and soil conditions and sends the data detected to the computing module for subsequent analysis.

Abstract: A method and system for generating a clock distribution circuit for each macro circuit in an ASIC design are disclosed herein. In some embodiments, a method for generating a clock distribution circuit receives the ASIC design specified in a hardware description language (HDL), places each macro circuit in allocated locations on a semiconductor substrate, generates a custom clock skew information for each macro circuit based on a macro clock delay model, generates a clock distribution circuit for each macro circuit placed on the semiconductor substrate based on the generated custom clock skew information, modifies the clock distribution circuit if the generated clock distribution circuit does not meet timing requirements of the ASIC design, and outputs a physical layout of the ASIC design for manufacturing under a semiconductor fabrication process.

Abstract: A memory circuit includes a non-volatile memory cell, a sense amplifier coupled to the non-volatile memory cell, and configured to generate a first output signal, and a detection circuit coupled to the sense amplifier and the non-volatile memory cell. The detection circuit is configured to latch the first output signal and disrupt a current path between the non-volatile memory cell and the sense amplifier.

Abstract: A method of manufacturing an anti-fuse device includes forming an anti-fuse structure on a substrate, forming a first transistor at a first position away from the anti-fuse device in a first direction, and forming a second transistor at a second position away from the anti-fuse device in a second direction opposite the first direction. Forming the anti-fuse structure includes forming first and second S/D structures in an active area, the first transistor includes the first S/D structure, and the second transistor includes the second S/D structure. The method includes constructing a first electrical connection between gate structures of the first and second transistors and a second electrical connection between a third S/D structure of the first transistor and a fourth S/D structure of the second transistor.

Abstract: A memory device includes a spin-orbit-transfer (SOT) bottom electrode, an SOT ferromagnetic free layer, a first tunnel barrier layer, a spin-transfer-torque (STT) ferromagnetic free layer, a second tunnel barrier layer and a reference layer. The SOT ferromagnetic free layer is over the SOT bottom electrode. The SOT ferromagnetic free layer has a magnetic orientation switchable by the SOT bottom electrode using a spin Hall effect or Rashba effect. The first tunnel barrier layer is over the SOT ferromagnetic free layer. The STT ferromagnetic free layer is over the first tunnel barrier layer and has a magnetic orientation switchable using an STT effect. The second tunnel barrier layer is over the STT ferromagnetic free layer. The second tunnel barrier layer has a thickness different from a thickness of the first tunnel barrier layer. The reference layer is over the second tunnel barrier layer and has a fixed magnetic orientation.

Abstract: A circuit includes a voltage divider circuit configured to generate a feedback voltage according to an output voltage, an operational amplifier configured to output a driving signal according to the feedback voltage and a reference voltage and a pass gate circuit including multiple current paths. The current paths are controlled by the driving signal and connected in parallel between the voltage divider circuit and a power reference node.

Abstract: The present disclosure relates generally to ion implantation, and more particularly, to systems and processes for adjusting a ribbon beam angle of an ion implantation system. An exemplary ion implantation system includes an ion source configured to generate a ribbon beam, a wafer chuck configured to hold a wafer during implantation by the ribbon beam, a dipole magnet disposed between the ion source and the wafer chuck, and a controller. The dipole magnet includes at least two coils configured to adjust a ribbon beam angle of the ribbon beam at one or more locations along a path of the ribbon beam between the ion source and the wafer held in the wafer chuck. The controller is configured to control the ion source, the wafer chuck, and the dipole magnet.

Abstract: Embodiments of the disclosure relate to active cooling devices for cooling an electronic assembly positioned downstream in a computing system. In one embodiment, an electronic assembly positioned downstream of the computing system is disclosed. The electronic assembly includes a printed circuit board electrically connected to the computing system; an air duct disposed over the printed circuit board; and an active cooling device thermally coupled to the printed circuit board. The printed circuit board includes a transceiver socket configured to receive at least one optical transceiver and one or more heat-generating components disposed thereon. The at least one optical transceiver is configured to mate with an active optical cable.

Abstract: A spray canister device includes a canister element containing a sprayable solution and a sleeved cover element. The sleeved cover element includes a sleeve portion having a first end and a second end opposite the first end, a handle grip extending from the second end of the sleeve portion, a projection extending from the sleeve portion, the projection disposed on a side of the sleeve portion opposite from the handle grip, and a cap portion extending form the first end of the sleeve portion. The cap portion having a body portion, a cut-out portion including an opening configured to spray the solution, and a channel disposed within the body portion. The channel forming a conduit between an outlet of the canister device and the opening.

Abstract: A method (fabricating a fusible structure) includes forming a metal line that extends in a first direction, the forming a metal line including: configuring the mask such that the metal line has a first portion that is between a second portion and a third portion; and using an optical proximity correction technique with a mask so that the first portion has a first thickness that is thinner than a second thickness of each of the second portion and the third portion; and forming a first dummy structure proximal to the metal line and aligned with the first portion relative to the first direction.

Abstract: A closed-loop liquid cooling system includes a liquid coolant conduit, a cold plate, a pump and a heat exchanger. The liquid coolant conduit is in proximity to a heat-generating electrical component. The liquid coolant conduit allows circulation of a liquid coolant to extract heat therefrom. The liquid coolant conduit includes an inner portion that surrounds and contains the liquid coolant, and an outer portion configured to prevent or inhibit leakage of the liquid coolant from the inner portion and also detect any leakage from the inner portion. The cold plate is in thermal communication with the liquid coolant. The pump is configured to transport the liquid coolant in the liquid coolant conduit. The heat exchanger is coupled to the liquid coolant conduit to extract heat therefrom.

Abstract: A memory device includes a first memory cell having a first polysilicon line associated with a first read word line and intersecting a first active region and a second active region, and a second polysilicon line and a first CPODE associated with a first program word line, the second polysilicon line intersecting the first active region and the first CPODE intersecting the second active region. The memory device also includes a second memory cell adjacent to the first memory cell, the second memory cell having a third polysilicon line associated with a second read word line and intersecting the first active region and the second active region, and a fourth polysilicon line and a second CPODE associated with a second program word line, the fourth polysilicon line intersecting the second active region and the second CPODE intersecting the first active region to form a cross-arrangement of CPODE.

Abstract: A method includes forming bottom conductive lines over a wafer. A first magnetic tunnel junction (MTJ) stack is formed over the bottom conductive lines. Middle conductive lines are formed over the first MTJ stack. A second MTJ stack is formed over the middle conductive lines. Top conductive lines are formed over the second MTJ stack.

Abstract: A method and system for generating a clock distribution circuit for each macro circuit in an ASIC design are disclosed herein. In some embodiments, a method for generating a clock distribution circuit receives the ASIC design specified in a hardware description language (HDL), places each macro circuit in allocated locations on a semiconductor substrate, generates a custom clock skew information for each macro circuit based on a macro clock delay model, generates a clock distribution circuit for each macro circuit placed on the semiconductor substrate based on the generated custom clock skew information, modifies the clock distribution circuit if the generated clock distribution circuit does not meet timing requirements of the ASIC design, and outputs a physical layout of the ASIC design for manufacturing under a semiconductor fabrication process.