Abstract: In some embodiments, digital logic components, such as those found in standard cells in integrated circuit devices, are used to synthesize signals with controllable waveforms that result in transmitted signals that meet certain requirements, such as above-threshold high openings and below-threshold over/under-shooting. In some embodiments, driving buffers with logic controls and delay chains are used to achieve controllable slew rates at rising and falling edges to minimize over/under shooting behavior in signals. In some embodiments, control logic and delay chains produce controllable rising/falling “stair-type” edges to obtain optimized damping waveform.

Abstract: A memory structure comprises a dielectric layer, a first ferromagnetic bottom electrode, a second ferromagnetic bottom electrode, an SOT channel layer, and an MTJ structure. The dielectric layer is over the substrate. The first ferromagnetic bottom electrode extends through the dielectric layer. The second ferromagnetic bottom electrode extends through the dielectric layer, and is spaced apart from the first ferromagnetic bottom electrode. The SOT channel layer extends from the first ferromagnetic bottom electrode to the second ferromagnetic bottom electrode. The MTJ structure is over the SOT channel layer.

Abstract: A protection circuit applied in a hub chip including a power pin, a first data pin, and a second data pin is provided. A voltage generation circuit generates and adjusts output voltage according to the voltage of the power pin and the voltage of the first data pin. A PMOS transistor includes a first gate, a first electrode, a second electrode, and a first bulk. The first electrode is coupled to the power pin. The second electrode is coupled to the first data pin. The first bulk receives the output voltage. A detection circuit is coupled to the first gate and detects the voltage of the power pin. In response to the voltage of the power pin being equal to the first voltage, the detection circuit transmits the voltage of the first data pin to the first gate.

Abstract: A memory device includes a first memory cell having a first polysilicon line associated with a first read word line and intersecting a first active region and a second active region, and a second polysilicon line and a first CPODE associated with a first program word line, the second polysilicon line intersecting the first active region and the first CPODE intersecting the second active region. The memory device also includes a second memory cell adjacent to the first memory cell, the second memory cell having a third polysilicon line associated with a second read word line and intersecting the first active region and the second active region, and a fourth polysilicon line and a second CPODE associated with a second program word line, the fourth polysilicon line intersecting the second active region and the second CPODE intersecting the first active region to form a cross-arrangement of CPODE.

Abstract: Video messaging systems and methods utilize a video messaging component based on a video messaging component container stored in a data store. The video messaging component container includes a collaborative video list that shows a list of video content generated by users of the video messaging component. Iterations of the video messaging component are rendered in host applications on client devices. As video content is generated by the iterations, the collaborative video list is updated to include the video content, and the iterations of the video messaging component are updated to reflect changes to the collaborative video list in real-time.

Abstract: A closed-loop liquid cooling system includes a liquid coolant conduit, a cold plate, a pump and a heat exchanger. The liquid coolant conduit is in proximity to a heat-generating electrical component. The liquid coolant conduit allows circulation of a liquid coolant to extract heat therefrom. The liquid coolant conduit includes an inner portion that surrounds and contains the liquid coolant, and an outer portion configured to prevent or inhibit leakage of the liquid coolant from the inner portion and also detect any leakage from the inner portion. The cold plate is in thermal communication with the liquid coolant. The pump is configured to transport the liquid coolant in the liquid coolant conduit. The heat exchanger is coupled to the liquid coolant conduit to extract heat therefrom.

Abstract: For a manual gearshift control of conventional vehicle transmission, a vehicle gearshift automatic control device including a first actuator module, a second actuator module and an electronic control unit, is provided in an add-on manner to retrofit the vehicle transmission with both automatic and manual gearshift functions. In an automatic gearshift mode, the electronic control unit executes the vehicle gearshift automatic control method and receives an automatic gearshift command to drive the first actuator module to push a shift lever to implement a lateral shift selection, or to drive the second actuator module to spin a park lever to implement a longitudinal gearshift. For vehicle security, whenever a vehicle gearshift automatic control device failure or a manual gearshift intervention is detected in the automatic gearshift mode, the electronic control unit shuts off the automatic gearshift mode and switches to a manual gearshift mode to perform the manual gearshift function.

Abstract: The present disclosure provides a memory device, a semiconductor device, and a method of operating a memory device. A memory device includes a memory cell, a bit line, a word line, a select transistor, a fuse element, and a heater. The bit line is connected to the memory cell. The word line is connected to the memory cell. The select transistor is disposed in the memory cell. A gate of the select transistor is connected to the word line. The fuse element is disposed in the memory cell. The fuse element is connected to the bit line and the select transistor. The heater is configured to heat the fuse element.

Abstract: The present disclosure includes a voltage provision circuit. In one aspect of the present disclosure, a voltage provision circuit is disclosed. The voltage provision circuit includes a first NMOS transistor gated with a first control signal and sourced with a ground voltage. The voltage provision circuit includes a second NMOS transistor gated with a second control signal complementary to the first control signal and sourced with the ground voltage. The voltage provision circuit includes a first PMOS transistor sourced with a first supply voltage. The voltage provision circuit includes a second PMOS transistor sourced with the first supply voltage. The voltage provision circuit includes a voltage modulation circuit, coupled between the first to second PMOS transistors and the first to second NMOS transistors, that is configured to provide a first intermediate signal based on the first and second control signals.

Abstract: In some embodiments, digital logic components, such as those found in standard cells in integrated circuit devices, are used to synthesize signals with controllable waveforms that result in transmitted signals that meet certain requirements, such as above-threshold high openings and below-threshold over/under-shooting. In some embodiments, driving buffers with logic controls and delay chains are used to achieve controllable slew rates at rising and falling edges to minimize over/under shooting behavior in signals. In some embodiments, control logic and delay chains produce controllable rising/falling “stair-type” edges to obtain optimized damping waveform.

Abstract: A circuit includes a voltage divider circuit configured to generate a feedback voltage according to an output voltage, an operational amplifier configured to output a driving signal according to the feedback voltage and a reference voltage and a pass gate circuit including multiple current paths. The current paths are controlled by the driving signal and connected in parallel between the voltage divider circuit and a power reference node.

Abstract: An integrated circuit includes a semiconductor substrate and a plurality of circuit elements in or on the substrate. The circuit elements are defined by standard layout cells selected from a cell library. The circuit elements including a plurality of flip-flops. Each flip-flop has a data input terminal, a data output terminal, a clock input terminal, and a clock output terminal. A first one of the flip-flops directly abuts a second flip-flop such that the clock output terminal of the first flip-flop electrically connects with the clock input terminal of the second flip-flop.

Abstract: End effector tool changers for a robotic system are disclosed. The end effector tool changer is physically compact, mechanically robust, has high radial strength, prevents undesirable rotations, uses minimal sensory input, is suitable for a wide variety of tools, and operates quickly. The end effector tool changer includes a robotic arm attachment portion, including a first magnetic part and a plurality of first engagement parts, and a tool attachment portion, including a second magnetic part and a plurality of second engagement parts, where the plurality of first engagement parts is configured to engage with the plurality of second engagement parts, each of the plurality of first engagement parts and each of the plurality of second engagement parts are selected from the group consisting of a pin and a pin groove, and the first magnetic part spatially and magnetically corresponds to the second magnetic part.

Abstract: In some aspects of the present disclosure, a bandgap reference circuit includes a first current mirror and a first resistor coupled to the first current mirror to provide a proportional to absolute temperature (PTAT) voltage. The circuit includes a second current mirror and a bipolar junction transistor (BJT) device coupled to the second current mirror to provide a complementary to the absolute temperature (CTAT) voltage. The circuit includes an output node to provide a bandgap voltage that is a weighted sum of the PTAT voltage and the CTAT voltage. The circuit includes a second resistor coupled between the output node and a first node, wherein the first node is coupled between the first resistor and the first current mirror. The circuit includes a third resistor coupled between the output node and a second node, wherein the second node is coupled between the BJT device and the second current mirror.

Abstract: A memory circuit includes a non-volatile memory cell, a comparator and a detection circuit. The comparator is coupled to the non-volatile memory cell, and configured to generate a first output signal. The comparator including a first input terminal and a first output terminal. The first input terminal is coupled to the non-volatile memory cell by a first node, and configured to receive a first voltage. The first output terminal is configured to output the first output signal. The detection circuit is coupled to the comparator and the non-volatile memory cell. The detection circuit is configured to latch the first output signal and disrupt a current path between at least the non-volatile memory cell and the comparator. The detection circuit includes a first inverter coupled to the first output terminal of the comparator and configured to generate an inverted first output signal.

Abstract: A first clock signal is generated from a reference clock signal. A first frequency associated with the first clock signal is less than a reference clock frequency associated with the reference clock signal. The first clock signal is propagated towards a first component of an integrated circuit through a clock tree. A second clock signal having a second frequency is generated from the first clock signal at a terminal point of the clock tree. The second clock signal is provided to the first component.

Abstract: A multi-fuse memory cell is disclosed. The circuit includes: a first fuse element electrically coupled to a first transistor, a gate of the first transistor is electrically coupled to a first selection signal; a second fuse element electrically coupled to a second transistor, a gate of the second transistor is electrically coupled to a second selection signal, both the first transistor and the second transistor are grounded; and a programming transistor electrically coupled to the first fuse element and the second fuse element, wherein a gate of the programming transistor is electrically coupled to a programming signal.

Abstract: The present disclosure provides a memory device, a semiconductor device, and a method of operating a memory device. A memory device includes a memory cell, a bit line, a word line, a select transistor, a fuse element, and a heater. The bit line is connected to the memory cell. The word line is connected to the memory cell. The select transistor is disposed in the memory cell. A gate of the select transistor is connected to the word line. The fuse element is disposed in the memory cell. The fuse element is connected to the bit line and the select transistor. The heater is configured to heat the fuse element.

Abstract: An arbitrary-scale blind super resolution model has two designs. First, learn dual degradation representations where the implicit and explicit representations of degradation are sequentially extracted from the input low resolution image. Second, process both upsampling and downsampling at the same time, where the implicit and explicit degradation representations are utilized respectively, in order to enable cycle-consistency and train the arbitrary-scale blind super resolution model.

Abstract: A method for generating a high resolution image from a low resolution image includes retrieving a plurality of low resolution image patches from the low resolution image, performing discrete wavelet transform on each low resolution image patch to generate a first image patch with a high frequency on a horizontal axis and a high frequency on a vertical axis, a second image patch with a high frequency on the horizontal axis and a low frequency on the vertical axis, and a third image patch with a low frequency on the horizontal axis and a high frequency on the vertical axis, inputting the three image patches to a dual branch degradation extractor to generate a blur representation and a noise representation, and performing contrastive learning on the blur representation and the noise representation by reducing a blur loss and a noise loss.