Patents by Inventor Shawna M. Liff

Shawna M. Liff has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20200235061
    Abstract: Microelectronic assemblies, and related devices and methods, are disclosed herein. For example, in some embodiments, a microelectronic assembly may a die having a front side and a back side, the die comprising a first material and conductive contacts at the front side; and a thermal layer attached to the back side of the die, the thermal layer comprising a second material and a conductive pathway, wherein the conductive pathway extends from a front side of the thermal layer to a back side of the thermal layer.
    Type: Application
    Filed: December 29, 2017
    Publication date: July 23, 2020
    Applicant: Intel Corporation
    Inventors: Adel A. Elsherbini, Patrick Morrow, Henning Braunisch, Kimin Jun, Brennen Mueller, Shawna M. Liff, Johanna M. Swan, Paul B. Fischer
  • Publication number: 20200235082
    Abstract: A device package and a method of forming the device package are described. The device package includes one or more dies disposed on a first substrate. The device packages further includes one or more interconnects vertically disposed on the first substrate, and a mold layer disposed over and around the first die, the one or more interconnects, and the first substrate. The device package has a second die disposed on a second substrate, wherein the first substrate is electrically coupled to the second substrate with the one or more interconnects, and wherein the one or more interconnects are directly disposed on at least one of a top surface of the first substrate and a bottom surface of the second substrate without an adhesive layer. The device package may include one or more interconnects having one or more different thicknesses or heights at different locations on the first substrate.
    Type: Application
    Filed: September 30, 2017
    Publication date: July 23, 2020
    Inventors: Feras EID, Johanna M. SWAN, Shawna M. LIFF
  • Patent number: 10721568
    Abstract: Embodiments of the invention include an acoustic transducer device having a base structure that is positioned in proximity to a cavity of an organic substrate, a piezoelectric material in contact with a first electrode of the base structure, and a second electrode in contact with the piezoelectric material. In one example, for a transmit mode, a voltage signal is applied between the first and second electrodes and this causes a stress in the piezoelectric material which causes a stack that is formed with the first electrode, the piezoelectric material, and the second electrode to vibrate and hence the base structure to vibrate and generate acoustic waves.
    Type: Grant
    Filed: July 1, 2016
    Date of Patent: July 21, 2020
    Assignee: Intel Corporation
    Inventors: Georgios C. Dogiamis, Feras Eid, Adel A. Elsherbini, Johanna Swan, Shawna M. Liff, Thomas L. Sounart, Sasha N. Oster
  • Publication number: 20200227401
    Abstract: Microelectronic assemblies, and related devices and methods, are disclosed herein. For example, in some embodiments, a microelectronic assembly may include a package substrate having a first surface and an opposing second surface, and a die secured to the package substrate, wherein the die has a first surface and an opposing second surface, the die has first conductive contacts at the first surface and second conductive contacts at the second surface, and the first conductive contacts are coupled to conductive pathways in the package substrate by first non-solder interconnects.
    Type: Application
    Filed: December 29, 2017
    Publication date: July 16, 2020
    Applicant: Intel Corporation
    Inventors: Adel A. Elsherbini, Shawna M. Liff, Johanna M. Swan, Arun Chandrasekhar
  • Publication number: 20200227377
    Abstract: Microelectronic assemblies, and related devices and methods, are disclosed herein. For example, in some embodiments, a microelectronic assembly may include a package substrate having a first surface and an opposing second surface, and a die secured to the package substrate, wherein the die has a first surface and an opposing second surface, the die has first conductive contacts at the first surface and second conductive contacts at the second surface, and the first conductive contacts are coupled to conductive pathways in the package substrate by first non-solder interconnects.
    Type: Application
    Filed: December 29, 2017
    Publication date: July 16, 2020
    Applicant: Intel Corporation
    Inventors: Shawna M. Liff, Adel A. Elsherbini, Johanna M. Swan, Arun Chandrasekhar
  • Publication number: 20200227384
    Abstract: Microelectronic assemblies, and related devices and methods, are disclosed herein. For example, in some embodiments, a microelectronic assembly may include a package substrate having a first surface and an opposing second surface, and a die secured to the package substrate, wherein the die has a first surface and an opposing second surface, the die has first conductive contacts at the first surface and second conductive contacts at the second surface, and the first conductive contacts are coupled to conductive pathways in the package substrate by first non-solder interconnects.
    Type: Application
    Filed: December 29, 2017
    Publication date: July 16, 2020
    Applicant: Intel Corporation
    Inventors: Shawna M. Liff, Adel A. Elsherbini, Johanna M. Swan
  • Publication number: 20200219815
    Abstract: Microelectronic assemblies, and related devices and methods, are disclosed herein. For example, in some embodiments, a microelectronic assembly may include a package substrate, a first die coupled to the package substrate with first interconnects, and a second die coupled to the first die with second interconnects, wherein the second die is coupled to the package substrate with third interconnects, a communication network is at least partially included in the first die and at least partially included in the second die, and the communication network includes a communication pathway between the first die and the second die.
    Type: Application
    Filed: December 29, 2017
    Publication date: July 9, 2020
    Applicant: Intel Corporation
    Inventors: Adel A. Elsherbini, Amr Elshazly, Arun Chandrasekhar, Shawna M. Liff, Johanna M. Swan
  • Patent number: 10707171
    Abstract: Embodiments of the invention include molded modules and methods for forming molded modules. According to an embodiment the molded modules may be integrated into an electrical package. Electrical packages according to embodiments of the invention may include a die with a redistribution layer formed on at least one surface. The molded module may be mounted to the die. According to an embodiment, the molded module may include a mold layer and a plurality of components encapsulated within the mold layer. Terminals from each of the components may be substantially coplanar with a surface of the mold layer in order to allow the terminals to be electrically coupled to the redistribution layer on the die. Additional embodiments of the invention may include one or more through mold vias formed in the mold layer to provide power delivery and/or one or more faraday cages around components.
    Type: Grant
    Filed: December 22, 2015
    Date of Patent: July 7, 2020
    Assignee: Intel Corporation
    Inventors: Tomita Yoshihiro, Eric J. Li, Shawna M. Liff, Javier A. Falcon, Joshua D. Heppner
  • Publication number: 20200212012
    Abstract: A device package has substrates disposed on top of one another to form a stack, and pads formed on at least one of the top surface and the bottom surface of each of the substrates. The device package has interconnects electrically coupling at least one of the top surface and the bottom surface of each substrate to at least one of the top surface and the bottom surface of another substrate. The device package has pillars disposed between at least one of the top surface and the bottom surface of one or more substrates to at least one of the top surface and the bottom surface of other substrates. The device package also has adhesive layers formed between at least one of the top surface and the bottom surface of one or more substrates to at least one of the top surface and the bottom surface of other substrates.
    Type: Application
    Filed: September 30, 2017
    Publication date: July 2, 2020
    Inventors: Preston T. MEYERS, Javier A. FALCON, Shawna M. LIFF, Joe R. SAUCEDO, Adel A. ELSHERBINI, Albert S. LOPEZ, Johanna M. SWAN
  • Patent number: 10658566
    Abstract: Embodiments of the invention include piezoelectrically driven switches that are used for modifying a background color or light source color in display systems, and methods of forming such devices. In an embodiment, a piezoelectrically actuated switch for modulating a background color in a display may include a photonic crystal that has a plurality of blinds oriented substantially perpendicular to a surface of the display. In an embodiment, the blinds include a black surface and a white surface. The switch may also include an anchor spaced away from an edge of the photonic crystal and a piezoelectric actuator formed on the surface of the anchor and a surface of the photonic crystal. Some embodiments may include a photonic crystal that is a multi-layer polymeric structure or a polymer chain with a plurality of nanoparticles spaced at regular intervals on the polymer chain.
    Type: Grant
    Filed: April 1, 2016
    Date of Patent: May 19, 2020
    Assignee: Intel Corporation
    Inventors: Shawna M. Liff, Feras Eid, Aleksandar Aleksov, Sasha N. Oster, Baris Bicen, Thomas L. Sounart, Johanna M. Swan, Adel A. Elsherbini, Valluri R. Rao
  • Patent number: 10649158
    Abstract: Embodiments of the invention include an optoelectronic package that allows for in situ alignment of optical fibers. In an embodiment, the optoelectronic package may include an organic substrate. Embodiments include a cavity formed into the organic substrate. Additionally, the optoelectronic package may include an actuator formed on the organic substrate that extends over the cavity. In one embodiment, the actuator may include a first electrode, a piezoelectric layer formed on the first electrode, and a second electrode formed on the piezoelectric layer. According to an additional embodiment of the invention, the actuator may include a first portion and a second portion. In order to allow for resistive heating and actuation driven by thermal expansion, a cross-sectional area of the first portion of the beam may be greater than a cross-sectional area of the second portion of the beam.
    Type: Grant
    Filed: July 1, 2016
    Date of Patent: May 12, 2020
    Assignee: Intel Corporation
    Inventors: Johanna M. Swan, Aleksandar Aleksov, Sasha N. Oster, Feras Eid, Baris Bicen, Thomas L. Sounart, Shawna M. Liff, Valluri R. Rao
  • Patent number: 10644616
    Abstract: Embodiments of the invention include a self-propelled sensor system. In an embodiment, the self-propelled sensor system includes a piezoelectrically actuated motor that is integrated with a substrate. In an embodiment, the self-propelled sensor system may also include a sensor and an integrated circuit electrically coupled to the piezoelectrically actuated motor. Embodiments of the invention may also include self-propelled sensor systems that include plurality of piezoelectrically actuated motors. In an embodiment the piezoelectrically actuated motors may be one or more different types of motors including, but not limited to, stick and slip motors, inchworm stepping motors, standing acoustic wave motors, a plurality of piezoelectrically actuated cantilevers, and a piezoelectrically actuated diaphragm. Additional embodiments of the invention may include a plurality of self-propelled sensor systems that are communicatively coupled to form a sensor mesh.
    Type: Grant
    Filed: September 30, 2016
    Date of Patent: May 5, 2020
    Assignee: Intel Corporation
    Inventors: Shawna M. Liff, Georgios C. Dogiamis, Sasha N. Oster, Feras Eid, Adel A. Elsherbini, Thomas L. Sounart, Johanna M. Swan
  • Patent number: 10636716
    Abstract: Examples of an electronic package include a package assembly. The package assembly can include a substrate having a first substrate surface that includes a conductive layer attached to the first substrate surface. The package assembly includes a die communicatively coupled to the conductive layer and a contact block that includes a first contact surface on one end of the contact block, a second contact surface on an opposing side of the contact block, and a contact block wall extended therebetween. The contact block can include a conductive material. The first contact surface can be coupled to the package assembly with a joint extended partially up the contact block wall. The electronic package can further include an overmold covering portions of the substrate, conductive layer, and die. The second contact surface of the contact block can be exposed through the overmold.
    Type: Grant
    Filed: May 30, 2018
    Date of Patent: April 28, 2020
    Assignee: Intel Corporation
    Inventors: Sasha Oster, Srikant Nekkanty, Joshua D. Heppner, Adel A. Elsherbini, Yoshihiro Tomita, Debendra Mallik, Shawna M. Liff, Yoko Sekihara
  • Patent number: 10634566
    Abstract: Embodiments of the invention include a temperature sensing device that includes a base structure that is positioned in proximity to a cavity of an organic substrate, an input transducer coupled to the base structure, and an output transducer coupled to the base structure. The input transducer includes a first piezoelectric material to generate vibrations which are transmitted on the base structure in response to input signals being applied to the input transducer. The output transducer includes a second piezoelectric material to receive the vibrations and to generate output signals which are used to determine a change in ambient temperature.
    Type: Grant
    Filed: June 30, 2016
    Date of Patent: April 28, 2020
    Assignee: Intel Corporation
    Inventors: Feras Eid, Sasha N. Oster, Georgios C. Dogiamis, Thomas L. Sounart, Adel A. Elsherbini, Shawna M. Liff, Johanna M. Swan
  • Patent number: 10629557
    Abstract: A system for packaging integrated circuits includes an integrated circuit having one or more integrated circuit terminals. The system for packaging integrated circuits also includes a substrate having one or more substrate terminals. The system for packaging integrated circuits further includes an electrically conductive adhesive in communication with the integrated circuit terminals and the substrate terminals. The electrically conductive adhesive establishes an electrical connection between each of the one or more integrated circuit terminals and the one or more substrate terminals. The electrical connection between each of the one or more integrated circuit terminals and the one or more substrate terminals are enclosed in a dielectric. The system for packaging integrated circuits includes a second adhesive in communication with the integrated circuit and the substrate, wherein the second adhesive couples the integrated circuit and substrate together.
    Type: Grant
    Filed: December 30, 2016
    Date of Patent: April 21, 2020
    Inventors: Veronica A Strong, Sasha N. Oster, Shawna M. Liff
  • Publication number: 20200105653
    Abstract: Microelectronic assemblies, related devices and methods, are disclosed herein. In some embodiments, a microelectronic assembly may include a package substrate having a surface; a die having a first surface and an opposing second surface; and a chiplet having a first surface and an opposing second surface, wherein the chiplet is between the surface of the package substrate and the first surface of the die, wherein the first surface of the chiplet is coupled to the surface of the package substrate and the second surface of the chiplet is coupled to the first surface of the die, and wherein the chiplet includes: a capacitor at the first surface; and an element at the second surface, wherein the element includes a switching transistor or a diode.
    Type: Application
    Filed: September 27, 2018
    Publication date: April 2, 2020
    Applicant: Intel Corporation
    Inventors: Adel A. Elsherbini, Kaladhar Radhakrishnan, Krishna Bharath, Shawna M. Liff, Johanna M. Swan
  • Publication number: 20200105701
    Abstract: An electronic package and method includes a substrate including a plurality of pads on a major surface. An electronic component including a plurality of pads on a major surface facing the major surface of the substrate. A stud bump electrically couples one of the plurality of pads of the substrate to one of the plurality of pads of the electronic component.
    Type: Application
    Filed: September 28, 2018
    Publication date: April 2, 2020
    Inventors: Zhaozhi Li, Sanka Ganesan, Debendra Mallik, Gregory Perry, Kuan H. Lu, Omkar Karhade, Shawna M. Liff
  • Publication number: 20200098621
    Abstract: Microelectronic assemblies, related devices and methods, are disclosed herein. In some embodiments, a microelectronic assembly may include a first die having a first surface and an opposing second surface, wherein the first die is in a first dielectric layer; a magnetic core inductor, having a first surface and an opposing second surface, in the first dielectric layer, wherein the magnetic core inductor may include a first conductive pillar at least partially surrounded by a magnetic material, and a second conductive pillar coupled to the first conductive pillar; and a second die having a first surface and an opposing second surface, wherein the second die is in a second dielectric layer, and wherein the first surface of the second die is coupled to the second surface of the magnetic core inductor.
    Type: Application
    Filed: September 24, 2018
    Publication date: March 26, 2020
    Applicant: Intel Corporation
    Inventors: Krishna Bharath, Adel A. Elsherbini, Shawna M. Liff, Kaladhar Radhakrishnan, Zhiguo Qian, Johanna M. Swan
  • Publication number: 20200098724
    Abstract: Embodiments herein may relate to a semiconductor package or a semiconductor package structure. The package or package structure may include an interposer with a memory coupled to one side and a processing unit coupled to the other side. A third chip may be coupled with the interposer adjacent to the processing unit. Other embodiments may be described and/or claimed.
    Type: Application
    Filed: September 26, 2018
    Publication date: March 26, 2020
    Applicant: Intel Corporation
    Inventors: Shawna M. Liff, Adel A. Elsherbini, Johanna M. Swan, Gerald S. Pasdast
  • Publication number: 20200098676
    Abstract: Microelectronic assemblies, related devices and methods, are disclosed herein. In some embodiments, a microelectronic assembly may include a die, having an active surface and an opposing backside surface, including a plurality of through silicon vias (TSVs); and an inductor including a first conductive pillar with a first end and an opposing second end, wherein the first end of the first conductive pillar is coupled to the backside surface of a first individual TSV; a second conductive pillar with a first end and an opposing second end, wherein the first end of the second conductive pillar is coupled to the backside surface of a second individual TSV, wherein the second end of the second conductive pillar is coupled to the second end of the first conductive pillar, and wherein the first and the second conductive pillars are at least partially surrounded in a magnetic material.
    Type: Application
    Filed: September 24, 2018
    Publication date: March 26, 2020
    Applicant: Intel Corporation
    Inventors: Adel A. Elsherbini, Krishna Bharath, Shawna M. Liff, Johanna M. Swan