Abstract: An apparatus comprises a waveguide including: an elongate waveguide core including a dielectric material, wherein the waveguide core includes at least one space arranged lengthwise along the waveguide core that is void of the dielectric material; and a conductive layer arranged around the waveguide core.

Abstract: A method of making a waveguide, comprises: extruding a first dielectric material as a waveguide core of the waveguide, wherein the waveguide core is elongate; and coextruding an outer layer with the waveguide core, wherein the outer layer is arranged around the waveguide core.

Abstract: Embodiments of the invention include a display formed on an organic substrate and methods of forming such a device. According to an embodiment, an array of pixel mirrors may be formed on the organic substrate. For example, each of the pixel mirrors is actuatable about one or more axes out of the plane of the organic substrate. Additionally, embodiments of the invention may include an array of routing mirrors formed on the organic substrate. According to an embodiment, each of the routing mirrors is actuatable about two axes out of the plane of the organic substrate. In embodiments of the invention, a light source may be used for emitting light towards the array of routing mirrors. For example, light emitted from the light source may be reflected to one or more of the pixel mirrors by one of the routing mirrors.

Abstract: An embedded silicon bridge system including tall interconnect via pillars is part of a system in package device. The tall via pillars may span a Z-height distance to a subsequent bond pad from a bond pad that is part of an organic substrate that houses the embedded silicon bridge.

Abstract: Microelectronic assemblies, and related devices and methods, are disclosed herein. For example, in some embodiments, a microelectronic assembly may include a package substrate having a first surface and an opposing second surface, and a die secured to the package substrate, wherein the die has a first surface and an opposing second surface, the die has first conductive contacts at the first surface and second conductive contacts at the second surface, and the first conductive contacts are coupled to conductive pathways in the package substrate by first non-solder interconnects.

Abstract: Microelectronic assemblies, and related devices and methods, are disclosed herein. For example, in some embodiments, a microelectronic assembly may include a package substrate having a first surface and an opposing second surface, and a die secured to the package substrate, wherein the die has a first surface and an opposing second surface, the die has first conductive contacts at the first surface and second conductive contacts at the second surface, and the first conductive contacts are coupled to conductive pathways in the package substrate by first non-solder interconnects.

Abstract: Microelectronic assemblies, and related devices and methods, are disclosed herein. For example, in some embodiments, a microelectronic assembly may include a package substrate, a first die coupled to the package substrate with first interconnects, and a second die coupled to the first die with second interconnects, wherein the second die is coupled to the package substrate with third interconnects, a communication network is at least partially included in the first die and at least partially included in the second die, and the communication network includes a communication pathway between the first die and the second die.

Abstract: Microelectronic assemblies, related devices and methods, are disclosed herein. In some embodiments, a microelectronic assembly may include a package substrate having a first surface and an opposing second surface; a first die having a first surface and an opposing second surface embedded in a first dielectric layer, where the first surface of the first die is coupled to the second surface of the package substrate by first interconnects; a second die having a first surface and an opposing second surface embedded in a second dielectric layer, where the first surface of the second die is coupled to the second surface of the first die by second interconnects; and a third die having a first surface and an opposing second surface embedded in a third dielectric layer, where the first surface of the third die is coupled to the second surface of the second die by third interconnects.

Abstract: Microelectronic assemblies, and related devices and methods, are disclosed herein. For example, in some embodiments, a microelectronic assembly may include a package substrate having a first surface and an opposing second surface, and a die secured to the package substrate, wherein the die has a first surface and an opposing second surface, the die has first conductive contacts at the first surface and second conductive contacts at the second surface, and the first conductive contacts are coupled to conductive pathways in the package substrate by first non-solder interconnects.

Abstract: Microelectronic assemblies, and related devices and methods, are disclosed herein. For example, in some embodiments, a microelectronic assembly may include a package substrate, a first die coupled to the package substrate with first interconnects, and a second die coupled to the first die with second interconnects, wherein the second die is coupled to the package substrate with third interconnects, a communication network is at least partially included in the first die and at least partially included in the second die, and the communication network includes a communication pathway between the first die and the second die.

Abstract: Various embodiments disclosed relate to a semiconductor package. The present semiconductor package includes a substrate. The substrate is formed from alternating conducting layers and dielectric layers. A first active electronic component is disposed on an external surface of the substrate, and a second active electronic component is at least partially embedded within the substrate. A first interconnect region is formed from a plurality of interconnects between the first active electronic component and the second active electronic component. Between the first active electronic component and the substrate a second interconnect region is formed from a plurality of interconnects. Additionally, a third interconnect region is formed from a plurality of interconnects between the second active electronic component and the substrate.

Abstract: Disclosed herein are maskless imaging tools and display systems that include piezoelectrically actuated mirrors and methods of forming such devices. The maskless imaging tool may include a light source. Additionally, the tool may include one or more piezoelectrically actuated mirrors for receiving light from the light source. The piezoelectrically actuated mirrors are actuatable about one or more axes to reflect the light from the light source to a workpiece positioned to receive light from the piezoelectrically actuated mirror. Disclosed herein is a maskless imaging tool that is a laser direct imaging lithography (LDIL) tool. The maskless imaging tool may also be a via-drill tool. Disclosed herein is also a piezoelectrically actuated mirror used in a projection system. For example, the projection system may be integrated into a pair of glasses.

Abstract: Embodiments of the invention include a piezo-electric mirror in an microelectronic package and methods of forming the package. According to an embodiment the microelectronic package may include an organic substrate with a cavity formed in the organic substrate. In some embodiments, an actuator is anchored to the organic substrate and extends over the cavity. For example, the actuator may include a first electrode and a piezo-electric layer formed on the first electrode. A second electrode may be formed on the piezo-electric layer. Additionally, a mirror may be formed on the actuator. Embodiments allow for the piezo-electric layer to be formed on an organic package substrate by using low temperature crystallization processes. For example, the piezo-electric layer may be deposited in an amorphous state. Thereafter, a laser annealing process that includes a pulsed laser may be used to crystallize the piezo-electric layer.

Abstract: An apparatus comprises a waveguide section including an outer layer of conductive material tubular in shape and having multiple ends; and a joining feature on at least one of the ends of the waveguide section configured for joining to a second separate waveguide section.

Abstract: Semiconductor packages that mitigate warpage and/or other types or mechanical deformation of package substrates are provided. In some embodiments, a package substrate can include a peripheral conductive region having an assembly of rigid conductive members, such as metal layers, metal interconnects, or a combination thereof. The peripheral conductive region can be integrated into the package substrate during the manufacturing of the package substrate. In some implementations, lithographically defined conductive members can be leveraged to form extended conductive layers that can provide increased stiffness compared to nearly cylindrical conductive vias. Non-peripheral conductive regions also can be integrated into a semiconductor package in order to reduce specific patterns of mechanical deformations and/or to provide other functionality, such as electromagnetic interference (EMI) shielding.

Abstract: Embodiments of the invention include a current sensing device for sensing current in an organic substrate. The current sensing device includes a released base structure that is positioned in proximity to a cavity of the organic substrate and a piezoelectric film stack that is positioned in proximity to the released base structure. The piezoelectric film stack includes a piezoelectric material in contact with first and second electrodes. A magnetic field is applied to the current sensing device and this causes movement of the released base structure and the piezoelectric stack which induces a voltage (potential difference) between the first and second electrodes.

Abstract: A microelectronic structure includes a microelectronic substrate having a first surface and a cavity extending into the substrate from the microelectronic substrate first surface, a first microelectronic device and a second microelectronic device attached to the microelectronic substrate first surface, and a microelectronic bridge disposed within the microelectronic substrate cavity and attached to the first microelectronic device and to the second microelectronic device. In one embodiment, the microelectronic structure may include a reconstituted wafer formed from the first microelectronic device and the second microelectronic device. In another embodiment, a flux material may extend between the first microelectronic device and the microelectronic bridge and between the second microelectronic device and the microelectronic bridge.

Abstract: Embodiments are generally directed to a package architecture for antenna arrays. An embodiment of an apparatus includes an electronic package, the electronic package including one or more routing layers; a transmitter to drive a signal for wireless transmission; and an assembled phased array antenna to transmit the signal, the assembled phased array antenna including a plurality of separate antenna elements in an array, each antenna element of the array being individually attached to a first side of the electronic package. The antenna elements include a first antenna element and a second antenna element, wherein the first antenna element is separated from the second antenna element by a gap.

Abstract: An optoelectronic apparatus is presented. In embodiments, the apparatus may include a package including a substrate with a first side and a second side opposite the first side, wherein the first side comprises a ball grid array (BGA) field. The apparatus may further include one or more integrated circuits (ICs) disposed on the first side of the substrate, inside the BGA field, that thermally interface with a printed circuit board (PCB), to which the package is to be coupled, one or more optical ICs coupled to the second side and communicatively coupled with the one or more ICs via interconnects provided in the substrate, wherein at least one of the optical ICs is at least partially covered by an integrated heat spreader (IHS), to provide dissipation of heat produced by the at least one optical IC.

Abstract: Quantum computing assemblies, and related devices and methods, are disclosed herein. For example, in some embodiments, a quantum computing assembly may include: a package substrate; a first die coupled to the package substrate; and a second die coupled to the second surface of the package substrate and coupled to the first die; wherein the first die or the second die includes quantum processing circuitry.