Abstract: Semiconductor devices are provided. A semiconductor device includes a power switch, a first power mesh and a second power mesh. The power switch has a first terminal and a second terminal. The first power mesh is directly connected to the first terminal of the power switch. The second power mesh is directly connected to the second terminal of the power switch. The first power mesh includes a first power rail over the power switch and extending in a first direction. The second power mesh includes a second power rail under the power switch and extending in the first direction. The first and second power rails are separated from each other.

Abstract: A method of forming an integrated circuit device includes forming first segments extending in a first direction in a first conductive layer; forming second segments extending in the first direction in the first conductive layer, the forming the first and second segments including: interspersing the first and second segments relative to a second direction perpendicular to the first direction such that: the first segments are symmetrically spaced apart relative to each other, the second segments are symmetrically spaced apart relative to each other, and ones of the second segments are substantially asymmetrically spaced between corresponding adjacent ones of the first segments.

Abstract: A computerized method of transforming an interactive graphical user interface according to machine learning includes generating a user interface element corresponding to a persona. In response to user interaction with the user interface element, data structures related to the persona are extracted from a first data store. The data structures are transformed into a set of input variables. The method includes generating a first output variable based on the set of input variables. A second output variable based on the first input variable is generated by: generating a set of intermediate output variables, determining a first intermediate output variable of the set of intermediate output variables, and determining a second intermediate output variable based on a machine learning model corresponding to the first intermediate output variable. In response to the second output variable exceeding a first threshold, the graphical user interface displays a first message.

Abstract: A conductive line structure includes: first and second offset sets of long pillars that are substantially coaxial on an intra-set basis; a third set of offset short pillars, the short pillars being: overlapping of long pillars in the first and second sets; and organized into groups of first quantities of the short pillars; each of the groups being overlapping of and electrically coupled between a pair of one of the long pillars in the first set and a one of the long pillars in the second set such that, in each of the groups, each short pillar being overlapping of and electrically coupled between the pair; and each long pillar in each of the first and second sets being overlapped by a second quantity of short pillars in the third set and being electrically coupled to same; and the first quantity being less than the second quantity.

Abstract: A chip package is provided. The chip package includes a device substrate, a first redistribution layer (RDL), a carrier base, and at least one conductive connection structure. The device substrate has at least one first through-via opening extending from the backside surface of the device substrate to the active surface of the device substrate. The first RDL is disposed on the backside surface of the device substrate and extends in the first through-via opening. The carrier base carries the device substrate, and has a first surface facing the backside surface of the device substrate and a second surface opposite the first surface. The conductive connection structure is disposed on the second surface of the carrier base and is electrically connected to the first RDL.

Abstract: An electrically and thermally conductive gasket includes a resilient core including a plurality of sides, a heat spreader disposed along at least two sides of the plurality of sides of the resilient core, and an electrically conductive layer disposed along and/or covering at least a portion of the heat spreader, such that the portion of the heat spreader is between the resilient core and the electrically conductive layer. The gasket is positionable and/or compressible between first and second surfaces to thereby define an electrically conductive path and a thermally conductive path between the first and second surfaces.

Abstract: An electrically and thermally conductive gasket includes a resilient core including a plurality of sides, a heat spreader disposed along at least two sides of the plurality of sides of the resilient core, and an electrically conductive layer disposed along and/or covering at least a portion of the heat spreader, such that the portion of the heat spreader is between the resilient core and the electrically conductive layer. The gasket is positionable and/or compressible between first and second surfaces to thereby define an electrically conductive path and a thermally conductive path between the first and second surfaces.

Abstract: A method of forming a semiconductor arrangement includes forming a first capacitor in a first voltage domain and forming a second capacitor in the first voltage domain. The first capacitor is connected in parallel with the second capacitor. A third capacitor and a fourth capacitor are formed in a second voltage domain. The third capacitor is connected in series with the fourth capacitor. The first capacitor and the second capacitor are connected in parallel with a supply terminal of the first voltage domain and a reference terminal of the first voltage domain. The fourth capacitor is connected to a supply terminal of the second voltage domain. The third capacitor is connected to a reference terminal of the second voltage domain.

Abstract: A device includes a power grid (PG) arrangement including: first and second segments in a first conductive layer which are conductive and extend in a first direction, the first segments being configured for a first reference voltage and the second segments being configured for a second reference voltage; the first and second segments being interspersed relative to a second direction, the second direction being perpendicular to the first direction; and relative to the second direction, the first segments being symmetrically spaced apart relative to each other, the second segments being symmetrically spaced apart relative to each other, and the second segments being substantially asymmetrically spaced between corresponding adjacent ones of the first segments.

Abstract: Semiconductor devices are provided. A semiconductor device includes a semiconductor substrate, a power switch, a first power mesh and a second power mesh. The power switch is formed over the front surface of the semiconductor substrate. The first power mesh is formed over the power switch and is directly connected to the first terminal of the power switch. The second power mesh is formed over the back surface of the semiconductor substrate and is directly connected to the second terminal of the power switch.

Abstract: The present invention provides a GPIO driver including a control logic, a level shifter module and a post-driver. The control logic supplied by a first supply voltage is configured to receive an input signal to generate a first signal. The level shifter module is configured to receive the first signal to generate a second signal. The post-driver supplied by a second supply voltage is configured to receive the second signal to generate an output signal. When the first supply voltage is lower than the second supply voltage, the level shifter module performs a level-boosting operation to increase a voltage level of the first signal to generate the second signal; and when the first supply voltage is greater than the second supply voltage, the level shifter module operates as a buffer, and the voltage level of the second signal is the same as the voltage level of the first signal.

Abstract: A method of forming a semiconductor arrangement includes forming a first capacitor in a first voltage domain and forming a second capacitor in the first voltage domain. The first capacitor is connected in parallel with the second capacitor. A third capacitor and a fourth capacitor are formed in a second voltage domain. The third capacitor is connected in series with the fourth capacitor. The first capacitor and the second capacitor are connected in parallel with a supply terminal of the first voltage domain and a reference terminal of the first voltage domain. The fourth capacitor is connected to a supply terminal of the second voltage domain. The third capacitor is connected to a reference terminal of the second voltage domain.

Abstract: Various layouts for conductive interconnects in the conductor layers in an integrated circuit are disclosed. Some or all of the conductive interconnects are included in a power delivery system. In general, the conductive interconnects in a first conductor layer are arranged according to an orthogonal layout and the conductive interconnects in a second conductor layer are arranged according to a non-orthogonal layout. Conductive stripes in a transition conductor layer positioned between the first and the second conductor layers electrically connect the conductive interconnects in the first conductor layer to the conductive interconnects in the second conductor layer.

Abstract: An interface device includes a dynamic tracking bias circuit, an ESD (Electrostatic Discharge) clamp circuit, a pre-driver, a post-driver, and an I/O (Input/Output) pad. The dynamic tracking bias circuit provides a first supply voltage. The first supply voltage is determined according to a main power voltage and a second supply voltage. The ESD clamp circuit limits the second supply voltage. The post-driver is driven by the pre-driver. The I/O pad is driven by the post-driver. The pre-driver and the post-driver are supplied by the main power voltage, the first supply voltage, and the second supply voltage.

Abstract: A solar energy storage and generation system includes a housing mounted on a base, a solar collector installed inside the housing, at least one lens installed on the upper surface of the housing, and multiple liquid-level counterbalance devices installed separately at different corner positions inside the housing. The base includes a multi-axis adjustment device positioned corresponding to the center of gravity of the counterweights in the housing. By installing the liquid-level counterbalance devices inside the housing and the multi-axis adjustment device, the upper surface of the housing can be adjusted to face the direction of the sun, thereby achieving a sun-tracking effect.

Abstract: Various layouts for conductive interconnects in the conductor layers in an integrated circuit are disclosed. Some or all of the conductive interconnects are included in a power delivery system. In general, the conductive interconnects in a first conductor layer are arranged according to an orthogonal layout and the conductive interconnects in a second conductor layer are arranged according to a non-orthogonal layout. Conductive stripes in a transition conductor layer positioned between the first and the second conductor layers electrically connect the conductive interconnects in the first conductor layer to the conductive interconnects in the second conductor layer.

Abstract: A plug-in holder includes a frame, a first engaging structure and at least one second engaging structure. The frame has a first side and a second side, wherein the first side is opposite to the second side. The first engaging structure is located at the first side. The at least one second engaging structure is located at the second side.

Abstract: In a method, cell placement is performed to place a plurality of cells into a region of an integrated circuit (IC). A thermal analysis is performed to determine whether the region of the IC is thermally stable at an operating condition. In response to a determination that the region of the IC is thermally unstable, at least one of a structure or the operating condition of the region of the IC is changed. After the thermal analysis, routing is performed to route a plurality of nets interconnecting the placed cells. At least one of the cell placement, the thermal analysis, the changing or the routing is executed by a processor.

Abstract: A solar energy collector includes a body, wherein the body has a geometric shape with a hollow interior. The body has multiple openings arranged at intervals around a Y-axis to allow a light ray to enter, and the openings are distributed along a Z-axis at different height positions. This arrangement reduces light exposure and disperses most of the thermal energy to be absorbed within the body. The light ray enters the interior of the body after being concentrated and reflected by a light path mechanism. Once inside the collector body, the light ray will be continuously reflected until it is absorbed, maximizing the utilization rate of the light ray.

Abstract: This application provides an integrated power generation system with thermal energy and pressure storage cycles comprising a heat and pressure storage unit connected to a heat source, the heat source absorbs and transmits thermal energy to the unit to heat and pressurize a first working substance and convert it to a gaseous state; a first power generation device receives the high-temperature and high-pressure first working substance released from the unit and converts the fluid kinetic energy of the first working substance into electrical energy; a heat storage tank receives the first working substance flowing through the first power generation device for heat exchange and storage of thermal energy; and a cooling tank receives the first working substance from the heat storage tank to enable the first working substance and undergoes a phase change into a liquid state and then transmits it to the unit to complete a cycle.