Patents by Inventor Shen Lin
Shen Lin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11985238Abstract: Embodiments disclose a vehicle-mounted device upgrade method and a related device. The method may be applied to an intelligent vehicle, the intelligent vehicle includes a vehicle-mounted control device, and the method may include: receiving, by the vehicle-mounted control device, a first partial key sent by the communications device; restoring, by the vehicle-mounted control device, a first key by using the first partial key and a second partial key that is stored on the vehicle-mounted control device; and performing, by the vehicle-mounted control device, secure processing on a first upgrade file by using the first key, to obtain the securely processed first upgrade file, where the secure processing includes generating first message authentication code (MAC), and the securely processed first upgrade file includes the first upgrade file and the first MAC. According to this application, the vehicle-mounted device can be securely and efficiently upgraded.Type: GrantFiled: October 30, 2020Date of Patent: May 14, 2024Assignee: Huawei International Pte. Ltd.Inventors: Yanjiang Yang, Zhuo Wei, Hsiao-Ying Lin, He Wei, Junqiang Shen
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Patent number: 11984378Abstract: A semiconductor package structure includes an interposer substrate formed over a package substrate. The structure also includes a die disposed over the interposer substrate. The structure also includes a first heat spreader disposed over the package substrate. The structure also includes a second heat spreader disposed over the die and connected to the first heat spreader. The coefficient of thermal expansion (CTE) of the first heat spreader and the coefficient of thermal expansion of the second heat spreader are different.Type: GrantFiled: May 13, 2021Date of Patent: May 14, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Shu-Shen Yeh, Po-Yao Lin, Chin-Hua Wang, Yu-Sheng Lin, Shin-Puu Jeng
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Publication number: 20240153842Abstract: A semiconductor structure includes a die embedded in a molding material, the die having die connectors on a first side; a first redistribution structure at the first side of the die, the first redistribution structure being electrically coupled to the die through the die connectors; a second redistribution structure at a second side of the die opposing the first side; and a thermally conductive material in the second redistribution structure, the die being interposed between the thermally conductive material and the first redistribution structure, the thermally conductive material extending through the second redistribution structure, and the thermally conductive material being electrically isolated.Type: ApplicationFiled: January 4, 2024Publication date: May 9, 2024Inventors: Hao-Jan Pei, Wei-Yu Chen, Chia-Shen Cheng, Chih-Chiang Tsao, Cheng-Ting Chen, Chia-Lun Chang, Chih-Wei Lin, Hsiu-Jen Lin, Ching-Hua Hsieh, Chung-Shi Liu
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Publication number: 20240153839Abstract: A semiconductor package structure includes an interposer substrate formed over a package substrate. The structure also includes a die disposed over the interposer substrate. The structure also includes a first heat spreader disposed over the package substrate. The structure also includes a second heat spreader disposed over the die and connected to the first heat spreader. The coefficient of thermal expansion (CTE) of the first heat spreader and the coefficient of thermal expansion of the second heat spreader are different.Type: ApplicationFiled: January 12, 2024Publication date: May 9, 2024Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Shu-Shen YEH, Po-Yao LIN, Chin-Hua WANG, Yu-Sheng LIN, Shin-Puu JENG
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Publication number: 20240155843Abstract: A semiconductor device includes a substrate having a flash memory region and a logic device region, a logic transistor disposed in the logic device region, and a flash memory transistor disposed in the flash memory region. The flash memory transistor includes a metal select gate having two opposite sidewalls and two memory gates disposed on the two opposite sidewalls of the metal select gate.Type: ApplicationFiled: November 28, 2022Publication date: May 9, 2024Applicant: UNITED MICROELECTRONICS CORP.Inventors: Wang Xiang, CHIA CHING HSU, Shen-De Wang, Yung-Lin Tseng, WEICHANG LIU
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Patent number: 11978722Abstract: A package structure and a formation method of a package structure are provided. The method includes disposing a chip structure over a substrate. The chip structure has an inclined sidewall, the inclined sidewall is at an acute angle to a vertical, the vertical is a direction perpendicular to a main surface of the chip structure, and the acute angle is in a range from about 12 degrees to about 45 degrees. The method also includes forming a protective layer to surround the chip structure.Type: GrantFiled: August 27, 2021Date of Patent: May 7, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Shu-Shen Yeh, Po-Chen Lai, Che-Chia Yang, Li-Ling Liao, Po-Yao Lin, Shin-Puu Jeng
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Patent number: 11973001Abstract: Semiconductor devices and methods of manufacture which utilize lids in order to constrain thermal expansion during annealing are presented. In some embodiments lids are placed and attached on encapsulant and, in some embodiments, over first semiconductor dies. As such, when heat is applied, and the encapsulant attempts to expand, the lid will work to constrain the expansion, reducing the amount of stress that would otherwise accumulate within the encapsulant.Type: GrantFiled: May 5, 2023Date of Patent: April 30, 2024Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Shu-Shen Yeh, Chin-Hua Wang, Chia-Kuei Hsu, Po-Yao Lin, Shin-Puu Jeng
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Patent number: 11972956Abstract: A lid attach process includes dipping a periphery of a lid in a dipping tank of adhesive material such that the adhesive material attaches to the periphery of the lid. The lid attach process further includes positioning the lid over a die attached to a substrate using a lid carrier, wherein the periphery of the lid is aligned with a periphery of the lid carrier. The lid attach process further includes attaching the lid to the substrate with the adhesive material forming an interface with the substrate. The lid attach process further includes contacting a thermal interface material (TIM) on the die with the lid.Type: GrantFiled: May 22, 2020Date of Patent: April 30, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Chin-Liang Chen, Wei-Ting Lin, Yu-Chih Liu, Kuan-Lin Ho, Jason Shen
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Publication number: 20240136246Abstract: A semiconductor device includes a package structure, a first heat spreader, and a second heat spreader. The first heat spreader is aside the package structure. The second heat spreader is in physical contact with the first heat spreader. The second heat spreader covers a top surface and sidewalls of the package structure. A material of the first heat spreader is different from a material of the second heat spreader.Type: ApplicationFiled: January 3, 2024Publication date: April 25, 2024Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Shu-Shen Yeh, Po-Yao Lin, Yu-Sheng Lin, Po-Chen Lai, Shin-Puu Jeng
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Publication number: 20240138272Abstract: Various embodiments of the present disclosure are directed towards an integrated chip including a first conductive structure over a substrate. A data storage structure overlies the first conductive structure. The data storage structure comprises a first dielectric layer on the first conductive structure and a second dielectric layer on the first dielectric layer. The first dielectric layer comprises a dielectric material and a first dopant having a concentration that changes from a top surface of the first dielectric layer in a direction towards the first conductive structure. A second conductive structure overlies the data storage structure.Type: ApplicationFiled: January 3, 2024Publication date: April 25, 2024Inventors: Fa-Shen Jiang, Cheng-Yuan Tsai, Hai-Dang Trinh, Hsing-Lien Lin, Hsun-Chung Kuang, Bi-Shen Lee
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Patent number: 11967582Abstract: A multi-chip device includes a first material within a substrate. The first material has a first coefficient of thermal expansion different than a second coefficient of thermal expansion of the substrate. A first chip overlies a first portion of the first material and a first portion of the substrate. A second chip overlies a second portion of the first material and a second portion of the substrate. The first material is between the first portion of the substrate and the second portion of the substrate.Type: GrantFiled: April 24, 2023Date of Patent: April 23, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LIMITEDInventors: Chin-Hua Wang, Po-Chen Lai, Shu-Shen Yeh, Tsung-Yen Lee, Po-Yao Lin, Shin-Puu Jeng
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Patent number: 11967547Abstract: Some embodiments relate to a semiconductor structure. The semiconductor structure includes a first substrate including a first plurality of conductive pads that are laterally spaced apart from one another on the first substrate. A first plurality of conductive bumps are disposed on the first plurality of conductive pads, respectively. A multi-tiered solder-resist structure is disposed on the first substrate and arranged between the first plurality of conductive pads. The multi-tiered solder-resist structure has different widths at a different heights over the first substrate and contacts sidewalls of the first plurality of conductive bumps to separate the first plurality of conductive bumps from one another.Type: GrantFiled: August 26, 2021Date of Patent: April 23, 2024Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chin-Hua Wang, Shu-Shen Yeh, Po-Chen Lai, Po-Yao Lin, Shin-Puu Jeng
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Publication number: 20240128398Abstract: An epitaxial structure includes a first epitaxial layer, a second epitaxial layer, and an interface treatment layer. The second epitaxial layer is disposed on the first epitaxial layer. The interface treatment layer is located between the first epitaxial layer and the second epitaxial layer and is in contact with the first epitaxial layer and the second epitaxial layer. The first epitaxial layer, the second epitaxial layer, and the interface treatment layer include the same material. An image contrast ratio of a transmission electron microscope (TEM) of the interface treatment layer to the first epitaxial layer and an image contrast ratio of a TEM of the interface treatment layer to the second epitaxial layer are both greater than 1.005. A method for forming an epitaxial structure is also provided.Type: ApplicationFiled: November 25, 2022Publication date: April 18, 2024Applicant: PlayNitride Display Co., Ltd.Inventors: Hsin-Chiao Fang, Shen-Jie Wang, Yen-Lin Lai
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Publication number: 20240128397Abstract: An epitaxial structure including a first epitaxial layer, a second epitaxial layer, and an interface treatment layer is provided. The first epitaxial layer is an ohmic contact layer. The second epitaxial layer is disposed on the first epitaxial layer and is a phosphide compound layer, where a material of the second epitaxial layer is different from a material of the first epitaxial layer. The interface treatment layer contacts the first epitaxial layer and the second epitaxial layer and is located between the first epitaxial layer and the second epitaxial layer. An image contrast ratio of a transmission electron microscope (TEM) of the interface treatment layer to the first epitaxial layer and an image contrast ratio of the TEM of the interface treatment layer to the second epitaxial layer are both greater than 1.005. A method for forming an epitaxial structure is also provided.Type: ApplicationFiled: November 18, 2022Publication date: April 18, 2024Applicant: PlayNitride Display Co., Ltd.Inventors: Hsin-Chiao Fang, Shen-Jie Wang, Yen-Lin Lai
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Patent number: 11963468Abstract: In some embodiments, the present disclosure relates to an integrated chip. The integrated chip includes a bottom electrode disposed over one or more interconnects and a diffusion barrier layer on the bottom electrode. The diffusion barrier layer has an inner upper surface that is arranged laterally between and vertically below an outer upper surface of the diffusion barrier film. The outer upper surface wraps around the inner upper surface in a top-view of the diffusion barrier layer. A data storage structure is separated from the bottom electrode by the diffusion barrier layer. A top electrode is arranged over the data storage structure.Type: GrantFiled: July 27, 2022Date of Patent: April 16, 2024Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Hai-Dang Trinh, Chii-Ming Wu, Hsing-Lien Lin, Fa-Shen Jiang
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Publication number: 20240120294Abstract: A chip package includes a substrate, a semiconductor chip, and a thermal conductive structure. The chip package includes a first and a second support structures below the thermal conductive structure. The first and the second support structures connect the substrate and corners of the thermal conductive structure. The thermal conductive structure has a side edge connecting the first and the second support structures. The first and the second support structures and the side edge together define of an opening exposing a space surrounding the semiconductor chip. The first and the second support structures are disposed along a side of the substrate. The first support structure is laterally separated from the side of the substrate by a first lateral distance. The side edge of the thermal conductive structure is laterally separated from the side of the substrate by a second lateral distance different than the first lateral distance.Type: ApplicationFiled: December 21, 2023Publication date: April 11, 2024Inventors: Shu-Shen YEH, Chin-Hua WANG, Kuang-Chun LEE, Po-Yao LIN, Shyue-Ter LEU, Shin-Puu JENG
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Publication number: 20240122078Abstract: A semiconductor memory device includes a substrate having a conductor region thereon, an interlayer dielectric layer on the substrate, and a conductive via electrically connected to the conductor region. The conductive via has a lower portion embedded in the interlayer dielectric layer and an upper portion protruding from a top surface of the interlayer dielectric layer. The upper portion has a rounded top surface. A storage structure conformally covers the rounded top surface.Type: ApplicationFiled: December 18, 2023Publication date: April 11, 2024Applicant: UNITED MICROELECTRONICS CORP.Inventors: Chia-Chang Hsu, Tang-Chun Weng, Cheng-Yi Lin, Yung-Shen Chen, Chia-Hung Lin
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Publication number: 20240115738Abstract: Provided herein are methods for treatment of cystic fibrosis (CF), including for patients with class I CFTR mutations. The methods may involve administration of a recombinant adeno-associated virus (rAAV) that includes an AV.TL65 capsid protein and a polynucleotide that includes an F5 enhancer and a tg83 promoter operably linked to a CFTR?R minigene, or a pharmaceutical composition thereof.Type: ApplicationFiled: April 15, 2022Publication date: April 11, 2024Inventors: Mark SMITH, Katherine EXCOFFON, Shen LIN, Madhupriya MAHANKALI, Eric YUEN, Roland KOLBECK, Matthew GLATFELTER
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Patent number: 11956919Abstract: A cold plate is provided and includes: a housing disposed with a chamber; a base combined with the housing to form a working space separated from the chamber but connected with the chamber through an interconnecting structure to allow a working medium to flow within the chamber and the working space; a heat transfer structure disposed on the inner side of the base; and a pump disposed within the working space to drive the working medium in the working space. As such, the cold plate can provide better heat dissipation performance.Type: GrantFiled: December 23, 2020Date of Patent: April 9, 2024Assignee: AURAS TECHNOLOGY CO., LTD.Inventors: Chien-An Chen, Chien-Yu Chen, Tian-Li Ye, Jen-Hao Lin, Wei-Shen Lee
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Patent number: 11955455Abstract: A method includes bonding a first package component over a second package component. The second package component includes a plurality of dielectric layers, and a plurality of redistribution lines in the plurality of dielectric layers. The method further includes dispensing a stress absorber on the second package component, curing the stress absorber, and forming an encapsulant on the second package component and the stress absorber.Type: GrantFiled: July 25, 2022Date of Patent: April 9, 2024Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Shin-Puu Jeng, Chien-Sheng Chen, Po-Yao Lin, Po-Chen Lai, Shu-Shen Yeh