Patents by Inventor Shen Lin

Shen Lin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 12093625
    Abstract: In a method, cell placement is performed to place a plurality of cells into a region of an integrated circuit (IC). A thermal analysis is performed to determine whether the region of the IC is thermally stable at an operating condition. In response to a determination that the region of the IC is thermally unstable, at least one of a structure or the operating condition of the region of the IC is changed. After the thermal analysis, routing is performed to route a plurality of nets interconnecting the placed cells. At least one of the cell placement, the thermal analysis, the changing or the routing is executed by a processor.
    Type: Grant
    Filed: April 30, 2021
    Date of Patent: September 17, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Wan-Yu Lo, Kuo-Nan Yang, Chin-Shen Lin, Chung-Hsing Wang
  • Patent number: 12096584
    Abstract: A plug-in holder includes a frame, a first engaging structure and at least one second engaging structure. The frame has a first side and a second side, wherein the first side is opposite to the second side. The first engaging structure is located at the first side. The at least one second engaging structure is located at the second side.
    Type: Grant
    Filed: April 10, 2022
    Date of Patent: September 17, 2024
    Assignee: Wistron Corporation
    Inventor: Chih-Shen Lin
  • Publication number: 20240295344
    Abstract: A solar energy collector includes a body, wherein the body has a geometric shape with a hollow interior. The body has multiple openings arranged at intervals around a Y-axis to allow a light ray to enter, and the openings are distributed along a Z-axis at different height positions. This arrangement reduces light exposure and disperses most of the thermal energy to be absorbed within the body. The light ray enters the interior of the body after being concentrated and reflected by a light path mechanism. Once inside the collector body, the light ray will be continuously reflected until it is absorbed, maximizing the utilization rate of the light ray.
    Type: Application
    Filed: October 13, 2022
    Publication date: September 5, 2024
    Inventor: CHIH-SHEN LIN
  • Publication number: 20240263621
    Abstract: This application provides an integrated power generation system with thermal energy and pressure storage cycles comprising a heat and pressure storage unit connected to a heat source, the heat source absorbs and transmits thermal energy to the unit to heat and pressurize a first working substance and convert it to a gaseous state; a first power generation device receives the high-temperature and high-pressure first working substance released from the unit and converts the fluid kinetic energy of the first working substance into electrical energy; a heat storage tank receives the first working substance flowing through the first power generation device for heat exchange and storage of thermal energy; and a cooling tank receives the first working substance from the heat storage tank to enable the first working substance and undergoes a phase change into a liquid state and then transmits it to the unit to complete a cycle.
    Type: Application
    Filed: June 10, 2022
    Publication date: August 8, 2024
    Inventor: Chih-Shen LIN
  • Publication number: 20240258200
    Abstract: A semiconductor devices includes a substrate, a power grid structure, and a through via penetrating the substrate. The power grid structure includes: first and second rails extending along a first direction, a conductive wire, a third rail, a conductive via, and a connecting member. The conductive wire is between the first and second rails, and extends along the first direction. The third rail is below the first rail, the second rail and the conductive wire, and extends along a second direction perpendicular to the first direction. The conductive via is between and electrically couples the conductive wire to the third rail. The connecting member is between and electrically couples the first rail to the conductive wire. The through via extends through the substrate and along a third direction perpendicular to the first direction and the second direction. The through via is disposed on and coupled to the conductive wire.
    Type: Application
    Filed: May 30, 2023
    Publication date: August 1, 2024
    Inventors: Chin-Shen LIN, Ren-Zheng LIAO, Hao-Tien KAN, Yung-Fong LU
  • Publication number: 20240234321
    Abstract: A conductive line structure includes: first and second offset sets of long pillars that are substantially coaxial on an intra-set basis; a third set of offset short pillars, the short pillars being: overlapping of long pillars in the first and second sets; and organized into groups of first quantities of the short pillars; each of the groups being overlapping of and electrically coupled between a pair of one of the long pillars in the first set and a one of the long pillars in the second set such that, in each of the groups, each short pillar being overlapping of and electrically coupled between the pair; and each long pillar in each of the first and second sets being overlapped by a second quantity of short pillars in the third set and being electrically coupled to same; and the first quantity being less than the second quantity.
    Type: Application
    Filed: February 1, 2024
    Publication date: July 11, 2024
    Inventors: Hiranmay BISWAS, Chi-Yeh YU, Kuo-Nan YANG, Chung-Hsing WANG, Stefan RUSU, Chin-Shen LIN
  • Publication number: 20240115738
    Abstract: Provided herein are methods for treatment of cystic fibrosis (CF), including for patients with class I CFTR mutations. The methods may involve administration of a recombinant adeno-associated virus (rAAV) that includes an AV.TL65 capsid protein and a polynucleotide that includes an F5 enhancer and a tg83 promoter operably linked to a CFTR?R minigene, or a pharmaceutical composition thereof.
    Type: Application
    Filed: April 15, 2022
    Publication date: April 11, 2024
    Inventors: Mark SMITH, Katherine EXCOFFON, Shen LIN, Madhupriya MAHANKALI, Eric YUEN, Roland KOLBECK, Matthew GLATFELTER
  • Patent number: 11950771
    Abstract: The present invention provides a supporting hook structure, comprising a sleeve, a fixing rod, a first limit unit, a hook and a fixing device. The fixing rod is connected to the side surface of the sleeve. The hook body is connected to one end of the sleeve. The first limit unit is arranged on the side surface of the sleeve and adjacent to the hook body. The first limit unit makes the hook body rotates with the axis direction of the sleeve as a rotation axis. The fixing device is connected to the other end of the sleeve to fix the rotating position of the hook body. Through the above, the hook part enters the proximal thigh from a surgical entrance and the hook part rotates to make the hook part abut against the proximal femur to complete the positioning and fixation of the femur hook structure to the femur.
    Type: Grant
    Filed: August 16, 2021
    Date of Patent: April 9, 2024
    Assignee: UNITED ORTHOPEDIC CORPORATION
    Inventors: Yan-Shen Lin, Jiann-Jong Liau, Yu-Liang Liu, Teh-Yang Lin, Wen-Chuan Chen
  • Patent number: 11943939
    Abstract: An integrated circuit (IC) device includes a substrate and a circuit region over the substrate. The circuit region includes at least one active region extending along a first direction, at least one gate region extending across the at least one active region and along a second direction transverse to the first direction, and at least one first input/output (IO) pattern configured to electrically couple the circuit region to external circuitry outside the circuit region. The at least one first IO pattern extends along a third direction oblique to both the first direction and the second direction.
    Type: Grant
    Filed: January 4, 2021
    Date of Patent: March 26, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Meng-Kai Hsu, Jerry Chang Jui Kao, Chin-Shen Lin, Ming-Tao Yu, Tzu-Ying Lin, Chung-Hsing Wang
  • Patent number: 11935833
    Abstract: A method of forming an IC structure includes forming first and second power rails at a power rail level. First metal segments are formed at a first metal level above the power rail level. Each first metal segment of the plurality of first metal segments overlap one or both of the first power rail or the second power rail. First vias are formed between the power rail level and the first metal level. Second metal segments are formed at a second metal level above the first metal level. At least one second metal segment of the plurality of second metal segments overlaps the first power rail. At least one second metal segment of the plurality of second metal segments overlaps the second power rail. A plurality of second vias are formed between the first metal level and the second metal level.
    Type: Grant
    Filed: December 8, 2021
    Date of Patent: March 19, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Hiranmay Biswas, Chi-Yeh Yu, Kuo-Nan Yang, Chung-Hsing Wang, Stefan Rusu, Chin-Shen Lin
  • Publication number: 20240086209
    Abstract: A computerized method of transforming an interactive graphical user interface according to machine learning includes generating a user interface element corresponding to a persona. In response to user interaction with the user interface element, data structures related to the persona are extracted from a first data store. The data structures are transformed into a set of input variables. The method includes generating a first output variable based on the set of input variables. A second output variable based on the first input variable is generated by: generating a set of intermediate output variables, determining a first intermediate output variable of the set of intermediate output variables, and determining a second intermediate output variable based on a machine learning model corresponding to the first intermediate output variable. In response to the second output variable exceeding a first threshold, the graphical user interface displays a first message.
    Type: Application
    Filed: November 9, 2023
    Publication date: March 14, 2024
    Inventor: Yu Shen Lin
  • Patent number: 11929331
    Abstract: The present disclosure provides a routing structure. The routing structure includes a substrate having a boundary and a first conductive trace configured to be coupled to a first conductive pad disposed within the boundary of the substrate. The first conductive trace is inclined with respect to the boundary of the substrate.
    Type: Grant
    Filed: December 19, 2022
    Date of Patent: March 12, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Chin-Shen Lin, Wan-Yu Lo, Meng-Xiang Lee, Hao-Tien Kan, Kuo-Nan Yang, Chung-Hsing Wang
  • Publication number: 20240012658
    Abstract: A computerized method of transforming an interactive graphical user interface according to machine learning includes generating a selectable user interface element corresponding to a persona. In response to a user selecting the user interface element, data structures related to the persona are extracted from a first data store. The data structures are transformed into a set of input variables at a data processing module and loaded at a model execution module. The model execution module generates a first output variable based on the set of input variables. An analysis module generates a second output variable based on the first input variable. The graphical user interface displays a first message, a second message, or a third message in response to conditions being met for the second output variable.
    Type: Application
    Filed: July 7, 2022
    Publication date: January 11, 2024
    Inventor: Yu Shen Lin
  • Publication number: 20230420369
    Abstract: An integrated circuit (IC) device includes a substrate with a power control circuit, front and back side metal layers, and first and second feed through vias (FTVs). The front side metal layer has first and second front side power rails. The back side metal layer has first and second back side power rails. The first FTV extends through the substrate, and couples the first front side power rail to the first back side power rail. The second FTV extends through the substrate, and couples the second front side power rail to the second back side power rail. The power control circuit is coupled to the first and second front side power rails, and is controllable to electrically connect the first front side power rail to the second front side power rail, or electrically disconnect the first front side power rail from the second front side power rail.
    Type: Application
    Filed: September 2, 2022
    Publication date: December 28, 2023
    Inventors: Chin-Shen LIN, Luk LU, Hao-Tien KAN, Ren-Zheng LIAO
  • Publication number: 20230404831
    Abstract: A femoral lift apparatus includes a lift device and a hook device. The hook device is coupled to the lift device. The femoral lift apparatus is labor-saving and can avoid the problem that the conventional femoral lift apparatus may block the surgical view, hinder the operation position for a hip joint replacement surgery. With the assistance of this current femoral lift apparatus, the hip joint replacement surgery can be performed more smoothly.
    Type: Application
    Filed: September 26, 2022
    Publication date: December 21, 2023
    Inventors: EDWIN P SU, Yan-Shen Lin, Jiann-Jong Liau, Yu-Liang Liu, Teh-Yang Lin, Wen-Chuan Chen
  • Patent number: 11847473
    Abstract: A computerized method of transforming an interactive graphical user interface according to machine learning includes generating a selectable user interface element corresponding to a persona. In response to a user selecting the user interface element, data structures related to the persona are extracted from a first data store. The data structures are transformed into a set of input variables at a data processing module and loaded at a model execution module. The model execution module generates a first output variable based on the set of input variables. An analysis module generates a second output variable based on the first input variable. The graphical user interface displays a first message, a second message, or a third message in response to conditions being met for the second output variable.
    Type: Grant
    Filed: July 7, 2022
    Date of Patent: December 19, 2023
    Assignee: Evernorth Strategic Development, Inc.
    Inventor: Yu Shen Lin
  • Publication number: 20230403868
    Abstract: A method includes forming a circuit region over a substrate. The circuit region includes at least one active region extending along a first direction, and at least one gate region extending across the at least one active region and along a second direction transverse to the first direction. At least one first input/output (TO) pattern and at least one second TO pattern are correspondingly formed in different first and second metal layers to electrically couple the circuit region to external circuitry outside the circuit region. The at least one first TO pattern extends along a third direction oblique to both the first direction and the second direction. The at least one second TO pattern extends along a fourth direction oblique to both the first direction and the second direction, the fourth direction transverse to the third direction.
    Type: Application
    Filed: August 10, 2023
    Publication date: December 14, 2023
    Inventors: Jerry Chang Jui KAO, Meng-Kai HSU, Chin-Shen LIN, Ming-Tao YU, Tzu-Ying LIN, Chung-Hsing WANG
  • Publication number: 20230401370
    Abstract: A method executed at least partially by a processor includes determining a power parameter associated with a cell in an integrated circuit (IC) layout diagram. In response to the determined power parameter exceeding a design criterion, the method further includes performing a modification of the IC layout diagram, the modification including at least one of altering a placement of the cell in the IC layout diagram or modifying a power delivery path to the cell. The determining the power parameter is performed before a routing operation in the IC layout diagram.
    Type: Application
    Filed: August 9, 2023
    Publication date: December 14, 2023
    Inventors: Chin-Shen LIN, Hiranmay BISWAS, Kuo-Nan YANG, Chung-Hsing WANG
  • Publication number: 20230385518
    Abstract: A method of forming an integrated circuit includes forming at least a first or a second set of devices in a substrate, forming an interconnect structure over the first or second set of devices, and depositing a set of conductive structures on the interconnect structure. The first and second set of devices are configured to operate on a first supply voltage. Forming the interconnect structure includes depositing a set of insulating layers over the first or second set of devices, etching the set of insulating layers thereby forming a set of trenches, depositing a conductive material within the set of trenches, thereby forming a set of metal layers, and forming a portion of a header circuit between a first and a second metal layer. The header circuit is configured to provide the first supply voltage to the first set of devices.
    Type: Application
    Filed: July 18, 2023
    Publication date: November 30, 2023
    Inventors: John LIN, Chin-Shen LIN, Kuo-Nan YANG, Chung-Hsing WANG
  • Publication number: 20230376667
    Abstract: A method (of fabricating a power grid (PG) arrangement in a semiconductor) includes: forming a first layer including conductive lines (C_1st lines) which include interspersed alpha C_1st lines and beta C_1st lines designated correspondingly for first and second reference voltages; and forming a second layer over the first layer, the second layer including segments (C_2nd segments) which include interspersed alpha C_2nd segments and beta C_2nd segments designated correspondingly for the first and second reference voltages; and, relative to the first direction, each beta C_2nd segment being substantially asymmetrically between corresponding adjacent ones of the alpha C_2nd segments.
    Type: Application
    Filed: July 31, 2023
    Publication date: November 23, 2023
    Inventors: Hiranmay BISWAS, Chung-Hsing WANG, Chin-Shen LIN, Kuo-Nan YANG