Abstract: A pause command is sent to a Subscriber Identity Module (SIM) card of a cellular device in response to detecting a cyberattack against the cellular device on the cellular network. To mitigate the cyberattack, the SIM card temporarily disconnects the cellular device from the cellular network for a pause time. The SIM card prohibits the cellular device from connecting to the cellular network during the pause time and automatically allows the cellular device to reconnect to the cellular network after the pause time.

Abstract: Methods for analyzing electromigration (EM) in an integrated circuit (IC) are provided. A layout of the IC is obtained. A metal segment is selected from the layout according to a current simulation result of the IC. Two first vias are formed over and in contact with the metal segment in the layout. EM rule is kept on the metal segment when a distance between the two first vias is greater than a threshold distance. The EM rule is relaxed on the metal segment when the distance between the two first vias is less than or equal to the threshold distance.

Abstract: Failure-in-time (FIT) evaluation methods for an IC are provided. Data representing a layout of the IC is accessed, and the layout includes a metal line and a plurality of vertical interconnect accesses (VIAs). The metal line is divided into a first sub-line with a first line width and a second sub-line with a second line width. A plurality of nodes are picked along the first and second sub-lines of the metal line. The metal line is divided into a plurality of metal segments based on the nodes. FIT value is determined for each of the metal segments to verify the layout and fabricate the IC. The first line width is greater than the second line width.

Abstract: Methods for analyzing electromigration (EM) in an integrated circuit (IC) are provided. The layout of the IC is obtained. A metal segment is selected from the layout according to a current simulation result of the IC. EM rule is kept on the metal segment when a single via is formed over and in contact with the metal segment in the layout. The EM rule is relaxed on the metal segment when two first vias are formed over and in contact with the metal segment in the layout. The two first vias have the same current direction.

Abstract: A method (of fabricating a power grid (PG) arrangement in a semiconductor) includes: forming a first layer including conductive lines (C_1st lines)which include interspersed alpha C_1st lines and beta C_1st lines designated correspondingly for first and second reference voltages; and forming a second layer over the first layer, the second layer including segments (C_2nd segments) which include interspersed alpha C_2nd segments and beta C_2nd segments designated correspondingly for the first and second reference voltages; and, relative to the first direction, each beta C_2nd segment being substantially asymmetrically between corresponding adjacent ones of the alpha C_2nd segments.

Abstract: A touch device is provided. The touch device includes a substrate, a light-emitting element, a light-shielding member, a sensing board, and a light-passing board. The light-emitting element is disposed on the substrate. The light-shielding member is disposed on the substrate, wherein the light-shielding member has a first opening, and the light-emitting element is located in the first opening. The sensing board is disposed on the light-shielding member, and is electrically connected to the substrate. The sensing board has a second opening, and the first opening and the second opening overlap. The light-passing board is disposed on the sensing board, and covers the first opening and the second opening.

Abstract: A method of forming a semiconductor arrangement includes forming a first capacitor in a first voltage domain and forming a second capacitor in the first voltage domain. The first capacitor is connected in parallel with the second capacitor. A third capacitor and a fourth capacitor are formed in a second voltage domain. The third capacitor is connected in series with the fourth capacitor. The first capacitor and the second capacitor are connected in parallel with a supply terminal of the first voltage domain and a reference terminal of the first voltage domain. The fourth capacitor is connected to a supply terminal of the second voltage domain. The third capacitor is connected to a reference terminal of the second voltage domain.

Abstract: Provided herein are polynucleotides, rAAV vectors, pharmaceutical compositions, and methods of making and using the same, e.g., for treatment of cystic fibrosis (CF). For example, the disclosure provides a recombinant adeno-associated vims (rAAV) that includes, in one embodiment, an AV.TL65 capsid protein and a polynucleotide that includes an F5 enhancer and a tg83 promoter operably linked to a CFTR?R minigene, pharmaceutical compositions thereof, and methods of use thereof, e.g., for treatment of CF.

Abstract: An integrated circuit (IC) device includes a substrate and a circuit region over the substrate. The circuit region includes at least one active region extending along a first direction, at least one gate region extending across the at least one active region and along a second direction transverse to the first direction, and at least one first input/output (IO) pattern configured to electrically couple the circuit region to external circuitry outside the circuit region. The at least one first IO pattern extends along a third direction oblique to both the first direction and the second direction.

Abstract: An electronic device is provided. The electronic device includes a case, a mainboard, a cover and a locking module. The mainboard is disposed in the case. The cover covers the case. The locking module is disposed on the cover. The locking module includes a base, a latch, and a rotational member. The base is affixed to the cover. The latch is connected to the base, wherein the latch is moved between the first latch position and the second latch position relative to the base. The latch includes a recess and a protrusion. The rotational member is connected to the base. The rotational member is moved between the first rotational member position and the second rotational member position relative to the base. The rotational member includes a end portion, and the end portion is detachably connected to the recess. The locking module provides an automatic locking function.

Abstract: The disclosure provides methods of expressing a transgene in a cell, methods of treating disorders in a subject in need thereof, and pharmaceutical compositions. In particular, the methods involve contacting a cell (e.g., a cell of a subject suffering from a disorder such as cystic fibrosis) with a recombinant adeno-associated virus (rAAV) that includes, in one embodiment, an AV.TL65 capsid protein and a polynucleotide that includes a transgene in combination with an augmenter of AAV transduction, thereby expressing the transgene in the cell. The disclosure also provides pharmaceutical compositions that include an rAAV that includes, in one embodiment, an AV.TL65 capsid protein and a polynucleotide including a transgene in combination with one or more augmenters.

Abstract: A failure-in-time (FIT) evaluation method for an IC is provided. The FIT evaluation method includes accessing data representing a layout of the IC including a metal line and a plurality of vertical interconnect accesses (VIAs); picking a plurality of nodes along the metal line; dividing the metal line into a plurality of metal segments based on the nodes; and determining FIT value for each of the metal segments to verify the layout and fabricate the IC. The number of the nodes is less than the number of the VIAs, and a distance between two adjacent VIAs of the VIAs is less than a width of the metal line.

Abstract: An electrically and thermally conductive gasket includes a resilient core including a plurality of sides, a heat spreader disposed along at least two sides of the plurality of sides of the resilient core, and an electrically conductive layer disposed along and/or covering at least a portion of the heat spreader, such that the portion of the heat spreader is between the resilient core and the electrically conductive layer. The gasket is positionable and/or compressible between first and second surfaces to thereby define an electrically conductive path and a thermally conductive path between the first and second surfaces.

Abstract: A detection kit is suitable for detecting a target compound. The detection kit includes a reaction container, an inspection solution composed of a hydrophobic solvent, and a plurality of fluorescent materials. The inspection solution is disposed in the reaction container. The fluorescent materials are dispersed in the inspection solution. The fluorescent material emits fluorescence, and after the fluorescent materials interact with the target compound, the intensity of the fluorescence emitted by the fluorescent materials is reduced.

Abstract: A method (of fabricating a power grid (PG) arrangement in a semiconductor) includes: forming a first conductive layer including segments which are conductive, including forming first segments designated for a first reference voltage and second segments designated for a second reference voltage, and interspersing the first and second segments; relative to a first direction; and forming a second conductive layer over the first conductive layer, the second conductive layer including segments that are conductive, including forming third segments designated for the first reference voltage and fourth segments designated for the second reference voltage, interspersing the third and fourth segments relative to a second direction, the second direction being perpendicular to the first direction, and arranging the segments in the second conductive layer substantially asymmetrically including, relative to the first direction, locating each fourth segment substantially asymmetrically between corresponding adjacent ones of

Abstract: A method of forming an IC structure includes forming first and second power rails at a power rail level. First metal segments are formed at a first metal level above the power rail level. Each first metal segment of the plurality of first metal segments overlap one or both of the first power rail or the second power rail. First vias are formed between the power rail level and the first metal level. Second metal segments are formed at a second metal level above the first metal level. At least one second metal segment of the plurality of second metal segments overlaps the first power rail. At least one second metal segment of the plurality of second metal segments overlaps the second power rail. A plurality of second vias are formed between the first metal level and the second metal level.

Abstract: A system includes a processor configured to determine a power parameter associated with a cell in an integrated circuit (IC) layout diagram. In response to the determined power parameter exceeding a design criterion, the processor is configured to perform a modification of the IC layout diagram, the modification including at least one of altering a placement of the cell in the IC layout diagram or modifying a power delivery path to the cell. The power parameter includes at least one of a power density of a tile containing the cell, a voltage drop of the tile containing the cell, or a voltage drop of the cell.

Abstract: An integrated circuit (IC) structure includes a power rail oriented in a power rail direction and first metal segments above the power rail, oriented in a first metal level direction perpendicular to the power rail direction. First vias positioned between the power rail and the first metal segments are positioned at locations where first metal segments overlap the power rail. A second metal segment is positioned above the first metal segments, overlaps the power rail, and is oriented in the power rail direction. Second vias are positioned above the first vias between the first metal segments and the second metal segments, and a power strap is positioned above the second metal segment. The power strap is electrically connected to the power rail, each first metal segment of the plurality of first metal segments has a minimum width, and the power strap has a width greater than a minimum width.

Abstract: A method for manufacturing a semiconductor device is provided. The method comprises determining a dimensional quantity of a layout pattern having an angle relative to grid lines of a minimum grid. The minimum grid may be defined by a first quantity associated with a first direction and a second quantity associated with a second direction perpendicular to the first direction. The determination of the dimensional quantity of the layout pattern is based on the first quantity, the second quantity and the angle of the layout pattern relative to the grid lines of the minimum grid.

Abstract: Disclosed are systems for applying materials to components. The system comprises a tool operable for transferring a portion of a material from a supply of the material to a component. A first portion of the tool may be configured for cutting along a side or edge of the portion of the material. A second portion of the tool may be configured for tamping, pressing, or pushing against the portion of the material to cause uncut sides or edges of the portion of the material attached to the supply of the material to be torn, severed, detached, or separated from the supply of the material.