Abstract: A controlling method for semiconductor process auxiliary apparatus, a control assembly and a manufacturing system are provided. The controlling method includes the following steps. At least one manufacturing parameter of a semiconductor manufacturing processing apparatus are obtained. An energy adjusting signal is generated according to the manufacturing parameter. An auxiliary apparatus controlling signal is generated according to the energy adjusting signal. The semiconductor process auxiliary apparatus is controlled according to the semiconductor auxiliary apparatus controlling signal.

Abstract: A nitrogen-branched non-linear PEGylated lipid of Formula (1), wherein, X is —CRa< or (Ra is H or a C1-12 alkyl group); B1 and B2 are linking bonds or C1-20 alkylene groups; L1 and L2 are linking bonds or divalent linking groups; R1 and R2 are C1-50 aliphatic hydrocarbon groups or C1-50 residues of aliphatic hydrocarbon derivative, each containing 0-10 heteroatoms; Ld is a linking bond or a divalent linking group; Ncore is a multivalent group of valence y+1, and contains a trivalent nitrogen-atom branching core connected to Ld; y is 2, 3, 4, 5, 6, 7, 8, 9, or ?10; Lx is a linking bond or a divalent linking group; XPEG is a polyethylene glycol component. The non-linear PEGylated lipid herein can realize better surface modification of LNP. The lipid nanoparticle pharmaceutical composition and its formulation exhibit higher drug efficacy, especially for nucleic acid drugs.

Abstract: A pixel driving circuit includes a first transistor, a second transistor, and a first capacitor. The first transistor is configured to receive a data signal and drive a light emitting element based on the data signal. The first transistor includes a first gate terminal, a first source terminal, and a first drain terminal. The second transistor includes a second gate terminal receiving a first bias signal from a first bias source, a second source terminal coupled to the first transistor, and a second drain terminal coupled to the light emitting element. The first capacitor is disposed between the first gate terminal and the second gate terminal. The first transistor and the second transistor are different types of transistors.

Abstract: A light-emitting diode chip includes a substrate. The substrate has a side surface configured as a serrated surface, which includes a plurality of laser inscribed features disposed along a thickness direction of the substrate and spaced apart from each other. A method for manufacturing the light-emitting diode chip is also disclosed herein.

Abstract: A method for system profiling and controlling and a computer system performing the same are provided. In the method, an operating system is operated after the computer system is booted, in which a profiling-controlling system is operated. When the operating system loads and executes a system profiling-controlling program, the profiling-controlling system that simultaneously operates a profiling routine and a controlling routine is initiated. The profiling routine is used to retrieve system kernel data that is generated during operation of the operating system and analyze the system kernel data through a kernel tracing tool. When it is determined that controlling is required, the profiling routine notifies the controlling routine. The controlling routine controls operating parameters of the operating system in real time according to an analysis result generated by the profiling routine.

Abstract: A lens module, constructed to include all necessary filters but retaining its wide-angle characteristic and short focal length, is comprised of a housing, a cover plate, and a filter switcher. The housing and the cover plate form a receiving cavity, the cavity containing the filter switcher. The filter switcher includes holder, two mounting frames, two first adhesive layers, and two filters, and is of minimal thickness. The two first adhesive layers fix the filters on the two mounting frames. An enlarged installation space within the lens module is not required. The disclosure also relates to an electronic device using the lens module.

Abstract: An information security threat determination method and an information security threat determination device are provided. The information security threat determination method and the information security threat determination device are applicable to a network system including a terminal, a core network and a server. The information security threat determination method includes the following steps: receiving information about an abnormal event occurring in the network system; performing a cause and effect tree inspection procedure to generate a plurality of tracing causes according to the abnormal event and deploying a virtual terminal and a virtual server to communicate through the core network to verify whether each tracing cause will cause the abnormal event, thereby generating inspection result; and performing decision chain procedure to determine the abnormal event as non-information security threat event or information security threat event according to the inspection result.

Abstract: A package structure is provided. The package structure comprises a package substrate, an electronic device, a thermal interface material (TIM), a lid and an insulating encapsulant. The electronic device is disposed on and electrically connected to the package substrate. The TIM is disposed on the electronic device. The lid is disposed on the TIM. The insulating encapsulant is disposed on the package substrate and laterally encapsulates the electronic device and the TIM. A lateral dimension of the TIM is greater than a lateral dimension of the electronic device.

Abstract: A pixel structure is provided. The pixel structure includes a substrate, a micro light-emitting diode, and an electrophoretic structure. The micro light-emitting diode is disposed on the substrate and configured to emit light. The electrophoretic structure is disposed on the micro light-emitting diode and includes an upper electrode, a lower electrode, an electrophoretic medium, and an electrophoretic lens. The electrophoretic medium is disposed between the upper electrode and the lower electrode, wherein the electrophoretic medium has a first refractive index. The electrophoretic lens is disposed in the electrophoretic medium and has a second refractive index that is different from the first refractive index. The electrophoretic lens is configured to move away from or toward the micro light-emitting diode by being driven by the electric field, so that light passing through the electrophoretic lens has a first or second divergence angle after refracting.

Abstract: An encapsulation structure including a substrate, an isolation structure layer, a planarization layer, and a composite layer structure is disclosed. The isolation structure layer is disposed on the substrate and defines multiple sub-pixel areas. The polarization layer is disposed on the substrate, and has a peripheral portion surrounding and covering the isolation structure layer. A thickness of the peripheral portion increases as it approaches the isolation structure layer. The composite layer structure connects the substrate and covers the planarization layer and the isolation structure layer. The composite layer includes two barrier layers and an extension layer. The extension layer is located between and connects the two barrier layers. A thickness, a water vapor transmission rate, and ductility and malleability of the extension layer are respectively greater than a thickness, a water vapor transmission rate, and ductility and malleability of each of the two barrier layers.

Abstract: A transistor includes an insulating layer, a source region, a drain region, a channel layer, a ferroelectric layer, and a gate electrode. The source region and the drain region are respectively disposed on and in physical contact with two opposite sidewalls of the insulating layer. A thickness of the source region, a thickness of the drain region, and a thickness of the insulating layer are substantially the same. The channel layer is disposed on the insulating layer, the source region, and the drain region. The ferroelectric layer is disposed over the channel layer. The gate electrode is disposed on the ferroelectric layer.

Abstract: The present disclosure relates to exclusion rings for use in processing a semiconductor substrate in a processing chamber, such as a chemical vapor deposition chamber. The exclusion ring includes an alignment structure that cooperates with an alignment structure on a platen on which the exclusion ring will rest during processing of the wafer. The first alignment structure includes a guiding surface which promotes the reception of and positioning of the second alignment structure within the first alignment structure. Methods of utilizing the described exclusion rings are also described.

Abstract: The invention provides a non-invasive blood glucose monitoring device with a wearing fit detection function, comprising a substrate, a blood glucose monitoring module, an optical feedback sensing module and at least one light-blocking wall. The substrate defines a first setting area for disposing the blood glucose monitoring module and a second setting area for disposing the optical feedback sensing module. The second setting area is between an edge of the substrate and the first setting area. The optical feedback sensing module includes at least one light-emitting element and at least one light-receiving element. Each light-emitting element emits a light signal corresponding to at least one specific wavelength, and each light-receiving element receives the light signal corresponding to the at least one specific wavelength, after being reflected, as a basis for determining the wearing fit. The at least one light-blocking wall is located between the first setting area and the second setting area.

Abstract: The present disclosure provides a single-channel test device. The single-channel test device includes a metal flange, and a waveguide-coaxial conversion structure and a first square straight waveguide which are disposed along a central axis of the metal flange and disposed on two opposite sides of the metal flange respectively, wherein in the case that a waveguide aperture of one end of the first square straight waveguide distal to the metal flange is placed on and is kept in close contact with a single antenna unit to be tested in a phased reflectarray to be tested, the single-channel test device is configured to test a scattering parameter of the antenna unit to be tested.

Abstract: A wireless charging device is disclosed. At least one floating charging component is arranged in the wireless charging device, the floating charging component comprises a supporting plate, a power transmission coil, and a magnetic element, the top wall of a housing is provided with at least one mounting hole, and the floating charging component is movably arranged in the mounting hole, so that when the device to be charged is placed on a bearing surface of the top wall, the magnetic element is able to attract the device to be charged so that the outer surface of the supporting plate contacts with the device to be charged, so that ensures that the power transmission coil and the device to be charged be aligned with each other and the distance between them is small, thereby ensuring the wireless charging rate.

Abstract: A memory device including a base semiconductor die, conductive terminals, memory dies, an insulating encapsulation and a buffer cap is provided. The conductive terminals are disposed on a first surface of the base semiconductor die. The memory dies are stacked over a second surface of the base semiconductor die, and the second surface of the base semiconductor die is opposite to the first surface of the base semiconductor die. The insulating encapsulation is disposed on the second surface of the base semiconductor die and laterally encapsulates the memory dies. The buffer cap covers the first surface of the base semiconductor die, sidewalls of the base semiconductor die and sidewalls of the insulating encapsulation. A package structure including the above-mentioned memory device is also provided.

Abstract: A toy gun and a gas cylinder piercing structure are provided. The gas cylinder piercing structure includes a screw base and a movable push rod unit. The screw base includes a circular through-hole and an annular block around it. A top of the annular block has a slot. The movable push rod unit includes a round push rod movably inserted in the circular through-hole, and a return spring between the screw base and the round push round. A top of the round push rod has a striker pin. The striker pin extends with a needle portion. The striker pin has an engagement lug and a notch. When the engagement lug is blocked by the annular block, the round push rod completely fills the circular through-hole. When the engagement lug is engaged with the slot, the notch and the circular through-hole together form an air vent channel.

Abstract: Herein disclosed is a microfluidic device comprising: semi-spiral-shaped channels in fluid communication with (i) at least two inlet ports and (ii) at least two outlet ports, wherein the at least two inlet ports comprise: a sample inlet port and a sheath inlet port, wherein the sample inlet port is in fluid communication with sample inlet channels, each of the sample inlet channels is connected to one semi-spiral-shaped channel, and wherein the sheath inlet port is in fluid communication with sheath inlet channels, each of the sheath inlet channels is connected to one semi-spiral-shaped channel; wherein the at least two outlet ports comprise a first outlet port and each of the semi-spiral-shaped channels has a first outlet channel connected to the first outlet port, and wherein each first outlet channel is longer than any other outlet channel connected to the same semi-spiral-shaped channel. A method of fractionating particles is also disclosed.

Abstract: A semiconductor device includes a substrate having a first conductivity type and an epitaxial layer disposed on the substrate. A first trench and a second trench are disposed in the epitaxial layer. A first body region and a second body region both having a second conductivity type are disposed in the epitaxial layer, and located on two sides of the first trench, respectively. A first source region and a second source region both having the first conductivity type are disposed on the first body region and the second body region, respectively. A first electrode is disposed in the first trench. A source contact structure includes a first portion disposed in the first trench and is electrically connected to the first source region and the second source region. A first gate is disposed in the second trench.

Abstract: A transistor including a channel layer including an oxide semiconductor material and methods of making the same. The transistor includes a channel layer having a first oxide semiconductor layer having a first oxygen concentration, a second oxide semiconductor layer having a second oxygen concentration and a third oxide semiconductor layer having a third oxygen concentration. The second oxide semiconductor layer is located between the first semiconductor oxide layer and the third oxide semiconductor layer. The second oxygen concentration is lower than the first oxygen concentration and the third oxygen concentration.