Abstract: A toy gun includes a gun body, an action assembly, and a pressure diverter. The gun body includes a barrel and a gas flow conduit. The action assembly is installed on the gun body and includes a piston. The pressure diverter is received in the gun body and arranged between the barrel, the gas flow conduit, and the piston. The gas diverter includes a gas collection cavity and an inlet hole, a first outlet hole and a second outlet hole communicating to the gas collection cavity. The inlet hole is arranged corresponding to the gas flow conduit, the first outlet hole is arranged corresponding to the barrel, the second outlet hole is arranged corresponding to the piston. The cross-sectional area of the first outlet hole is greater than that of the second outlet hole.

Abstract: A memory circuit includes a memory array including a plurality of memory cells, each memory cell of the plurality of memory cells including an n-type channel layer including a metal oxide material, and a gate structure overlying and adjacent to the n-type channel layer, the gate structure including a conductive layer overlying a ferroelectric layer. The memory circuit is configured to apply a gate voltage to each memory cell of the plurality of memory cells in first and second write operations, the gate voltage has a positive polarity and a first magnitude in the first write operation and a negative polarity and a second magnitude greater than the first magnitude in the second write operation.

Abstract: The present disclosure provides an integrated circuit (IC) structure. The IC structure includes a semiconductor substrate; an interconnection structure formed on the semiconductor substrate; and a redistribution layer (RDL) metallic feature formed on the interconnection structure. The RDL metallic feature further includes a barrier layer disposed on the interconnection structure; a diffusion layer disposed on the barrier layer, wherein the diffusion layer includes metal and oxygen; and a metallic layer disposed on the diffusion layer.

Abstract: A semiconductor device manufacturing system and a method for manufacturing semiconductor device are provided. The semiconductor device manufacturing system includes a substrate processing device and a processor. The substrate processing device includes a processing chamber, a gas supply module and a gas source. The processor is configured to monitor and control the gas supplied into the substrate processing device.

Abstract: Disclosed are compositions and methods for treating disease or condition caused or exacerbated by S100A9 activity, such as myelodysplastic syndromes (MDS) using a composition comprising an effective amount of a CD33/S100A9 inhibitor.

Abstract: A wafer drying method that detects molecular contaminants in a drying gas as a feedback parameter for a multiple wafer drying process is disclosed. For example, the method includes dispensing, in a wafer drying module, a drying gas over a batch of wafers. Further, the method includes collecting the drying gas from an exhaust of the wafer drying module and determining the concentration of contaminants in the drying gas. The method also includes re-dispensing the drying gas over the batch of wafers if the concentration of contaminants is greater than a baseline value and transferring the batch of wafers out of the wafer drying module if the concentration is equal to or less than the baseline value.

Abstract: A motor and a rotating shaft cooling device thereof are disclosed. A rotating shaft of the motor is formed with an annular space. A shaft has a front end and a rear end. The shaft is a blind tube formed with a channel communicating with the annular space through a plurality of nozzles. The distance between the nozzles and the rear end is less than one-half of the length of the shaft. A cooling fluid flows through the nozzles to form a jet array to impinge on the inner wall of the rotating shaft to cool the rotating shaft, and flows back in the annular space to enhance the cooling effect, increase the heat exchange area, and improve the cooling effectiveness of the rotating shaft.

Abstract: A method is provided forming an airtight structure of an electroacoustic device which includes a body shell composed of at least two half-shells and at least one airtight structure region. The method includes providing an automatic glue dispensing device for dispensing and pre-curing a photo-curing glue for one of the two half-shells, putting the half-shell into a photo-curing device to convert the photo-curing glue pre-cured completely into an elastomer, and combining the half-shell and the other one to have a pressing wall of the other half-shell to press the elastomer to form the airtight structure of the electroacoustic device, wherein the automatic glue dispensing device includes a glue dispensing head moving on a groove of the airtight region of the half-shell for dispensing the photo-curing glue and a pre-curing head continuously providing a curing light ray for pre-curing the photo-curing glue.

Abstract: The present disclosure relates to an apparatus and a method for wafer cleaning. The apparatus can include a wafer holder configured to hold a wafer; a cleaning nozzle configured to dispense a cleaning fluid onto a first surface (e.g., front surface) of the wafer; and a cleaning brush configured to clean a second surface (e.g., back surface) of the wafer. Using the cleaning fluid, the cleaning brush can clean the second surface of the wafer with a scrubbing motion and ultrasonic vibration.

Abstract: An array of vertical transistors comprises spaced pillars of individual vertical transistors that individually comprise an upper source/drain region, a lower source/drain region, and a channel region vertically there-between. The upper source/drain region comprises a conductor oxide material in individual of the pillars. The channel region comprises an oxide semiconductor material in the individual pillars. The lower source/drain region comprises a first conductive oxide material in the individual pillars atop and directly against a second conductive oxide material in the individual pillars. Horizontally-elongated and spaced conductor lines individually interconnect a respective multiple of the vertical transistors in a column direction. The conductor lines individually comprise the second conductive oxide material atop and directly against metal material. The first conductive oxide material, the second conductive oxide material, and the metal material comprise different compositions relative one another.

Abstract: The present invention provides a respiratory mask comprising a nose cushion assembly. The nose cushion assembly comprises a base body and a buffering piece. The base body has a base intake portion, a base connection portion, and an air routing piece disposed at the inside of the base body and having a partitioning wall and a wall connection piece. The inside of the partitioning wall encloses an air intake zone. The wall connection piece is disposed outside the partitioning wall and connects with the base intake portion. Between the partitioning wall and the base intake portion there is defined an air outtake zone. The air intake zone is approximately at the center of the base intake portion. The buffering piece connects with the base connection portion and encloses a nose containing room, which in turn connects with the inside of the base body.

Abstract: An optical imaging lens includes five lens elements arranged from an object side to an image side in a given order along an optical axis of the optical imaging lens. The object-side surface of the second lens element has a convex portion in a vicinity of its periphery, the object -side surface of the third lens element has a convex portion in a vicinity of the optical axis, the object-side surface of the fourth lens element has a concave portion in a vicinity of its periphery, the optical imaging lens as a whole has only the five lens elements, and an effective system focal length is EFL, an air gap between the second lens element and the third lens element along the optical axis is G23, a central thickness of the third lens element along the optical axis is T3, and EFL, G23 and T3 satisfy the equation 4.89?EFL/(G23+T3)?5.88.

Abstract: A test kit for testing a device under test (DUT) includes a socket structure for containing the DUT, and a plunger assembly detachably coupled with the socket structure. The plunger assembly includes a multi-layered structure having at least an interposer substrate sandwiched by a top socket and a nest.

Abstract: A memory circuit includes a memory array including a plurality of memory cells, each memory cell including a gate structure including a ferroelectric layer and a channel layer adjacent to the gate structure, the channel layer including a metal oxide material. A driver circuit is configured to output a gate voltage to the gate structure of a memory cell, the gate voltage having a positive polarity and a first magnitude in in a first write operation and a negative polarity and a second magnitude in in a second write operation, and to control the second magnitude to be greater than the first magnitude.

Abstract: The present disclosure provides an integrated circuit (IC) structure. The IC structure includes a semiconductor substrate; an interconnection structure formed on the semiconductor substrate; and a redistribution layer (RDL) metallic feature formed on the interconnection structure. The RDL metallic feature further includes a barrier layer disposed on the interconnection structure; a diffusion layer disposed on the barrier layer, wherein the diffusion layer includes metal and oxygen; and a metallic layer disposed on the diffusion layer.

Abstract: A method of fabrication of a multi-gate semiconductor device that includes providing a fin having a plurality of a first type of epitaxial layers and a plurality of a second type of epitaxial layers. The plurality of the second type of epitaxial layers is oxidized in the source/drain region. A first portion of a first layer of the second type of epitaxial layers is removed in a channel region of the fin to form an opening between a first layer of the first type of epitaxial layer and a second layer of the first type of epitaxial layer. A portion of a gate structure is then formed in the opening.

Abstract: An array of vertical transistors comprises spaced pillars of individual vertical transistors that individually comprise an upper source/drain region, a lower source/drain region, and a channel region vertically there-between. The upper source/drain region comprises a conductor oxide material in individual of the pillars. The channel region comprises an oxide semiconductor material in the individual pillars. The lower source/drain region comprises a first conductive oxide material in the individual pillars atop and directly against a second conductive oxide material in the individual pillars. Horizontally-elongated and spaced conductor lines individually interconnect a respective multiple of the vertical transistors in a column direction. The conductor lines individually comprise the second conductive oxide material atop and directly against metal material. The first conductive oxide material, the second conductive oxide material, and the metal material comprise different compositions relative one another.

Abstract: Provided are a gate structure and a method of forming the same. The gate structure includes a gate dielectric layer, a metal layer, and a cluster layer. The metal layer is disposed over the gate dielectric layer. The cluster layer is sandwiched between the metal layer and the gate dielectric layer, wherein the cluster layer at least includes an amorphous silicon layer, an amorphous carbon layer, or an amorphous germanium layer. In addition, a semiconductor device including the gate structure is provided.

Abstract: A method of preparing polylactic acid (PLA) microsphere and polylactic-co-glycolic acid (PLGA) microsphere is provided, including the following steps. A first solution is provided, including polylactic acid or polylactic-co-glycolic acid and an organic solvent. A second solution is provided, including polyvinyl alcohol, sodium carboxymethyl cellulose and an aqueous solution. The first solution is added to the second solution and, at the same time, the second solution is agitated until polylactic acid is solidified to form a plurality of polylactic acid microspheres, or until polylactic-co-glycolic acid is solidified to form a plurality of polylactic-co-glycolic acid microspheres. The polylactic acid microspheres or polylactic-co-glycolic acid microspheres are collected.

Abstract: A semiconductor device includes a first passivation layer over a substrate. The semiconductor device further includes a post passivation interconnect (PPI) line over the first passivation layer, wherein a top-most portion of the PPI line has a first portion having a convex shape and a second portion having a concave shape. The semiconductor device further includes a second passivation layer configured to cause stress to the PPI line. The semiconductor device further includes a polymer material over the second passivation layer.