Patents by Inventor Sheng Wei
Sheng Wei has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Publication number: 20230236222Abstract: This disclosure provides a test kit for testing a device under test (DUT) including a socket structure for containing the DUT, and a plunger assembly detachably coupled with the socket structure. The plunger assembly includes a multi-layered structure having a nest and an interposer substrate installed under the nest.Type: ApplicationFiled: March 30, 2023Publication date: July 27, 2023Applicant: MEDIATEK INC.Inventors: Jing-Hui Zhuang, Ying-Chou Shih, Sheng-Wei Lei, Chang-Lin Wei, Che-Hsien Huang, Shih-Chia Chiu, Yi-Chieh Lin, Wun-Jian Lin
-
Patent number: 11699683Abstract: A semiconductor device with an interface includes a master device and a plurality of slave devices. The master device includes a master interface. The slave devices are stacked on the master device one after one as a three-dimension (3D) stack. Each of the slave devices includes a slave interface and a managing circuit, the master interface and the slave interfaces form the interface for passing signals in communication between the master device and the slave devices. The managing circuit of a current one of the slave devices drives a next one of the slave devices. An operation command received at the current one of the slave devices is just passed to the next one of the slave devices through the interface. A response from the current one of the slave devices is passed back to the master device through the interface.Type: GrantFiled: September 30, 2020Date of Patent: July 11, 2023Assignees: Global Unichip Corporation, Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Igor Elkanovich, Amnon Parnass, Pei Yu, Li-Ken Yeh, Yung-Sheng Fang, Sheng-Wei Lin, Tze-Chiang Huang, King Ho Tam, Ching-Fang Chen
-
Patent number: 11693474Abstract: The present invention provides a circuitry applied to multiple power domains. An amplifier of the circuitry includes an output stage and a switching circuit. The output stage includes a first transistor and a second transistor, wherein the first transistor is coupled between a supply voltage and an output terminal, the second transistor is coupled between the output terminal and a ground voltage. The switching circuit is configured to choose a body of the first transistor from the supply voltage or a reference voltage.Type: GrantFiled: May 25, 2021Date of Patent: July 4, 2023Assignee: Realtek Semiconductor Corp.Inventors: Wei-Cheng Tang, Li-Lung Kao, Chia-Ling Chang, Sheng-Wei Lin, Sheng-Tsung Wang
-
Publication number: 20230204558Abstract: A water quality monitoring device and a monitoring method thereof are provided. The water quality monitoring device includes a water tank, a first and a second optical detection devices and a control circuit. The water tank has an accommodating space to carry a liquid. The first optical detection device provides a first light to detect and obtain a first reference light intensity, a first scattered light intensity, and a first penetrating light intensity. The second optical detection device provides a second light to detect and obtain a second reference light intensity, a second scattered light intensity, and a second penetrating light intensity. The control circuit calculates a water quality detection value of the liquid based on the first reference light intensity, the first scattered light intensity, the first penetrating light intensity, the second reference light intensity, the second scattered light intensity, and the second penetrating light intensity.Type: ApplicationFiled: December 24, 2021Publication date: June 29, 2023Applicant: Industrial Technology Research InstituteInventors: Chen-Hua Chu, Chun-Kuo Liu, Yi-Hong Liu, Chi-Fan Wang, Jung-Hao Wang, Sheng-Wei Peng, Yu-Xuan Lin
-
Patent number: 11687472Abstract: An interface for a semiconductor device is provided. The semiconductor device has a master device and multiple slave devices as stacked up with electric connection. The interface includes a master interface, implemented in the master device and including a master interface circuit with a master bond pattern. Further, a slave interface is implemented in each slave device and includes a slave interface circuit with a slave bond pattern to correspondingly connect to the master bond pattern. A clock route is to transmit a clock signal through the master interface and the slave interface. The master device transmits a command and a selecting slave identification through the master interface to all the slave interfaces. One of the slave devices corresponding to the selecting slave identification executes the command and responds a result back to the master device through the slave interfaces and the master interface.Type: GrantFiled: August 20, 2020Date of Patent: June 27, 2023Assignees: GLOBAL UNICHIP CORPORATION, Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Igor Elkanovich, Amnon Parnass, Pei Yu, Li-Ken Yeh, Yung-Sheng Fang, Sheng-Wei Lin, Tze-Chiang Huang, King Ho Tam, Ching-Fang Chen
-
Publication number: 20230191898Abstract: A vehicle drive system includes a motor (drive motor), a generator, a reduction drive that reduces output of the motor, and a housing. At a position above a motor shaft, an oil passage, through which oil is supplied to each of the motor, the reduction drive, and the generator, is integrally formed with the housing. An oil pipe is attached to the housing and supplies the oil from an oil reservoir to the oil passage. At a position between the motor and the generator, the reduction drive is offset from the motor shaft in a second direction that is orthogonal to the first direction. The oil pipe is located between the motor and the generator in the first direction, and at least part of the oil pipe is located on an opposite side of the reduction drive with the motor shaft being interposed therebetween in the second direction.Type: ApplicationFiled: December 7, 2022Publication date: June 22, 2023Inventors: Yuya Yamaoka, Ryuichiro Amano, Yoshiaki Noguchi, Masaaki Kashimoto, Yusuke Oki, Li-Hsuan Huang, Sheng-Wei Chang
-
Patent number: 11680107Abstract: The present disclosure relates to a biodegradable and thermosensitive hydrogel composition comprising a diblock PLGA-PEG copolymer and a triblock PLGA-PEG-PLGA copolymer. A method for treating or alleviating one or more symptoms of a disease and a method for delivering an active agent are also provided.Type: GrantFiled: March 20, 2020Date of Patent: June 20, 2023Assignee: Taipei Medical UniversityInventors: Shyr-Yi Lin, Ming-Thau Sheu, Kuo-Hsiang Chuang, Yi-Jou Chen, Pu-Sheng Wei
-
Publication number: 20230182956Abstract: Embodiments of the disclosure are directed to a transportation system for carrying servers. The transportation system includes a server rack and a shock-absorbing pallet. The shock-absorbing pallet is secured under the server rack and configured to move relative to the server rack to dampen vibration during transportation of the server rack. The shock-absorbing pallet includes a top cover, a bottom cover, one or more isolation devices, and one or supporting layers. The one or more isolation devices are disposed between the top cover and the bottom cover. Each isolation device includes a shock-absorbing component coupled to the top cover and the bottom cover. The one or more supporting layers are secured between the top cover and the bottom cover around the one or more isolation devices. The one or more supporting layers have a plurality of slots for guiding a pallet lifter therethrough.Type: ApplicationFiled: December 14, 2021Publication date: June 15, 2023Inventors: Chao-Jung CHEN, Ming-Sheng CHANG, Sheng-Wei TANG, Ta-Chih CHEN
-
Patent number: 11676494Abstract: The present invention discloses a vessel collision avoiding system and method based on Artificial Potential Field algorithm, the method comprises the following steps: (S1) obtaining a vessel information, at least one obstacle information and a target information; (S2) establishing an Artificial Potential Field (APF) by the vessel information, the at least one obstacle information and the target information, wherein the Artificial Potential Field comprises an attractive field of the target and a repulsive field of the obstacle; (S3) combining the attractive field and the repulsive field to obtain a first resultant force; (S4) Adding an external force to the Artificial Potential Field based on the vessel information or the obstacle information; (S5) combining the first resultant force and the external force to obtain a second resultant force; and (S6) the vessel sails in the direction of the second resultant force to avoid the obstacle.Type: GrantFiled: March 23, 2020Date of Patent: June 13, 2023Assignee: SHIP AND OCEAN INDUSTRIES R&D CENTERInventors: Feng-Yeang Chung, Chun-Han Chu, Chi-Min Liao, Mu-Hua Chen, Ling-Ji Mu, Li-Yuan Zhang, Sheng-Wei Huang
-
Patent number: 11675731Abstract: A data protection system and a data protection method for handling an errored command are provided. The data protection system includes a master device and a slave device. The master device is configured to send command. The slave device is coupled to the master device. The save device is configured to receive the command from the master device. The master device includes a master interface. The slave device includes a slave interface. The master interface and the slave interface are electrically connected via one or plurality of bonds and/or TSVs and configured for interfacing between the master device and the slave device. The errored command represents the command having a parity or other error. The slave device is further configured to receive the errored command and to respond the errored command according to read or write operation.Type: GrantFiled: September 30, 2020Date of Patent: June 13, 2023Assignees: Global Unichip Corporation, Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Igor Elkanovich, Amnon Parnass, Pei Yu, Li-Ken Yeh, Yung-Sheng Fang, Sheng-Wei Lin, Tze-Chiang Huang, King Ho Tam, Ching-Fang Chen
-
Publication number: 20230153535Abstract: A device and method for generating article markup information are provided. The method for generating article markup information includes the following. Segmentation processing is performed on an article to generate a segmentation result. Name entity recognition is performed on the segmentation result to generate a first recognition result. Whether the segmentation result includes any word in an expansion list is determined. Expanded entity classification conversion is performed on the first recognition result to generate a second recognition result. The second recognition result and the segmentation result are used as markup information.Type: ApplicationFiled: January 4, 2022Publication date: May 18, 2023Applicant: Acer IncorporatedInventors: Yi-Chun Lin, Yueh-Yarng Tsai, Pin-Cyuan Lin, Ke-Han Pan, Sheng-Wei Chu
-
Patent number: 11625813Abstract: The present disclosure describes systems, non-transitory computer-readable media, and methods for accurately and efficiently removing objects from digital images taken from a camera viewfinder stream. For example, the disclosed systems access digital images from a camera viewfinder stream in connection with an undesired moving object depicted in the digital images. The disclosed systems generate a temporal window of the digital images concatenated with binary masks indicating the undesired moving object in each digital image. The disclosed systems further utilizes a 3D to 2D generator as part of a 3D to 2D generative adversarial neural network in connection with the temporal window to generate a target digital image with the region associated with the undesired moving object in-painted. In at least one embodiment, the disclosed systems provide the target digital image to a camera viewfinder display to show a user how a future digital photograph will look without the undesired moving object.Type: GrantFiled: October 30, 2020Date of Patent: April 11, 2023Assignee: Adobe, Inc.Inventors: Sheng-Wei Huang, Wentian Zhao, Kun Wan, Zichuan Liu, Xin Lu, Jen-Chan Jeff Chien
-
Patent number: 11624758Abstract: A test kit for testing a device under test (DUT) includes a socket structure for containing the DUT. The DUT includes an antenna and radiates a RF signal. The test kit further includes a reflector having a lower surface. The RF signal emitted from the antenna of the DUT is reflected by the reflector and a reflected RF signal is received by the antenna of the DUT.Type: GrantFiled: March 24, 2021Date of Patent: April 11, 2023Assignee: MEDIATEK INC.Inventors: Sheng-Wei Lei, Chang-Lin Wei, Ying-Chou Shih, Yeh-Chun Kao, Yen-Ju Lu, Po-Sen Tseng
-
Patent number: 11622134Abstract: Embodiments of a system and method for low-latency content streaming are described. In various embodiments, multiple data fragments may be sequentially generated. Each data fragment may represent a distinct portion of media content generated from a live content source. Each data fragment may include multiple sub-portions. Furthermore, for each data fragment, generating that fragment may include sequentially generating each sub-portion of that fragment. Embodiments may include, responsive to receiving a request for a particular data fragment from a client during the generation of a particular sub-portion of that particular data fragment, providing the particular sub-portion to the client subsequent to that particular sub-portion being generated and prior to the generation of that particular data fragment being completed in order to reduce playback latency at the client relative to the live content source.Type: GrantFiled: May 27, 2021Date of Patent: April 4, 2023Assignee: Adobe Inc.Inventors: Viswanathan Swaminathan, Sheng Wei, Srinivas R. Manapragada
-
Patent number: 11616028Abstract: Semiconductor devices having metallization structures including crack-inhibiting structures, and associated systems and methods, are disclosed herein. In one embodiment, a semiconductor device includes a metallization structure formed over a semiconductor substrate. The metallization structure can include a bond pad electrically coupled to the semiconductor substrate via one or more layers of conductive material, and an insulating material—such as a low-? dielectric material—at least partially around the conductive material. The metallization structure can further include a crack-inhibiting structure positioned beneath the bond pad between the bond pad and the semiconductor substrate. The crack-inhibiting structure can include (a) a metal lattice extending laterally between the bond pad and the semiconductor substrate and (b) barrier members extending vertically between the metal lattice and the bond pad.Type: GrantFiled: October 5, 2020Date of Patent: March 28, 2023Assignee: Micron Technology, Inc.Inventors: Shams U. Arifeen, Hyunsuk Chun, Sheng Wei Yang, Keizo Kawakita
-
Publication number: 20230086907Abstract: Semiconductor devices having metallization structures including crack-inhibiting structures, and associated systems and methods, are disclosed herein. In one embodiment, a semiconductor device includes a metallization structure formed over a semiconductor substrate. The metallization structure can include a bond pad electrically coupled to the semiconductor substrate via one or more layers of conductive material, and an insulating material—such as a low-? dielectric material—at least partially around the conductive material. The metallization structure can further include a crack-inhibiting structure positioned beneath the bond pad between the bond pad and the semiconductor substrate. The crack-inhibiting structure can include a barrier member extending vertically from the bond pad toward the semiconductor substrate and configured to inhibit crack propagation through the insulating material.Type: ApplicationFiled: August 16, 2022Publication date: March 23, 2023Inventors: Hyunsuk Chun, Sheng Wei Yang, Shams U. Arifeen
-
Patent number: 11609063Abstract: A toy gun includes a gun body, an action assembly, and a pressure diverter. The gun body includes a barrel and a gas flow conduit. The action assembly is installed on the gun body and includes a piston. The pressure diverter is received in the gun body and arranged between the barrel, the gas flow conduit, and the piston. The gas diverter includes a gas collection cavity and an inlet hole, a first outlet hole and a second outlet hole communicating to the gas collection cavity. The inlet hole is arranged corresponding to the gas flow conduit, the first outlet hole is arranged corresponding to the barrel, the second outlet hole is arranged corresponding to the piston. The cross-sectional area of the first outlet hole is greater than that of the second outlet hole.Type: GrantFiled: March 2, 2022Date of Patent: March 21, 2023Inventor: Ho-Sheng Wei
-
Patent number: 11611317Abstract: The present invention provides a circuitry applied to multiple power domains, wherein the circuitry includes a first circuit block and second circuit block, the first circuit block is powered by a first supply voltage of a first power domain, and the second circuit block is powered by a second supply voltage of a second power domain. The first circuit block includes a first amplifier and a switching circuit. The first amplifier is configured to receive an input signal to generate a processed input signal. When the second circuit block is powered by the second supply voltage, the switching circuit is configured to forward the processed input signal to the second circuit block; and when the second circuit block is not powered by the second supply voltage, the switching circuit disconnects a path between the first amplifier and the second circuit block.Type: GrantFiled: May 31, 2021Date of Patent: March 21, 2023Assignee: Realtek Semiconductor Corp.Inventors: Wei-Cheng Tang, Li-Lung Kao, Chia-Ling Chang, Sheng-Tsung Wang, Sheng-Wei Lin
-
Publication number: 20230083548Abstract: A memory circuit includes a memory array including a plurality of memory cells, each memory cell of the plurality of memory cells including an n-type channel layer including a metal oxide material, and a gate structure overlying and adjacent to the n-type channel layer, the gate structure including a conductive layer overlying a ferroelectric layer. The memory circuit is configured to apply a gate voltage to each memory cell of the plurality of memory cells in first and second write operations, the gate voltage has a positive polarity and a first magnitude in the first write operation and a negative polarity and a second magnitude greater than the first magnitude in the second write operation.Type: ApplicationFiled: November 18, 2022Publication date: March 16, 2023Inventors: Huan-Sheng WEI, Tzer-Min SHEN, Zhiqiang WU
-
Patent number: D983171Type: GrantFiled: November 16, 2022Date of Patent: April 11, 2023Inventor: Sheng Wei