Abstract: Disclosed are a polyethylene glycol conjugate drug, and a preparation method therefor and the use thereof. Specifically, the present invention relates to a polyethylene glycol conjugate drug represented by formula A or a pharmaceutically acceptable salt thereof, a method for preparing the polyethylene glycol conjugate drug or the pharmaceutically acceptable salt thereof, an intermediate for preparing the polyethylene glycol conjugate drug or the pharmaceutically acceptable salt thereof, a pharmaceutical composition comprising the polyethylene glycol conjugate drug or the pharmaceutically acceptable salt thereof, and the use of the polyethylene glycol conjugate drug or the pharmaceutically acceptable salt thereof in the preparation of a drug.

Abstract: A method of fabrication of a multi-gate semiconductor device that includes providing a fin having a plurality of a first type of epitaxial layers and a plurality of a second type of epitaxial layers. The plurality of the second type of epitaxial layers is oxidized in the source/drain region. A first portion of a first layer of the second type of epitaxial layers is removed in a channel region of the fin to form an opening between a first layer of the first type of epitaxial layer and a second layer of the first type of epitaxial layer. A portion of a gate structure is then formed in the opening.

Abstract: A device and method for generating article markup information are provided. The method for generating article markup information includes the following. Segmentation processing is performed on an article to generate a segmentation result. Name entity recognition is performed on the segmentation result to generate a first recognition result. Whether the segmentation result includes any word in an expansion list is determined. Expanded entity classification conversion is performed on the first recognition result to generate a second recognition result. The second recognition result and the segmentation result are used as markup information.

Abstract: An electronic device including a bracket and an antenna is provided. The bracket includes first, second, third, and fourth surfaces. The antenna includes a radiator. The radiator includes first, second, third, and fourth portions. The first portion is located on the first surface and includes connected first and second sections. The second portion is located on the second surface and includes third, fourth, fifth, and sixth sections. The third section, the fourth section, and the fifth sections are bent and connected to form a U shape. The third portion is located on the third surface and is connected to the second section and the fourth section. The fourth portion is located on the fourth surface and is connected to the fifth section, the sixth section, and the third portion. The radiator is adapted to resonate at a low frequency band and a first high frequency band.

Abstract: A method of forming a three-dimensional (3D) memory device includes: forming, over a substrate, a layer stack having alternating layers of a first conductive material and a first dielectric material; forming trenches extending vertically through the layer stack from an upper surface of the layer stack distal from the substrate to a lower surface of the layer stack facing the substrate; lining sidewalls and bottoms of the trenches with a memory film; forming a channel material over the memory film, the channel material including an amorphous material; filling the trenches with a second dielectric material after forming the channel material; forming memory cell isolation regions in the second dielectric material; forming source lines (SLs) and bit lines (BLs) that extend vertically in the second dielectric material on opposing sides of the memory cell isolation regions; and crystallizing first portions of the channel material after forming the SLs and BLs.

Abstract: Various embodiments of the teachings herein include an image processing system comprising: a video stream processing device configured to receive a video stream, segment the video stream into multiple frames of pictures arranged in chronological order, and distribute the multiple frames of pictures to edge computing devices in a connected edge computing device group; and a picture collecting device configured to receive pictures from the edge computing device group. The individual edge computing devices in the edge computing device group are each configured to subject the received pictures to target identification, and send the pictures marked with a region in which an identified target is located. The picture collecting device is further configured to restore in chronological order as a video stream the received pictures marked with target identification results.

Abstract: Interconnect structure packages (e.g., through silicon vias (TSV) packages, through interlayer via (TIV) packages) may be pre-manufactured as opposed to forming TIVs directly on a carrier substrate during a manufacturing process for a semiconductor die package at backend packaging facility. The interconnect structure packages may be placed onto a carrier substrate during manufacturing of a semiconductor device package, and a semiconductor die package may be placed on the carrier substrate adjacent to the interconnect structure packages. A molding compound layer may be formed around and in between the interconnect structure packages and the semiconductor die package.

Abstract: A method for performing audio enhancement with aid of timing control includes: utilizing a UE to determine a first predetermined synchronization delay and notify a first earphone of the first predetermined synchronization delay, wherein a first DSP circuit in the first earphone is arranged to determine a synchronization point according to a first time point of a first event and the first predetermined synchronization delay for the first earphone; utilizing the UE to determine a second predetermined synchronization delay and notify a second earphone of the second predetermined synchronization delay, wherein a second DSP circuit in the second earphone is arranged to determine the synchronization point according to a second time point of a second event and the second predetermined synchronization delay for the second earphone; and utilizing the UE to receive first uplink audio data from the first earphone and receive second uplink audio data from the second earphone.

Abstract: This disclosure provides systems, methods and apparatus, including computer programs encoded on computer storage media, for switching a secondary cell to a primary cell. A user equipment (UE) monitors a first radio condition of the UE for beams of a primary cell and a second radio condition for beams of one or more secondary cells configured for the UE in carrier aggregation. The UE transmits a request to configure a candidate beam of at least one candidate secondary cell as a new primary cell in response to the first radio condition not satisfying a first threshold and the second radio condition for the at least one candidate secondary cell satisfying a second threshold. A base station determines to reconfigure at least one secondary cell as the new primary cell. The base station and the UE perform a handover of the UE to the new primary cell.

Abstract: A memory circuit includes a memory array including a plurality of memory cells, each memory cell of the plurality of memory cells including an n-type channel layer including a metal oxide material, and a gate structure overlying and adjacent to the n-type channel layer, the gate structure including a conductive layer overlying a ferroelectric layer. The memory circuit is configured to apply a gate voltage to each memory cell of the plurality of memory cells in first and second write operations, the gate voltage has a positive polarity and a first magnitude in the first write operation and a negative polarity and a second magnitude greater than the first magnitude in the second write operation.

Abstract: The present invention relates to extended recombinant polypeptide (XTEN) compositions, conjugate compositions comprising XTEN and XTEN linked to cross-linkers useful for conjugation to pharmacologically active payloads, methods of making highly purified XTEN, methods of making XTEN-linker and XTEN-payload conjugates, and methods of using the XTEN-cross-linker and XTEN-payload compositions.

Abstract: A micro LED display device includes: a substrate; a plurality of micro light-emitting diodes disposed on the substrate; and a reflective layer and a black layer sequentially stacked on the substrate. The reflective layer and the black layer cover a surface of the substrate, wherein a top surface of the plurality of micro light-emitting diodes is exposed through the reflective layer and the black layer. A plurality of reflective banks and a plurality of black banks are sequentially disposed on the black layer and exposing the plurality of micro light-emitting diodes; and a color-conversion material covers the top surface of at least one of the plurality of micro light-emitting diodes. The color-conversion material is laterally disposed between the plurality of reflective banks. The reflective layer, the black layer, the plurality of reflective banks, and the plurality of black banks overlap each other in a display direction.

Abstract: A micro light-emitting diode (LED) display panel including a substrate, a first micro LED, a first light-shielding wall, a second micro LED, and a second light-shielding wall is provided. The substrate includes a plurality of pixel regions arranged in an array. The first micro LED is disposed on one of the pixel regions of the substrate. The first light-shielding wall is disposed on the substrate and located beside the first micro LED. The second micro LED is disposed on the one of the pixel regions of the substrate and located beside the first micro LED. The second light-shielding wall is disposed on the substrate and located beside the second micro LED. A light wavelength of the first micro LED is different from a light wavelength of the second micro LED. A height of the first light-shielding wall is smaller than a height of the second light-shielding wall.

Abstract: A leak check is performed on a semiconductor wafer processing tool that includes a process chamber and process gas lines, and a semiconductor wafer is processed using the semiconductor wafer processing tool if the leak check passes. Each gas line includes a mass flow controller (MFC) and normally closed valves including an upstream and downstream valves upstream and downstream of the MFC. Leak checking includes: leak checking up to the downstream valves of the gas lines with the upstream valves closed and the downstream valves of the gas lines closed; and leak checking up to the upstream valve of each the process gas line with the upstream valves of the of the process gas lines closed and with the downstream valve of the of the process gas line being leak checked open and the downstream valve of every other process gas line closed.

Abstract: A chuck vacuum line of a semiconductor processing tool includes a first portion that penetrates a sidewall of a main pumping line of the semiconductor processing tool. The chuck vacuum line includes a second portion that is substantially parallel to the sidewall of the main pumping line and to a direction of flow in the main pumping line. A size of the second portion increases between an inlet end of the second portion and an outlet end of the second portion along the direction of flow in the main pumping line.

Abstract: A semiconductor device and method of formation are provided. The semiconductor device comprises a silicide layer over a substrate, a metal plug in an opening defined by a dielectric layer over the substrate, a first metal layer between the metal plug and the dielectric layer and between the metal plug and the silicide layer, a second metal layer over the first metal layer, and an amorphous layer between the first metal layer and the second metal layer.

Abstract: Some implementations described herein include systems and techniques for fabricating a wafer-on-wafer product using a filled lateral gap between beveled regions of wafers included in a stacked-wafer assembly and along a perimeter region of the stacked-wafer assembly. The systems and techniques include a deposition tool having an electrode with a protrusion that enhances an electromagnetic field along the perimeter region of the stacked-wafer assembly during a deposition operation performed by the deposition tool. Relative to an electromagnetic field generated by a deposition tool not including the electrode with the protrusion, the enhanced electromagnetic field improves the deposition operation so that a supporting fill material may be sufficiently deposited.

Abstract: A magnetoresistive random access memory (MRAM) includes a first transistor and a second transistor on a substrate, a source line coupled to a first source/drain region of the first transistor, and a first metal interconnection coupled to a second source/drain region of the first transistor. Preferably, the first metal interconnection is extended to overlap the first transistor and the second transistor and the first metal interconnection further includes a first end coupled to the second source/drain region of the first transistor and a second end coupled to a magnetic tunneling junction (MTJ).

Abstract: A transistor includes an insulating layer, a source region, a drain region, a channel layer, a ferroelectric layer, and a gate electrode. The source region and the drain region are respectively disposed on and in physical contact with two opposite sidewalls of the insulating layer. A thickness of the source region, a thickness of the drain region, and a thickness of the insulating layer are substantially the same. The channel layer is disposed on the insulating layer, the source region, and the drain region. The ferroelectric layer is disposed over the channel layer. The gate electrode is disposed on the ferroelectric layer.

Abstract: The present disclosure provides a semiconductor structure. The semiconductor structure includes a substrate, a transistor region, a first and a second contact plug, a first metal via, a magnetic tunneling junction (MTJ) structure, and a metal interconnect. The transistor region includes a gate over the substrate, and a first and a second doped regions at least partially in the substrate. The first and the second contact plug are over the transistor region. The first and the second contact plug include a coplanar upper surface. The first metal via and the MTJ structure are over the first and the second contact plug, respectively. The first metal via is leveled with the MTJ structure. The metal interconnect is over the first metal via and the MTJ structure, and the metal interconnect includes at least two second metal vias in contact with the first metal via and the MTJ structure, respectively.