Abstract: A data protection system and a data protection method for handling an errored command are provided. The data protection system includes a master device and a slave device. The master device is configured to send command. The slave device is coupled to the master device. The save device is configured to receive the command from the master device. The master device includes a master interface. The slave device includes a slave interface. The master interface and the slave interface are electrically connected via one or plurality of bonds and/or TSVs and configured for interfacing between the master device and the slave device. The errored command represents the command having a parity or other error. The slave device is further configured to receive the errored command and to respond the errored command according to read or write operation.

Abstract: A semiconductor device with an interface includes a master device and a plurality of slave devices. The master device includes a master interface. The slave devices are stacked on the master device one after one as a three-dimension (3D) stack. Each of the slave devices includes a slave interface and a managing circuit, the master interface and the slave interfaces form the interface for passing signals in communication between the master device and the slave devices. The managing circuit of a current one of the slave devices drives a next one of the slave devices. An operation command received at the current one of the slave devices is just passed to the next one of the slave devices through the interface. A response from the current one of the slave devices is passed back to the master device through the interface.

Abstract: An interface for a semiconductor device is provided. The semiconductor device has a master device and multiple slave devices as stacked up with electric connection. The interface includes a master interface, implemented in the master device and including a master interface circuit with a master bond pattern. Further, a slave interface is implemented in each slave device and includes a slave interface circuit with a slave bond pattern to correspondingly connect to the master bond pattern. A clock route is to transmit a clock signal through the master interface and the slave interface. The master device transmits a command and a selecting slave identification through the master interface to all the slave interfaces. One of the slave devices corresponding to the selecting slave identification executes the command and responds a result back to the master device through the slave interfaces and the master interface.

Abstract: Disclosed are compositions and methods for targeted treatment of TLR9-expressing cancers. In particular, disclosed herein are molecules or conjugates containing a TLR9 targeting ligand, such as a CpG oligodeoxynucleotide, and a cytotoxic nanoparticle that targets TLR9-expressing malignant cells. Also disclosed is a pharmaceutical composition comprising a molecule disclosed herein in a pharmaceutically acceptable carrier. Also disclosed is a method for treating a TLR9-positive cancer in a subject that involves administering to the subject a therapeutically effective amount of a disclosed pharmaceutical composition.

Abstract: An array of vertical transistors comprises spaced pillars of individual vertical transistors that individually comprise an upper source/drain region, a lower source/drain region, and a channel region vertically there-between. The upper source/drain region comprises a conductor oxide material in individual of the pillars. The channel region comprises an oxide semiconductor material in the individual pillars. The lower source/drain region comprises a first conductive oxide material in the individual pillars atop and directly against a second conductive oxide material in the individual pillars. Horizontally-elongated and spaced conductor lines individually interconnect a respective multiple of the vertical transistors in a column direction. The conductor lines individually comprise the second conductive oxide material atop and directly against metal material. The first conductive oxide material, the second conductive oxide material, and the metal material comprise different compositions relative one another.

Abstract: The present invention provides a circuitry applied to multiple power domains. An amplifier of the circuitry includes an output stage and a switching circuit. The output stage includes a first transistor and a second transistor, wherein the first transistor is coupled between a supply voltage and an output terminal, the second transistor is coupled between the output terminal and a ground voltage. The switching circuit is configured to choose a body of the first transistor from the supply voltage or a reference voltage.

Abstract: A user location in a parking lot or other designated area may be identified based on sensor data, such as from one or more sensors in or around the designated area. Also within the designated area, a transport location of a transport associated with an order of the user may be identified based on image data provided by one or more cameras remote from the transport. The transport can be controlled to move from the identified transport location to the identified user location.

Abstract: The present invention provides a circuitry applied to multiple power domains, wherein the circuitry includes a first circuit block and second circuit block, the first circuit block is powered by a first supply voltage of a first power domain, and the second circuit block is powered by a second supply voltage of a second power domain. The first circuit block includes a first amplifier and a switching circuit. The first amplifier is configured to receive an input signal to generate a processed input signal. When the second circuit block is powered by the second supply voltage, the switching circuit is configured to forward the processed input signal to the second circuit block; and when the second circuit block is not powered by the second supply voltage, the switching circuit disconnects a path between the first amplifier and the second circuit block.

Abstract: A toy gun with a fixed firing pin structure mechanism includes a gun body having a barrel and a pneumatic conduit connected thereto; a switch valve installed between the barrel and the pneumatic conduit; an action assembly installed on the barrel; the action assembly having an action with a piston member and moving relative to the gun body, a restoring spring assembly supported therebetween; the restoring spring assembly driving the action toward the barrel; and a firing pin structure fixed onto the gun body and arranged between the switch valve and the piston member; the firing pin structure having a piston seat and a firing pin penetrating therein and moving relative to the switch valve; the piston member engaging/disengaging the piston seat.

Abstract: A toy gun (10) with a fixed firing pin structure mechanism includes a gun body (1) having a barrel (11) and a pneumatic conduit (12) connected thereto; a switch valve (2) installed between the barrel (11) and the pneumatic conduit (12); an action assembly (3) installed on the barrel (1); the action assembly (3) having an action (31) with a piston member (311) and moving relative to the gun body (1), a restoring spring assembly (32) supported therebetween; the restoring spring assembly (32) driving the action (31) toward the barrel (11); and a firing pin structure (4) fixed onto the gun body (1) and arranged between the switch valve (2) and the piston member (311); the firing pin structure (4) having a piston seat (41) and a firing pin (42) penetrating therein and moving relative to the switch valve (2); the piston member (311) engaging/disengaging the piston seat (41).

Abstract: Provided are a lithium ion battery, an electrode of a lithium ion battery, and an electrode material. An electrode material of the lithium ion battery includes electrode active powder and a metal thin film. The metal thin film partially or completely wraps a surface of the electrode active powder, in which the metal thin film includes silver, gold, platinum, palladium, aluminum, magnesium, zinc, tin, or an alloy of the foregoing.

Abstract: A memory circuit includes a memory array including a plurality of memory cells, each memory cell including a gate structure including a ferroelectric layer and a channel layer adjacent to the gate structure, the channel layer including a metal oxide material. A driver circuit is configured to output a gate voltage to the gate structure of a memory cell, the gate voltage having a positive polarity and a first magnitude in in a first write operation and a negative polarity and a second magnitude in in a second write operation, and to control the second magnitude to be greater than the first magnitude.

Abstract: Semiconductor device structures are provided. The semiconductor device structure includes a number of first semiconductor wires over a semiconductor substrate, and the first semiconductor wires are vertically spaced apart from each other. The semiconductor device structure includes a first gate stack partially wrapping the first semiconductor wires, and a spacer element adjacent to the first gate stack. Each of the first semiconductor wires has a first portion directly below the spacer element and a second portion directly below the first gate stack, the first portion has a first width, the second portion has a second width, and the first width is greater than the second width.

Abstract: An interface for a semiconductor device includes a master device and a plurality of slave devices. The interface includes a master interface and a slave interface. The master interface is implemented in the master device and includes a master bond pattern of master bonds arranged as a first array. The slave interface is implemented each slave device and includes a slave bond pattern of slave bonds arranged as a second array. The first array of the master bonds includes a first central row and first data rows in two parts being symmetric to the first central row. The second array of the slave bonds includes a second central row and second data rows in two parts being symmetric to the second central row. The first central row and the second central row are aligned in connection, and the first data rows are connected to the second data rows.

Abstract: A multi-gate semiconductor device having a fin element, a gate structure over the fin element, an epitaxial source/drain feature adjacent the fin element; a dielectric spacer interposing the gate structure and the epitaxial source/drain feature.

Abstract: A test kit for testing a device under test (DUT) includes a socket structure for containing the DUT. The DUT includes an antenna and radiates a RF signal. The test kit further includes a reflector having a lower surface. The RF signal emitted from the antenna of the DUT is reflected by the reflector and a reflected RF signal is received by the antenna of the DUT.

Abstract: The present invention discloses a vessel collision avoiding system and method based on Artificial Potential Field algorithm, the method comprises the following steps: (S1) obtaining a vessel information, at least one obstacle information and a target information; (S2) establishing an Artificial Potential Field (APF) by the vessel information, the at least one obstacle information and the target information, wherein the Artificial Potential Field comprises an attractive field of the target and a repulsive field of the obstacle; (S3) combining the attractive field and the repulsive field to obtain a first resultant force; (S4) Adding an external force to the Artificial Potential Field based on the vessel information or the obstacle information; (S5) combining the first resultant force and the external force to obtain a second resultant force; and (S6) the vessel sails in the direction of the second resultant force to avoid the obstacle.

Abstract: Disclosed are compositions and methods for targeted treatment of cancers, such as TLR9-expressing cancers. In particular, molecules containing a TLR9 targeting ligand, such as a CpG oligodeoxynucleotide, that target lytic peptides to TLR9-expressing malignant cells are disclosed.

Abstract: Embodiments of a system and method for low-latency content streaming are described. In various embodiments, multiple data fragments may be sequentially generated. Each data fragment may represent a distinct portion of media content generated from a live content source. Each data fragment may include multiple sub-portions. Furthermore, for each data fragment, generating that fragment may include sequentially generating each sub-portion of that fragment. Embodiments may include, responsive to receiving a request for a particular data fragment from a client during the generation of a particular sub-portion of that particular data fragment, providing the particular sub-portion to the client subsequent to that particular sub-portion being generated and prior to the generation of that particular data fragment being completed in order to reduce playback latency at the client relative to the live content source.

Abstract: Myelodysplastic syndrome (MDS) hematopoietic stem and progenitor cells (HSPC) translocate endosomal Toll-Like receptor (TLR)-9 to the plasma membrane, thereby sensitizing these clonal propagating cells to respective ligands in the microenvironment. TLR9 is the cognate receptor for RNA:DNA hybrids (R-loops) and unmethylated CpG oligonucleotides in oxidized mitochondrial DNA, the latter of which is abundant in the bone marrow microenvironment as a result of massive medullary pyroptotic cytolytic cell death. Both ligands are important danger-associated molecular patterns (DAMPs) triggering innate immune activation and chronic inflammation that contributes to MDS pathogenesis. In an effort to neutralize these DAMPs and disrupt this feed-forward inflammatory cascade, a chimeric protein was designed fusing the external epitopes of TLR9 to the Fc domain of human IgG4 to serve as a decoy receptor or ligand trap recognizing extracellular RNA:DNA hybrids (R-loops) and oxidized mitochondrial DNA.