Abstract: The present disclosure relates to an apparatus and a method for wafer cleaning. The apparatus can include a wafer holder configured to hold a wafer; a cleaning nozzle configured to dispense a cleaning fluid onto a first surface (e.g., front surface) of the wafer; and a cleaning brush configured to clean a second surface (e.g., back surface) of the wafer. Using the cleaning fluid, the cleaning brush can clean the second surface of the wafer with a scrubbing motion and ultrasonic vibration.

Abstract: An array of vertical transistors comprises spaced pillars of individual vertical transistors that individually comprise an upper source/drain region, a lower source/drain region, and a channel region vertically there-between. The upper source/drain region comprises a conductor oxide material in individual of the pillars. The channel region comprises an oxide semiconductor material in the individual pillars. The lower source/drain region comprises a first conductive oxide material in the individual pillars atop and directly against a second conductive oxide material in the individual pillars. Horizontally-elongated and spaced conductor lines individually interconnect a respective multiple of the vertical transistors in a column direction. The conductor lines individually comprise the second conductive oxide material atop and directly against metal material. The first conductive oxide material, the second conductive oxide material, and the metal material comprise different compositions relative one another.

Abstract: The present invention provides a respiratory mask comprising a nose cushion assembly. The nose cushion assembly comprises a base body and a buffering piece. The base body has a base intake portion, a base connection portion, and an air routing piece disposed at the inside of the base body and having a partitioning wall and a wall connection piece. The inside of the partitioning wall encloses an air intake zone. The wall connection piece is disposed outside the partitioning wall and connects with the base intake portion. Between the partitioning wall and the base intake portion there is defined an air outtake zone. The air intake zone is approximately at the center of the base intake portion. The buffering piece connects with the base connection portion and encloses a nose containing room, which in turn connects with the inside of the base body.

Abstract: An optical imaging lens includes five lens elements arranged from an object side to an image side in a given order along an optical axis of the optical imaging lens. The object-side surface of the second lens element has a convex portion in a vicinity of its periphery, the object -side surface of the third lens element has a convex portion in a vicinity of the optical axis, the object-side surface of the fourth lens element has a concave portion in a vicinity of its periphery, the optical imaging lens as a whole has only the five lens elements, and an effective system focal length is EFL, an air gap between the second lens element and the third lens element along the optical axis is G23, a central thickness of the third lens element along the optical axis is T3, and EFL, G23 and T3 satisfy the equation 4.89?EFL/(G23+T3)?5.88.

Abstract: A test kit for testing a device under test (DUT) includes a socket structure for containing the DUT, and a plunger assembly detachably coupled with the socket structure. The plunger assembly includes a multi-layered structure having at least an interposer substrate sandwiched by a top socket and a nest.

Abstract: A memory circuit includes a memory array including a plurality of memory cells, each memory cell including a gate structure including a ferroelectric layer and a channel layer adjacent to the gate structure, the channel layer including a metal oxide material. A driver circuit is configured to output a gate voltage to the gate structure of a memory cell, the gate voltage having a positive polarity and a first magnitude in in a first write operation and a negative polarity and a second magnitude in in a second write operation, and to control the second magnitude to be greater than the first magnitude.

Abstract: The present disclosure provides an integrated circuit (IC) structure. The IC structure includes a semiconductor substrate; an interconnection structure formed on the semiconductor substrate; and a redistribution layer (RDL) metallic feature formed on the interconnection structure. The RDL metallic feature further includes a barrier layer disposed on the interconnection structure; a diffusion layer disposed on the barrier layer, wherein the diffusion layer includes metal and oxygen; and a metallic layer disposed on the diffusion layer.

Abstract: A method of fabrication of a multi-gate semiconductor device that includes providing a fin having a plurality of a first type of epitaxial layers and a plurality of a second type of epitaxial layers. The plurality of the second type of epitaxial layers is oxidized in the source/drain region. A first portion of a first layer of the second type of epitaxial layers is removed in a channel region of the fin to form an opening between a first layer of the first type of epitaxial layer and a second layer of the first type of epitaxial layer. A portion of a gate structure is then formed in the opening.

Abstract: An array of vertical transistors comprises spaced pillars of individual vertical transistors that individually comprise an upper source/drain region, a lower source/drain region, and a channel region vertically there-between. The upper source/drain region comprises a conductor oxide material in individual of the pillars. The channel region comprises an oxide semiconductor material in the individual pillars. The lower source/drain region comprises a first conductive oxide material in the individual pillars atop and directly against a second conductive oxide material in the individual pillars. Horizontally-elongated and spaced conductor lines individually interconnect a respective multiple of the vertical transistors in a column direction. The conductor lines individually comprise the second conductive oxide material atop and directly against metal material. The first conductive oxide material, the second conductive oxide material, and the metal material comprise different compositions relative one another.

Abstract: Provided are a gate structure and a method of forming the same. The gate structure includes a gate dielectric layer, a metal layer, and a cluster layer. The metal layer is disposed over the gate dielectric layer. The cluster layer is sandwiched between the metal layer and the gate dielectric layer, wherein the cluster layer at least includes an amorphous silicon layer, an amorphous carbon layer, or an amorphous germanium layer. In addition, a semiconductor device including the gate structure is provided.

Abstract: A method of preparing polylactic acid (PLA) microsphere and polylactic-co-glycolic acid (PLGA) microsphere is provided, including the following steps. A first solution is provided, including polylactic acid or polylactic-co-glycolic acid and an organic solvent. A second solution is provided, including polyvinyl alcohol, sodium carboxymethyl cellulose and an aqueous solution. The first solution is added to the second solution and, at the same time, the second solution is agitated until polylactic acid is solidified to form a plurality of polylactic acid microspheres, or until polylactic-co-glycolic acid is solidified to form a plurality of polylactic-co-glycolic acid microspheres. The polylactic acid microspheres or polylactic-co-glycolic acid microspheres are collected.

Abstract: A semiconductor device includes a first passivation layer over a substrate. The semiconductor device further includes a post passivation interconnect (PPI) line over the first passivation layer, wherein a top-most portion of the PPI line has a first portion having a convex shape and a second portion having a concave shape. The semiconductor device further includes a second passivation layer configured to cause stress to the PPI line. The semiconductor device further includes a polymer material over the second passivation layer.

Abstract: Semiconductor devices having metallization structures including crack-inhibiting structures, and associated systems and methods, are disclosed herein. In one embodiment, a semiconductor device includes a metallization structure formed over a semiconductor substrate. The metallization structure can include a bond pad electrically coupled to the semiconductor substrate via one or more layers of conductive material, and an insulating material—such as a low-? dielectric material—at least partially around the conductive material. The metallization structure can further include a crack-inhibiting structure positioned beneath the bond pad between the bond pad and the semiconductor substrate. The crack-inhibiting structure can include a barrier member extending vertically from the bond pad toward the semiconductor substrate and configured to inhibit crack propagation through the insulating material.

Abstract: An air mattress includes a first air cell, a second air cell, a plurality of third air cells, and a body-lifting air cell. The second air cell includes a first air chamber, a second air chamber, and a structurally-weakened region. The body-lifting air cell is below the second air cell and at least one of the third air cells. The body-lifting air cell is inflated by an air source controlled by a control system. When the body-lifting air cell is inflated, a vertical distance between the top of second air cell and the bottom of air mattress is greater than a vertical distance between the top of first air cell and the bottom of air mattress. When the body-lifting air cell is inflated, the second air cell has a lower structural strength than the other air cells to have a cushioning effect against external forces.

Abstract: Provided are an air cell device and an air mattress system thereof. The air cell device includes an air cell which has therein an upper connection segment and a lower connection segment. The upper connection segment and the lower connection segment each have a curved portion whereby the air cell is partitioned to become a multilayered air cell so as to mitigate air cell bending or air cell inversion, thereby improving the lying human being's comfort.

Abstract: A teammate recommendation method for a multiplayer online game is proposed. The teammate recommendation method includes the steps of: determining one or more characteristic values for each of a plurality of players based on past game performance information of the players; dividing the players into a plurality of groups based on the characteristic values of the players; determining a Key Performance Indicator (KPI) for each of a plurality of combinations of the groups based on teammate information and team ranking of each game in the past game performance information; selecting one of the combinations, which includes a first group that the first player belongs to, based on the KPIs of the combinations; and recommending one or more second players based on the selected combination.

Abstract: An optical imaging lens includes first, second, third, fourth and fifth lens elements arranged sequentially from an object side to an image side along an optical axis. The image-side surface of the first lens element comprises a concave portion in a vicinity of the optical axis. The object-side surface of the fourth lens element comprises a concave portion in a vicinity of the optical axis. The optical imaging lens as a whole has only the five lens elements having refractive power.

Abstract: A state detector arrangement for indicating a state of use of a medicament delivery device is presented, where the state detector arrangement has an electromagnetic wave detector, and a spring, a deformation of the spring providing an indication of the state of use of the medicament delivery device, wherein the electromagnetic wave detector is configured to detect electromagnetic waves that have propagated through the spring, wherein an intensity of the electromagnetic waves detected by the electromagnetic wave detector provides a measure of the deformation of the spring.

Abstract: Provided are a gate structure and a method of forming the same. The gate structure includes a gate dielectric layer, a metal layer, and a cluster layer. The metal layer is disposed over the gate dielectric layer. The cluster layer is sandwiched between the metal layer and the gate dielectric layer, wherein the cluster layer at least includes an amorphous silicon layer, an amorphous carbon layer, or an amorphous germanium layer. In addition, a semiconductor device including the gate structure is provided.

Abstract: A positionable probe card includes a space transformer, a plurality of positioning pins, and a probe head. The space transformer includes a space transforming substrate, the space transforming substrate includes a plurality of apertures, and the positioning pins are respectively fixed in the apertures. The probe head includes a plurality of positioning holes, and the positioning pins are respectively inserted into corresponding positioning holes. In addition, a method of manufacturing a positionable probe card is also disclosed herein.