Patents by Inventor Shigeki Takahashi

Shigeki Takahashi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240101742
    Abstract: A living radical polymer that has a low molecular weight distribution and has a specific functional group at least at one end, and a resin-coated pigment has high dispersibility of a resin composition including the living radical polymer, is excellent in properties such as preservation stability, discharge stability, and color developability in a dispersed state, and is suitably used in a pigment dispersion. A living radical polymer has a specific functional group structure, the living radical polymer includes a polymerization initiator-derived specific organic compound moiety at one end or in a backbone of the living radical polymer and is obtained by reacting a radical generator having a specific functional group with at least any end, for example, an iodine end ascribable to a precursor. A living radical polymer composition includes the same; a resin-coated pigment is obtained by coating with the living radical polymer composition; and a method produces the living radical polymer.
    Type: Application
    Filed: January 21, 2022
    Publication date: March 28, 2024
    Applicants: NOF CORPORATION, NATIONAL UNIVERSITY CORPORATION YAMAGATA UNIVERSITY
    Inventors: Masumi TAKAMURA, Tatsuhiro TAKAHASHI, Shigeki TAKAHASHI, Shinri SAKAI
  • Publication number: 20240092400
    Abstract: A vehicle front recognition apparatus includes an imager that captures an image of an environment ahead of a vehicle on the road, an image analyzer that analyzes the image of the environment with artificial intelligence to segment the image areas of the image by classes to which objects captured in the image belong, and a road information acquirer that acquires high-precision map information ahead of the vehicle. The vehicle front recognition apparatus acquires dynamic information that is not included in the high-precision map information from the classes. The image analyzer includes a feeling-of-strangeness area extractor extracting a feeling-of-strangeness area using the classes from the image areas. The vehicle front recognition apparatus further includes a feeling-of-strangeness area verifier that verifies whether the vehicle can pass through the feeling-of-strangeness area and a notifier that notifies a driver when the vehicle cannot pass through the feeling-of-strangeness area.
    Type: Application
    Filed: September 7, 2023
    Publication date: March 21, 2024
    Applicant: SUBARU CORPORATION
    Inventors: Hiroki MANIWA, Reo HARADA, Hiroaki KURAMOCHI, Seiya SATO, Shigeki MUKAI, Kazuyuki TAKAHASHI, Wataru MUNEMURA
  • Publication number: 20240083422
    Abstract: A vehicle drive assist apparatus is to be applied to a vehicle. The vehicle drive assist apparatus includes an object recognizer, a risk area setter, and a risk level setter. The object recognizer is configured to recognize an object in front of the vehicle. The risk area setter is configured to, when small objects are around the object, set a risk area including the small objects. The risk level setter is configured to set a risk level for the risk area with respect to the vehicle based on distribution of height information items within the risk area.
    Type: Application
    Filed: August 28, 2023
    Publication date: March 14, 2024
    Applicant: SUBARU CORPORATION
    Inventors: Seiya SATO, Reo HARADA, Hiroaki KURAMOCHI, Hiroki MANIWA, Wataru MUNEMURA, Kazuyuki TAKAHASHI, Shigeki MUKAI
  • Publication number: 20240083416
    Abstract: A vehicle drive assist apparatus is to be applied to a vehicle. The apparatus includes an object recognizer, a risk area setter, a risk level setter, a route candidate setter, a route evaluation value calculator, and a vehicle travel route setter. The object recognizer recognizes an object in front of the vehicle. The risk area setter sets, when small objects are around the object, a risk area including the small objects. The risk level setter sets a risk level for the risk area based on a distribution state of the small objects within the risk area. The route candidate setter sets patterns of route candidates for avoiding a risk resulting from the risk area. The route evaluation value calculator calculates a route evaluation value for each of the route candidates. The vehicle travel route setter sets, as a vehicle travel route, the route candidate having an optimum route evaluation value.
    Type: Application
    Filed: August 28, 2023
    Publication date: March 14, 2024
    Applicant: SUBARU CORPORATION
    Inventors: Reo HARADA, Seiya SATO, Hiroaki KURAMOCHI, Hiroki MANIWA, Wataru MUNEMURA, Shigeki MUKAI, Kazuyuki TAKAHASHI
  • Publication number: 20240083423
    Abstract: A vehicle drive assist apparatus is to be applied to a vehicle. The vehicle drive assist apparatus includes an object recognizer, a dispersion area extractor, and a risk area setter. The object recognizer is configured to recognize an object in front of the vehicle. The dispersion area extractor is configured to extract a dispersion area where luminance values are dispersed around the recognized object. The risk area setter is configured to set, as a risk area where small objects are distributed, an area including the dispersion area.
    Type: Application
    Filed: August 28, 2023
    Publication date: March 14, 2024
    Applicant: SUBARU CORPORATION
    Inventors: Reo HARADA, Seiya SATO, Hiroaki KURAMOCHI, Hiroki MANIWA, Wataru MUNEMURA, Shigeki MUKAI, Kazuyuki TAKAHASHI
  • Publication number: 20220381081
    Abstract: A mobile body control system includes: a window open or close instruction recognition unit that recognizes an open or close instruction of a window provided to a mobile body in accordance with a voice operation or an operation of a mobile terminal performed by a passenger on the mobile body; a window control unit that executes a window open or close control for opening or closing the window, when the open or close instruction of the window is recognized; and a window operation restriction unit that executes at least one of window operation inhibition processing for inhibiting execution of the window open or close control by the window control unit in accordance with an operation of a switch provided to the mobile body, and window operation stop processing for stopping the window being operated by the window open or close control in accordance with an operation of the switch.
    Type: Application
    Filed: May 27, 2022
    Publication date: December 1, 2022
    Inventors: Mizuki Katsu, Naoki Shibata, Atsushi Sekiguchi, Shigeki Takahashi, Tomohiro Suzuki, Takamune Tsukahara, Kenichiro Kagawa, Futoshi Kobayashi, Masayuki Watarai, Makoto Ono, Katsuyasu Yamane, Koji Hashimoto, Hironori Takano
  • Patent number: 11502246
    Abstract: A magnetoresistive device includes a spin-orbit-torque (SOT) electrode layer, and a first magnetic layer, a first non-magnetic layer, and a second magnetic layer sequentially stacked over the SOT electrode layer. An interface layer is located between the SOT electrode layer and the first magnetic layer, and an etch stop layer covers a surface portion of the SOT electrode layer and is located adjacent the interface layer. The interface layer includes a metal having a spin diffusion length that is greater than a thickness of the interface layer, and the etch stop layer includes an oxide or nitride material of the metal.
    Type: Grant
    Filed: May 23, 2021
    Date of Patent: November 15, 2022
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Shigeki Takahashi
  • Publication number: 20220312191
    Abstract: A setting apparatus includes: a CPU and a memory connected to the CPU. The memory is configured to store information regarding each of a plurality of users individually using a single space. The CPU is configured to perform: identifying a user to use the space; authenticating the user identified in the identifying; setting devices provided in the space based on the information stored in the memory. The information stored in the memory includes: first information; and second information given stricter restriction than the first information. The CPU is configured to perform: the setting including performing a predetermined setting of the devices provided in the space based on the first information of the user identified in the identifying.
    Type: Application
    Filed: March 25, 2022
    Publication date: September 29, 2022
    Inventors: Yoshihiro Matsugi, Kazune Furudo, Naoki Shibata, Naoki Kikuchi, Shigeki Takahashi, Yuki Matsuura, Shogo Usui, Koji Hashimoto
  • Patent number: 11289476
    Abstract: In a semiconductor device in which an IGBT region having an IGBT element and an FWD region having an FWD element are formed to a semiconductor substrate, a plurality of carrier injection layers electrically connected with a second electrode and configuring a PN junction with a field stop layer is disposed in a cathode layer. When an impurity concentration of the field stop layer is defined as Nfs [cm?3], and a length of a shortest portion of each of the plurality of carrier injection layers along a planar direction of the semiconductor substrate is defined as L1 [?m], the plurality of carrier injection layers satisfies a relationship of L1>6.8×10?16×Nfs+20.
    Type: Grant
    Filed: March 30, 2020
    Date of Patent: March 29, 2022
    Assignee: DENSO CORPORATION
    Inventors: Koichi Murakawa, Shigeki Takahashi, Masakiyo Sumitomo
  • Publication number: 20210384417
    Abstract: A magnetoresistive device includes a spin-orbit-torque (SOT) electrode layer, and a first magnetic layer, a first non-magnetic layer, and a second magnetic layer sequentially stacked over the SOT electrode layer. An interface layer is located between the SOT electrode layer and the first magnetic layer, and an etch stop layer covers a surface portion of the SOT electrode layer and is located adjacent the interface layer. The interface layer includes a metal having a spin diffusion length that is greater than a thickness of the interface layer, and the etch stop layer includes an oxide or nitride material of the metal.
    Type: Application
    Filed: May 23, 2021
    Publication date: December 9, 2021
    Inventor: SHIGEKI TAKAHASHI
  • Patent number: 11054675
    Abstract: Provided is an optical modulator which is small in optical loss, is small in a size, and is low in required voltage and is operable to perform high-speed operation. The optical phase modulator 100 comprises a rib-type waveguide structure 110 including: a PN junction 106 which is formed of Si and is formed in a lateral direction on a substrate; and an Si1-xGex layer 108 which is constituted of at least one layer and is doped with an impurity to a p-type and is superposed on the PN junction 106 so as to be electrically connected to the PN junction 106. The rib-type waveguide structure 110 has a substantially uniform structure along a light propagation direction, and in a direction parallel with the substrate and perpendicular to the light propagation direction, a position of a junction interface 106a of the PN junction 106 is offset from a center of the Si1-xGex layer 108.
    Type: Grant
    Filed: August 24, 2018
    Date of Patent: July 6, 2021
    Assignees: PHOTONICS ELECTRONICS TECHNOLOGY RESEARCH ASSOCIATION, THE UNIVERSITY OF TOKYO
    Inventors: Junichi Fujikata, Shigeki Takahashi, Mitsuru Takenaka
  • Patent number: 11056584
    Abstract: In a semiconductor device having an active region and an inactive region, the active region includes a channel forming layer with a heterojunction structure having first and second semiconductor layers, a gate structure portion having a MOS gate electrode, a source electrode and a drain electrode disposed on the second semiconductor layer with the gate structure portion interposed therebetween, a third semiconductor layer disposed at a position away from the drain electrode between the gate structure portion and the drain electrode and not doped with an impurity, a p-type fourth semiconductor layer disposed on the third semiconductor layer, and a junction gate electrode brought into contact with the fourth semiconductor layer. The junction gate electrode is electrically connected to the source electrode to have a same potential as a potential of the source electrode, and is disposed only in the active region.
    Type: Grant
    Filed: November 25, 2019
    Date of Patent: July 6, 2021
    Assignee: DENSO CORPORATION
    Inventors: Kensuke Hata, Shinichi Hoshi, Hideo Matsuki, Youngshin Eum, Shigeki Takahashi
  • Patent number: 10996539
    Abstract: Provided is a SIS-type electro-optic modulator capable of realizing highly efficient optical coupling with a rib-type Si waveguide, improving modulation efficiency, realizing reduction of electric capacity and lead-out resistance in stacked semiconductor layers. The modulator includes a SIS junction constituted by first and second semiconductor layers having different type of conductivity and a dielectric layer interposed therebetween, wherein an electrical signal from electrodes coupled to the first and second semiconductor layers causes free carriers accumulate, deplete or invert on both sides of the dielectric layer, thereby modulating a free carrier concentration felt by an optical signal electric filed, light having a polarization component orthogonal to the width direction of the SIS junction is incident on the dielectric layer, and the width of the SIS junction is ?/neff or less (? is the wavelength of the incident light and neff is an effective refractive index of the modulator to the incident light).
    Type: Grant
    Filed: June 13, 2019
    Date of Patent: May 4, 2021
    Assignees: NEC CORPORATION, PHOTONICS ELECTRONICS TECHNOLOGY RESEARCH ASSOCIATION
    Inventors: Shigeki Takahashi, Junichi Fujikata
  • Publication number: 20210017624
    Abstract: An induction heating method for a metal strip is provided to heat a continuously conveyed metal strip using an induction heating device disposed at a first position on a pass line. The induction heating method includes a step of detecting a displacement from a predetermined datum line of a width direction center line of the metal strip at a second position on the pass line that is different from the first position, a step of computing an estimated displacement of the width direction center line of the metal strip at the first position by temporal and spatial extrapolation of the displacement based on a function expressing a time series of changes in the displacement, and a step of controlling a relative positional relationship between the induction heating device and the metal strip in a width direction of the metal strip based on the estimated displacement.
    Type: Application
    Filed: March 12, 2019
    Publication date: January 21, 2021
    Applicant: NIPPON STEEL CORPORATION
    Inventors: Yoshiaki HIROTA, Masato TAIRA, Shigeki TAKAHASHI
  • Patent number: 10840238
    Abstract: A semiconductor device has a semiconductor substrate including an IGBT region operating as an IGBT provided by an emitter layer, a base layer, a drift layer and a collector layer, and a diode region operating as a diode and provided by an anode layer, the drift layer and a cathode layer. The semiconductor substrate further includes a guard ring of a second conduction type, provided in a surface layer of the drift layer in a peripheral region surrounding a device region where the IGBT region and the diode region are adjacent to each other. The cathode layer and the guard ring are positioned such as to satisfy L/d?1.5, where L is a minimum value of a distance between the cathode layer and the guard ring as projected to a plane parallel to a surface of the semiconductor substrate, and d is a thickness of the semiconductor substrate.
    Type: Grant
    Filed: May 24, 2017
    Date of Patent: November 17, 2020
    Assignee: DENSO CORPORATION
    Inventors: Takafumi Arakawa, Shigeki Takahashi
  • Publication number: 20200301177
    Abstract: Provided is an optical modulator which is small in optical loss, is small in a size, and is low in required voltage and is operable to perform high-speed operation. The optical phase modulator 100 comprises a rib-type waveguide structure 110 including: a PN junction 106 which is formed of Si and is formed in a lateral direction on a substrate; and an Si1-xGex layer 108 which is constituted of at least one layer and is doped with an impurity to a p-type and is superposed on the PN junction 106 so as to be electrically connected to the PN junction 106. The rib-type waveguide structure 110 has a substantially uniform structure along a light propagation direction, and in a direction parallel with the substrate and perpendicular to the light propagation direction, a position of a junction interface 106a of the PN junction 106 is offset from a center of the Si1-xGex layer 108.
    Type: Application
    Filed: August 24, 2018
    Publication date: September 24, 2020
    Inventors: Junichi Fujikata, Shigeki Takahashi, Mitsuru Takenaka
  • Patent number: 10763345
    Abstract: In a semiconductor device, a boundary area is between an IGBT region and a diode region. In other words, the boundary region is at a position adjacent to the diode region. The boundary region has a lower ratio of formation of a high-concentration P-type layer than the IGBT region. Accordingly, during recovery, hole injection from the IGBT region to the diode region can be inhibited. The reduced ratio of formation of the high-concentration P-type layer in the boundary region also reduces the amount of hole injection from the high-concentration P-type layer of the boundary region. Thus, it inhibits an increase in maximum reverse current during the recovery, and also decreases the carrier density on the cathode side to inhibit an increase in tail electrical current, so that the semiconductor device reduces switching loss and is highly resistant to recovery destruction.
    Type: Grant
    Filed: April 24, 2019
    Date of Patent: September 1, 2020
    Assignee: DENSO CORPORATION
    Inventors: Koichi Murakawa, Masakiyo Sumitomo, Shigeki Takahashi
  • Patent number: 10748988
    Abstract: A semiconductor device has an element part and an outer peripheral part, and a deep layer is formed in the outer peripheral part more deeply than a base layer. When a position of the deep layer closest to the element part is defined as a boundary position, a distance between the boundary position and a position closest to the outer peripheral part in an emitter region is defined as a first distance, and a distance between the boundary position and a position of an end of a collector layer is defined as a second distance, the first distance and the second distance are adjusted such that a carrier density in the outer peripheral part is lowered based on breakdown voltage in the outer peripheral part lowered by the deep layer.
    Type: Grant
    Filed: July 8, 2019
    Date of Patent: August 18, 2020
    Assignee: DENSO CORPORATION
    Inventors: Masanori Miyata, Shigeki Takahashi, Masakiyo Sumitomo, Tomofusa Shiga
  • Publication number: 20200227406
    Abstract: In a semiconductor device in which an IGBT region having an IGBT element and an FWD region having an FWD element are formed to a semiconductor substrate, a plurality of carrier injection layers electrically connected with a second electrode and configuring a PN junction with a field stop layer is disposed in a cathode layer. When an impurity concentration of the field stop layer is defined as Nfs [cm?3], and a length of a shortest portion of each of the plurality of carrier injection layers along a planar direction of the semiconductor substrate is defined as L1 [?m], the plurality of carrier injection layers satisfies a relationship of L1>6.8×10?18×Nfs+20.
    Type: Application
    Filed: March 30, 2020
    Publication date: July 16, 2020
    Inventors: Koichi MURAKAWA, Shigeki TAKAHASHI, Masakiyo SUMITOMO
  • Publication number: 20200091332
    Abstract: In a semiconductor device having an active region and an inactive region, the active region includes a channel forming layer with a heterojunction structure having first and second semiconductor layers, a gate structure portion having a MOS gate electrode, a source electrode and a drain electrode disposed on the second semiconductor layer with the gate structure portion interposed therebetween, a third semiconductor layer disposed at a position away from the drain electrode between the gate structure portion and the drain electrode and not doped with an impurity, a p-type fourth semiconductor layer disposed on the third semiconductor layer, and a junction gate electrode brought into contact with the fourth semiconductor layer. The junction gate electrode is electrically connected to the source electrode to have a same potential as a potential of the source electrode, and is disposed only in the active region.
    Type: Application
    Filed: November 25, 2019
    Publication date: March 19, 2020
    Inventors: KENSUKE HATA, SHINICHI HOSHI, HIDEO MATSUKI, YOUNGSHIN EUM, SHIGEKI TAKAHASHI