Patents by Inventor Shigeki Takahashi

Shigeki Takahashi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20190384135
    Abstract: Provided is a SIS-type electro-optic modulator capable of realizing highly efficient optical coupling with a rib-type Si waveguide, improving modulation efficiency, realizing reduction of electric capacity and lead-out resistance in stacked semiconductor layers. The modulator includes a SIS junction constituted by first and second semiconductor layers having different type of conductivity and a dielectric layer interposed therebetween, wherein an electrical signal from electrodes coupled to the first and second semiconductor layers causes free carriers accumulate, deplete or invert on both sides of the dielectric layer, thereby modulating a free carrier concentration felt by an optical signal electric filed, light having a polarization component orthogonal to the width direction of the SIS junction is incident on the dielectric layer, and the width of the SIS junction is ?/neff or less (? is the wavelength of the incident light and neff is an effective refractive index of the modulator to the incident light).
    Type: Application
    Filed: June 13, 2019
    Publication date: December 19, 2019
    Applicants: NEC CORPORATION, PHOTONICS ELECTRONICS TECHNOLOGY RESEARCH ASSOCIATION
    Inventors: Shigeki TAKAHASHI, Junichi FUJIKATA
  • Publication number: 20190333987
    Abstract: A semiconductor device has an element part and an outer peripheral part, and a deep layer is formed in the outer peripheral part more deeply than a base layer. When a position of the deep layer closest to the element part is defined as a boundary position, a distance between the boundary position and a position closest to the outer peripheral part in an emitter region is defined as a first distance, and a distance between the boundary position and a position of an end of a collector layer is defined as a second distance, the first distance and the second distance are adjusted such that a carrier density in the outer peripheral part is lowered based on breakdown voltage in the outer peripheral part lowered by the deep layer.
    Type: Application
    Filed: July 8, 2019
    Publication date: October 31, 2019
    Inventors: Masanori MIYATA, Shigeki TAKAHASHI, Masakiyo SUMITOMO, Tomofusa SHIGA
  • Patent number: 10395809
    Abstract: Embodiments of the inventive concepts provide a flat perpendicular magnetic layer having a low saturation magnetization and a perpendicular magnetization-type tunnel magnetoresistive element using the same. The perpendicular magnetic layer is a nitrogen-poor (Mn1?xGax)Ny layer (0<x?0.5 and 0<y<0.1) formed by providing nitrogen (N) into a MnGa alloy while adjusting a nitrogen amount. The perpendicular magnetic layer can be formed flat.
    Type: Grant
    Filed: May 10, 2017
    Date of Patent: August 27, 2019
    Assignees: Samsung Electronics Co., Ltd., National Institute for Materials Science
    Inventors: Shigeki Takahashi, Yoshiaki Sonobe, Hiroaki Sukegawa, Hwachol Lee, Kazuhiro Hono, Seiji Mitani, Jun Liu
  • Patent number: 10388773
    Abstract: A semiconductor device includes: a drift layer; a base layer on the drift layer; a collector layer and a cathode layer opposite to the base layer; multiple trenches penetrating the base layer; a gate electrode in each trench; an emitter region in a surface portion of the base layer and contacting each trench; a first electrode connected to the base layer and the emitter region; and a second electrode connected to the collector layer and the cathode layer. The gate electrodes in a diode region of a semiconductor substrate are controlled independently from the gate electrodes in the IGBT region. A voltage not forming an inversion layer in the base layer is applied to the gate electrodes in the diode region.
    Type: Grant
    Filed: July 7, 2015
    Date of Patent: August 20, 2019
    Assignee: DENSO CORPORATION
    Inventors: Masakiyo Sumitomo, Shigeki Takahashi
  • Publication number: 20190252534
    Abstract: In a semiconductor device, a boundary area is between an IGBT region and a diode region. In other words, the boundary region is at a position adjacent to the diode region. The boundary region has a lower ratio of formation of a high-concentration P-type layer than the IGBT region. Accordingly, during recovery, hole injection from the IGBT region to the diode region can be inhibited. The reduced ratio of formation of the high-concentration P-type layer in the boundary region also reduces the amount of hole injection from the high-concentration P-type layer of the boundary region. Thus, it inhibits an increase in maximum reverse current during the recovery, and also decreases the carrier density on the cathode side to inhibit an increase in tail electrical current, so that the semiconductor device reduces switching loss and is highly resistant to recovery destruction.
    Type: Application
    Filed: April 24, 2019
    Publication date: August 15, 2019
    Inventors: Koichi MURAKAWA, Masakiyo SUMITOMO, Shigeki TAKAHASHI
  • Patent number: 10314363
    Abstract: Provided is an insole capable of supporting a foot in a well-balanced manner. An insole 1 for a shoe is configured to include a calcaneal anterior-part support protrusion 90 for supporting a calcaneal anterior part 12A from a sole.
    Type: Grant
    Filed: June 21, 2013
    Date of Patent: June 11, 2019
    Assignee: BMZ. Inc
    Inventors: Tsuyoshi Takahashi, Kimihiko Kanazawa, Shigeki Takahashi, Takeo Sayama, Norihisa Okumura, Shouta Kaneko, Yuichi Takata
  • Patent number: 10274757
    Abstract: An electro-optic device includes a first semiconductor layer including the rib-type waveguide, which includes a rib part and a first slab part, which extends in a first direction from the rib part; a dielectric layer, which is formed on the rib part; a second semiconductor layer, which extends in a second direction, which is opposite to the first direction, from an upper surface of the dielectric layer; a first high-concentration impurity region, which is formed in the first semiconductor layer to be in contact with the first slab part on the first direction side; and a second high-concentration impurity region, which is formed in a region of the second semiconductor layer on the second direction side. The second high-concentration impurity region is formed in a region other than a region overlapping the first semiconductor layer in a lamination direction.
    Type: Grant
    Filed: February 17, 2016
    Date of Patent: April 30, 2019
    Assignees: NEC CORPORATION, PHOTONICS ELECTRONICS TECHNOLOGY RESEARCH ASSOCIATION
    Inventors: Junichi Fujikata, Shigeki Takahashi
  • Publication number: 20190096878
    Abstract: semiconductor device has a semiconductor substrate including an IGBT region operating as an IGBT provided by an emitter layer, a base layer, a drift layer and a collector layer, and a diode region operating as a diode and provided by an anode layer, the drift layer and a cathode layer. The semiconductor substrate further includes a guard ring of a second conduction type, provided in a surface layer of the drift layer in a peripheral region surrounding a device region where the IGBT region and the diode region are adjacent to each other. The cathode layer and the guard ring are positioned such as to satisfy L/d?1.5, where L is a minimum value of a distance between the cathode layer and the guard ring as projected to a plane parallel to a surface of the semiconductor substrate, and d is a thickness of the semiconductor substrate.
    Type: Application
    Filed: May 24, 2017
    Publication date: March 28, 2019
    Inventors: Takafumi ARAKAWA, Shigeki TAKAHASHI
  • Patent number: 10224322
    Abstract: A semiconductor device includes a diode provided with: a drift layer being a first conductivity type; a cathode region being provided in a back face side of the drift layer and being the first conductivity type; a second conductivity type region provided in a surface layer part of the drift layer; multiple trenches dividing the second conductivity type region into pieces by being provided deeper than the second conductivity type region, and configuring an anode region; a gate insulation film provided in a surface of the trench; a gate electrode provided in a surface of the gate insulation film; an upper electrode electrically connected with the anode region; and a lower electrode electrically connected with the cathode region. A width between the trenches is narrowest in the drift layer is defined as a mesa width. The mesa width is set to be equal to or greater than 0.3 ?m.
    Type: Grant
    Filed: July 22, 2016
    Date of Patent: March 5, 2019
    Assignee: DENSO CORPORATION
    Inventors: Weitao Cheng, Shigeki Takahashi, Masakiyo Sumitomo
  • Patent number: 10146070
    Abstract: An optical phase modulator 100 according to an embodiment of this disclosure comprises a rib-type waveguide structure 110 comprising: a PN junction 106 comprising Si and formed in a lateral direction on a substrate; and a Si1-xGex layer 108 that is doped with a p-type impurity and comprises at least one layer laminated on the PN junction 106, so as to be electrically connected to the PN junction 106.
    Type: Grant
    Filed: February 2, 2016
    Date of Patent: December 4, 2018
    Assignee: PHOTONICS ELECTRONICS TECHNOLOGY RESEARCH ASSOCIATION
    Inventors: Junichi Fujikata, Shigeki Takahashi, Mitsuru Takenaka, Younghyun Kim
  • Publication number: 20180151558
    Abstract: A semiconductor device includes a diode provided with: a drift layer being a first conductivity type; a cathode region being provided in a back face side of the drift layer and being the first conductivity type; a second conductivity type region provided in a surface layer part of the drift layer; multiple trenches dividing the second conductivity type region into pieces by being provided deeper than the second conductivity type region, and configuring an anode region; a gate insulation film provided in a surface of the trench; a gate electrode provided in a surface of the gate insulation film; an upper electrode electrically connected with the anode region; and a lower electrode electrically connected with the cathode region. A width between the trenches is narrowest in the drift layer is defined as a mesa width. The mesa width is set to be equal to or greater than 0.3 ?m.
    Type: Application
    Filed: July 22, 2016
    Publication date: May 31, 2018
    Inventors: Weitao CHENG, Shigeki TAKAHASHI, Masakiyo SUMITOMO
  • Publication number: 20180074349
    Abstract: An electro-optic device includes a first semiconductor layer including the rib-type waveguide, which includes a rib part and a first slab part, which extends in a first direction from the rib part; a dielectric layer, which is formed on the rib part; a second semiconductor layer, which extends in a second direction, which is opposite to the first direction, from an upper surface of the dielectric layer; a first high-concentration impurity region, which is formed in the first semiconductor layer to be in contact with the first slab part on the first direction side; and a second high-concentration impurity region, which is formed in a region of the second semiconductor layer on the second direction side. The second high-concentration impurity region is formed in a region other than a region overlapping the first semiconductor layer in a lamination direction.
    Type: Application
    Filed: February 17, 2016
    Publication date: March 15, 2018
    Applicants: NEC Corporation, Photonics Electronics Technology Research Association
    Inventors: Junichi FUJIKATA, Shigeki TAKAHASHI
  • Patent number: 9897752
    Abstract: An optical end coupling type silicon optical integrated circuit is provided using an SOI substrate. This optical integrated circuit is constituted so as to connect with an external optical circuit at an end coupling part and have signal light incident to an optical circuit that includes a curved part. In the plane of the optical integrated circuit, the position of one end coupling part selected from among any thereof and the position of any multimode optical waveguide element to which a respective optical waveguide is connected via a respective curved part satisfy a positional relationship defined on the basis of a beam divergence angle [theta] of stray light.
    Type: Grant
    Filed: March 20, 2014
    Date of Patent: February 20, 2018
    Assignee: PHOTONICS ELECTRONICS TECHNOLOGY RESEARCH ASSOCIATION
    Inventors: Shigeki Takahashi, Junichi Fujikata
  • Publication number: 20180024410
    Abstract: An optical phase modulator 100 according to an embodiment of this disclosure comprises a rib-type waveguide structure 110 comprising: a PN junction 106 comprising Si and formed in a lateral direction on a substrate; and a Si1-xGex layer 108 that is doped with a p-type impurity and comprises at least one layer laminated on the PN junction 106, so as to be electrically connected to the PN junction 106.
    Type: Application
    Filed: February 2, 2016
    Publication date: January 25, 2018
    Inventors: Junichi FUJIKATA, Shigeki TAKAHASHI, Mitsuru TAKENAKA, Younghyun KIM
  • Publication number: 20170330668
    Abstract: Embodiments of the inventive concepts provide a flat perpendicular magnetic layer having a low saturation magnetization and a perpendicular magnetization-type tunnel magnetoresistive element using the same. The perpendicular magnetic layer is a nitrogen-poor (Mn1?xGax)Ny layer (0<x?0.5 and 0<y<0.1) formed by providing nitrogen (N) into a MnGa alloy while adjusting a nitrogen amount. The perpendicular magnetic layer can be formed flat.
    Type: Application
    Filed: May 10, 2017
    Publication date: November 16, 2017
    Inventors: Shigeki TAKAHASHI, Yoshiaki SONOBE, Hiroaki SUKEGAWA, Hwachol LEE, Kazuhiro HONO, Seiji MITANI, Jun LIU
  • Publication number: 20170250269
    Abstract: A semiconductor device includes: a drift layer; a base layer on the drift layer; a collector layer and a cathode layer opposite to the base layer; multiple trenches penetrating the base layer; a gate electrode in each trench; an emitter region in a surface portion of the base layer and contacting each trench; a first electrode connected to the base layer and the emitter region; and a second electrode connected to the collector layer and the cathode layer. The gate electrodes in a diode region of a semiconductor substrate are controlled independently from the gate electrodes in the IGBT region. A voltage not forming an inversion layer in the base layer is applied to the gate electrodes in the diode region.
    Type: Application
    Filed: July 7, 2015
    Publication date: August 31, 2017
    Inventors: Masakiyo SUMITOMO, Shigeki TAKAHASHI
  • Patent number: 9741846
    Abstract: A semiconductor device includes a lateral transistor having: a semiconductor substrate including a drift layer; a first impurity layer in the drift layer; a channel layer in the drift layer; a second impurity layer in the channel layer; a separation insulation film on the drift layer between the channel layer and the first impurity layer; a gate insulation film on a channel region between the second impurity layer and the drift layer connected with the separation insulation film; a gate electrode on the gate insulation film and the separation insulation film; a first electrode connected with the first impurity layer; a second electrode connected with the second impurity layer and the channel layer; and a field plate on the separation insulation film between the gate electrode and the first electrode and connected with the first electrode. The field plate is larger than the gate electrode in a current direction.
    Type: Grant
    Filed: December 17, 2014
    Date of Patent: August 22, 2017
    Assignee: DENSO CORPORATION
    Inventors: Hiroshi Kameoka, Shigeki Takahashi, Akira Yamada, Atsushi Kasahara
  • Patent number: 9721945
    Abstract: A semiconductor device includes: an IGBT section including a vertical IGBT; and a diode section arranged along the IGBT section and including a diode. The diode section includes a hole injection reduction layer having a first conductivity type and arranged in an upper layer portion of a drift layer, extending to a depth deeper than an anode region constituted by a second conductivity type region in the diode section, having an impurity concentration lower than an impurity concentration of the anode region and higher than an impurity concentration of the drift layer.
    Type: Grant
    Filed: December 16, 2014
    Date of Patent: August 1, 2017
    Assignee: DENSO CORPORATION
    Inventors: Weitao Cheng, Shigeki Takahashi
  • Patent number: 9703125
    Abstract: Provided is a silicon-based electro-optic modulator which is small in size and capable of high speed operation. A first silicon semiconductor layer (120) doped to exhibit a first type of conductivity and a second semiconductor layer (160) doped to exhibit a second type of conductivity are at least partly stacked together, and a relatively thin dielectric (150) is formed at the interface between the stacked first and second silicon semiconductor layers (120, 160). The first silicon semiconductor layer (120) has a rib waveguide shape (130) comprising a rib portion (131) and slab portions (132). A first heavily doped region (140) formed by a high concentration doping process is arranged at a location, in the first silicon semiconductor layer (120), neighboring to each of the slab portions (132). The first heavily doped region (140) has almost the same height as that of the rib portion (131) of the rib waveguide (130).
    Type: Grant
    Filed: November 28, 2013
    Date of Patent: July 11, 2017
    Assignee: NEC CORPORATION
    Inventors: Junichi Fujikata, Shigeki Takahashi
  • Patent number: 9678288
    Abstract: A low-cost optical circuit, in which influence of reflected light is reduced, is provided. According to an embodiment of the present invention, an optical circuit (200) comprises a first optical coupler (204A) having at least two outputs, and a second optical coupler (204B) coupled to at least one of the outputs of the first optical coupler (204A), and wherein the ratio of an intensity of light reflected from the first optical coupler (204A) to an intensity of light inputted to the first optical coupler is smaller than the ratio of an intensity of light reflected from the second optical coupler (204B) to an intensity of light inputted to the second optical coupler.
    Type: Grant
    Filed: July 9, 2014
    Date of Patent: June 13, 2017
    Assignee: PHOTONICS ELECTRONICS TECHNOLOGY RESEARCH ASSOCIATION
    Inventor: Shigeki Takahashi