Patents by Inventor Shigeki Takahashi

Shigeki Takahashi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20170025410
    Abstract: A semiconductor device includes: an IGBT section including a vertical IGBT; and a diode section arranged along the IGBT section and including a diode. The diode section includes a hole injection reduction layer having a first conductivity type and arranged in an upper layer portion of a drift layer, extending to a depth deeper than an anode region constituted by a second conductivity type region in the diode section, having an impurity concentration lower than an impurity concentration of the anode region and higher than an impurity concentration of the drift layer.
    Type: Application
    Filed: December 16, 2014
    Publication date: January 26, 2017
    Inventors: Weitao CHENG, Shigeki TAKAHASHI
  • Patent number: 9548818
    Abstract: An optical modulator includes an optical phase modulator which applies an operating voltage to at least one arm so as to modulate an optical phase of an optical signal transmitted via at least one arm and an optical phase adjuster which applies a voltage below the operating voltage to at least one arm so as to adjust an operating point. In the optical phase adjuster, an optical phase coarse adjuster applies a voltage below the operating voltage to at least one arm so as to change an optical phase of an optical signal by 180° or more, while an optical phase fine adjuster applies a voltage below the operating voltage to at least one arm so as to changer an optical phase of an optical signal by 90° or less. Thus, it is possible to automatically calibrate an operating point of an optical modulator with low power consumption.
    Type: Grant
    Filed: March 23, 2015
    Date of Patent: January 17, 2017
    Assignee: NEC CORPORATION
    Inventors: Junichi Fujikata, Shigeki Takahashi
  • Publication number: 20160359107
    Abstract: According to one embodiment, a method of manufacturing a magnetoresistive element, the method includes forming a first magnetic layer, forming a tunnel barrier layer on the first magnetic layer, forming a second magnetic layer on the tunnel barrier layer, forming a hard mask layer on the second magnetic layer, and patterning the second magnetic layer, the tunnel barrier layer, and the first magnetic layer, with a cluster ion beam using the hard mask layer as a mask, wherein the cluster ion beam comprises cluster ions, cluster sizes of the cluster ions are distributed, and a peak value of the distribution of the cluster sizes is 2 pieces or more and 1000 pieces or less.
    Type: Application
    Filed: August 18, 2016
    Publication date: December 8, 2016
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Yuichi OHSAWA, Junichi ITO, Shigeki TAKAHASHI, Saori KASHIWADA, Chikayoshi KAMATA
  • Publication number: 20160351708
    Abstract: A semiconductor device includes a lateral transistor having: a semiconductor substrate including a drift layer; a first impurity layer in the drift layer; a channel layer in the drift layer; a second impurity layer in the channel layer; a separation insulation film on the drift layer between the channel layer and the first impurity layer; a gate insulation film on a channel region between the second impurity layer and the drift layer connected with the separation insulation film; a gate electrode on the gate insulation film and the separation insulation film; a first electrode connected with the first impurity layer; a second electrode connected with the second impurity layer and the channel layer; and a field plate on the separation insulation film between the gate electrode and the first electrode and connected with the first electrode. The field plate is larger than the gate electrode in a current direction.
    Type: Application
    Filed: December 17, 2014
    Publication date: December 1, 2016
    Inventors: Hiroshi KAMEOKA, Shigeki TAKAHASHI, Akira YAMADA, Atsushi KASAHARA
  • Publication number: 20160291350
    Abstract: Provided is a silicon-based electro-optic modulator which is small in size and capable of high speed operation. A first silicon semiconductor layer (120) doped to exhibit a first type of conductivity and a second semiconductor layer (160) doped to exhibit a second type of conductivity are at least partly stacked together, and a relatively thin dielectric (150) is formed at the interface between the stacked first and second silicon semiconductor layers (120, 160). The first silicon semiconductor layer (120) has a rib waveguide shape (130) comprising a rib portion (131) and slab portions (132). A first heavily doped region (140) formed by a high concentration doping process is arranged at a location, in the first silicon semiconductor layer (120), neighboring to each of the slab portions (132). The first heavily doped region (140) has almost the same height as that of the rib portion (131) of the rib waveguide (130).
    Type: Application
    Filed: November 28, 2013
    Publication date: October 6, 2016
    Inventors: Junichi FUJIKATA, Shigeki TAKAHASHI
  • Patent number: 9429693
    Abstract: A rib waveguide type high-order mode filter includes a plate-like slab region 1; a projection portion 2 formed in a stripe along a waveguiding direction of light on the slab region 1; and a mesa region 4 having a bottom surface positioned at the same level as that of the bottom surface of the slab region 1 and a top surface positioned at a higher level than that of the top surface of the slab region 1, on at least one side of the slab region 1, wherein the projection portion 2, the slab region 1, and the mesa region 4 are made of the same material; and the mesa region 4 includes a doped area 4a in which an optical-absorption function is added by impurity doping into the material.
    Type: Grant
    Filed: June 18, 2013
    Date of Patent: August 30, 2016
    Assignee: NEC CORPORATION
    Inventor: Shigeki Takahashi
  • Publication number: 20160170157
    Abstract: A low-cost optical circuit, in which influence of reflected light is reduced, is provided. According to an embodiment of the present invention, an optical circuit (200) comprises a first optical coupler (204A) having at least two outputs, and a second optical coupler (204B) coupled to at least one of the outputs of the first optical coupler (204A), and wherein the ratio of an intensity of light reflected from the first optical coupler (204A) to an intensity of light inputted to the first optical coupler is smaller than the ratio of an intensity of light reflected from the second optical coupler (204B) to an intensity of light inputted to the second optical coupler.
    Type: Application
    Filed: July 9, 2014
    Publication date: June 16, 2016
    Inventor: Shigeki TAKAHASHI
  • Patent number: 9349944
    Abstract: A magnetic tunnel junction device includes: a first magnetic layer that has an easy axis vertical to a surface; a non-magnetic layer on the first magnetic layer; and a second magnetic layer that has an easy axis vertical to a surface on the non-magnetic layer, and an interface layer formed of a Heussler alloy between the non-magnetic layer and at least one of the first and second magnetic layers. The at least one of the first and second magnetic layers is formed of MnGa. A lattice constant of the interface layer parallel to a major surface thereof in a bulk state thereof is between a lattice constant of the non-magnetic layer parallel to a major surface thereof in a bulk state thereof and a lattice constant of the at least one of the first and second magnetic layers parallel to a major surface thereof in a bulk state thereof.
    Type: Grant
    Filed: December 22, 2014
    Date of Patent: May 24, 2016
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Shigeki Takahashi, Yoshiaki Sonobe, Koki Takanashi
  • Patent number: 9341868
    Abstract: In a region in which silicon semiconductor layers having first and second conductive types are stacked, a concavoconvex structure including a Si1-xGex (x=0.01 to 0.9) layer is formed on a surface of the first silicon semiconductor layer, a relatively thin dielectric is formed on the concavoconvex structure, and a silicon semiconductor layer having the second conductive type is further stacked.
    Type: Grant
    Filed: March 14, 2013
    Date of Patent: May 17, 2016
    Assignee: NEC CORPORATION
    Inventors: Junichi Fujikata, Shigeki Takahashi
  • Publication number: 20160095382
    Abstract: Provided is an insole capable of supporting afoot in a well-balanced manner. An insole 1 for a shoe is configured to include a calcaneal anterior-part support protrusion 90 for supporting a calcaneal anterior part 12A from a sole.
    Type: Application
    Filed: June 21, 2013
    Publication date: April 7, 2016
    Inventors: Tsuyoshi TAKAHASHI, Kimihiko KANAZAWA, Shigeki TAKAHASHI, Takeo SAYAMA, Norihisa OKUMURA, Shouta KANEKO, Yuichi TAKATA
  • Patent number: 9274280
    Abstract: An optical waveguide type optical terminator forms an optical waveguide structure including at least an optical absorption core (103) which is formed on a clad layer (102) and includes a portion composed of silicon in which an impurity of 1019 cm?3 or more is doped, and is used by being optically connected in series with an optical waveguide including a core (105) composed of silicon. The optical absorption core (103) is sufficient provided that, at least, an impurity of around 1019 cm?3 is doped therein. For example, its impurity concentration is sufficient provided that it falls within a range of 1019-1020 cm?3. The existence of this impurity causes absorption of light in the optical absorption core (103).
    Type: Grant
    Filed: May 10, 2012
    Date of Patent: March 1, 2016
    Assignee: NEC CORPORATION
    Inventors: Jun Ushida, Shigeru Nakamura, Shigeki Takahashi
  • Publication number: 20160041338
    Abstract: An optical end coupling type silicon optical integrated circuit is provided using an SOI substrate. This optical integrated circuit is constituted so as to connect with an external optical circuit at an end coupling part and have signal light incident to an optical circuit that includes a curved part. In the plane of the optical integrated circuit, the position of one end coupling part selected from among any thereof and the position of any multimode optical waveguide element to which a respective optical waveguide is connected via a respective curved part satisfy a positional relationship defined on the basis of a beam divergence angle [theta] of stray light.
    Type: Application
    Filed: March 20, 2014
    Publication date: February 11, 2016
    Inventors: Shigeki Takahashi, Junichi Fujikata
  • Patent number: 9244295
    Abstract: An optical modulator includes a plurality of electrode pads arranged in a zigzag alignment; two arms which are partially bent to circumvent the electrode pads so as to carry out optical phase modulation at various parts based on voltages input via the electrode pads; an optical branch structure branching the arms; and an optical coupling structure aggregating the arms together. Each arm is made of a silicon-base electro-optic element including a substrate; a first conductive semiconductor layer having a rib waveguide structure; a dielectric layer deposited on the rib waveguide structure; and a second conductive semiconductor layer deposited on the dielectric layer. The first conductive semiconductor layer is connected to first electrode wires via first contacts, while the second conductive semiconductor layer is connected to second electrode wires via second contacts. Thus, it is possible to miniaturize the optical modulator which can operate at a low voltage.
    Type: Grant
    Filed: March 23, 2015
    Date of Patent: January 26, 2016
    Assignee: NEC CORPORATION
    Inventors: Junichi Fujikata, Shigeki Takahashi
  • Patent number: 9240445
    Abstract: A lateral semiconductor device includes a semiconductor layer, an insulating layer, and a resistive field plate. The semiconductor layer includes a first semiconductor region and a second semiconductor region at a surface portion, and the second semiconductor region makes a circuit around the first semiconductor region. The insulating layer is formed on a surface of the semiconductor layer and is disposed between the first and second semiconductor regions. The resistive field plate is formed on a surface of the insulating layer. Between the first and second semiconductor regions, a first section and a second section are adjacent to each other along a circumferential direction around the first semiconductor region. The resistive field plate includes first and second resistive field plate sections respectively formed in the first and second sections, and the first and second resistive field plate sections are separated from each other.
    Type: Grant
    Filed: May 10, 2012
    Date of Patent: January 19, 2016
    Assignee: DENSO CORPORATION
    Inventors: Takashi Suzuki, Norihito Tokura, Satoshi Shiraki, Shigeki Takahashi, Youichi Ashida, Akira Yamada
  • Patent number: 9224944
    Abstract: A magnetic memory according to an embodiment includes: at least one memory cell comprising a magnetoresistive element as a memory element, and first and second electrodes that energize the magnetoresistive element. The magnetoresistive element includes: a first magnetic layer having a variable magnetization direction perpendicular to a film plane; a tunnel barrier layer on the first magnetic layer; and a second magnetic layer on the tunnel barrier layer, and having a fixed magnetization direction perpendicular to the film plane. The first magnetic layer including: a first region; and a second region outside the first region so as to surround the first region, and having a smaller perpendicular magnetic anisotropy energy than that of the first region. The second magnetic layer including: a third region; and a fourth region outside the third region, and having a smaller perpendicular magnetic anisotropy energy than that of the third region.
    Type: Grant
    Filed: March 24, 2014
    Date of Patent: December 29, 2015
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Shigeki Takahashi, Yuichi Ohsawa, Junichi Ito, Chikayoshi Kamata, Saori Kashiwada, Minoru Amano, Hiroaki Yoda
  • Patent number: 9214536
    Abstract: A lateral insulated gate bipolar transistor includes a semiconductor substrate including a drift layer, a collector region, a channel layer, an emitter region, a gate insulating layer, a gate electrode, a collector electrode, an emitter electrode, and a barrier layer. The barrier layer is disposed along either side of the collector region and is located to a depth deeper than a bottom of the channel layer. The barrier layer has an impurity concentration that is higher than an impurity concentration of the drift layer. The barrier layer has a first end close to the collector region and a second end far from the collector region. The first end is located between the channel layer and the collector region, and the second end is located on the bottom of the channel layer.
    Type: Grant
    Filed: November 12, 2013
    Date of Patent: December 15, 2015
    Assignee: DENSO CORPORATION
    Inventors: Shigeki Takahashi, Norihito Tokura, Satoshi Shiraki, Youichi Ashida, Akio Nakagawa
  • Patent number: 9201196
    Abstract: A high-order mode filter includes a slab region, a band-shaped projection elongated in an optical waveguide direction, a first optical waveguide including a disturbance element and a second optical waveguide. The disturbance element is formed by doping impurities into the slab region, thus indicating a lower refractive index than the slab region. Both the first optical waveguide and the second optical waveguide are alternately arranged. The first optical waveguide may include a disturbance element positioned close to the projection, while the second optical waveguide may include a disturbance element distanced from the projection in the slab region. The high-order mode filter causes a large high-order mode loss due to interference between a removable high-order mode and an intentional high-order mode at the connecting face between the first optical waveguide and the second optical waveguide, thus reducing reflected light and stray light.
    Type: Grant
    Filed: November 29, 2012
    Date of Patent: December 1, 2015
    Assignee: NEC CORPORATION
    Inventor: Shigeki Takahashi
  • Patent number: 9151892
    Abstract: In order to provide a spot size converter and a method for making the same which enable the optical connection with low loss and are able to reduce the excess loss for the position misalignment in mounting, a spot size converter according to an exemplary aspect of the present invention includes: a substrate on which an optical waveguide including a first core is laminated and which includes a notch; a core reducing part which is formed so that a cross-section area of the first core may gradually decrease toward an end part of the first core in the direction of light propagation; a second core which surrounds the core reducing part and is made of a material whose refractive index is smaller than that of the first core; a peripheral clad which surrounds the second core and is made of a material whose refractive index is smaller than that of the second core; and a lower clad which is formed in a lower part of the second core and includes the peripheral clad; wherein the lower clad is formed in the notch.
    Type: Grant
    Filed: February 1, 2012
    Date of Patent: October 6, 2015
    Assignee: NEC CORPORATION
    Inventors: Shigeki Takahashi, Shigeru Nakamura, Masashige Ishizaka, Nobuhide Fujioka
  • Publication number: 20150280832
    Abstract: An optical modulator includes an optical phase modulator which applies an operating voltage to at least one arm so as to modulate an optical phase of an optical signal transmitted via at least one arm and an optical phase adjuster which applies a voltage below the operating voltage to at least one arm so as to adjust an operating point. In the optical phase adjuster, an optical phase coarse adjuster applies a voltage below the operating voltage to at least one arm so as to change an optical phase of an optical signal by 180° or more, while an optical phase fine adjuster applies a voltage below the operating voltage to at least one arm so as to changer an optical phase of an optical signal by 90° or less. Thus, it is possible to automatically calibrate an operating point of an optical modulator with low power consumption.
    Type: Application
    Filed: March 23, 2015
    Publication date: October 1, 2015
    Inventors: Junichi FUJIKATA, Shigeki TAKAHASHI
  • Publication number: 20150277159
    Abstract: An optical modulator includes a plurality of electrode pads arranged in a zigzag alignment; two arms which are partially bent to circumvent the electrode pads so as to carry out optical phase modulation at various parts based on voltages input via the electrode pads; an optical branch structure branching the arms; and an optical coupling structure aggregating the arms together. Each arm is made of a silicon-base electro-optic element including a substrate; a first conductive semiconductor layer having a rib waveguide structure; a dielectric layer deposited on the rib waveguide structure; and a second conductive semiconductor layer deposited on the dielectric layer. The first conductive semiconductor layer is connected to first electrode wires via first contacts, while the second conductive semiconductor layer is connected to second electrode wires via second contacts. Thus, it is possible to miniaturize the optical modulator which can operate at a low voltage.
    Type: Application
    Filed: March 23, 2015
    Publication date: October 1, 2015
    Inventors: Junichi FUJIKATA, Shigeki TAKAHASHI