Patents by Inventor Shin Hashimoto

Shin Hashimoto has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8148751
    Abstract: A group III nitride semiconductor device and a group III nitride semiconductor wafer are provided. The group III nitride semiconductor device has a channel layer comprising group III nitride-based semiconductor containing Al. The group III nitride semiconductor device can enhance the mobility of the two-dimensional electron gas and improve current characteristics. The group III nitride semiconductor wafer is used to make the group III nitride semiconductor device. The group III nitride semiconductor wafer comprises a substrate made of AlXGa1-XN (0<X?1), a first AlGaN layer made of group III nitride-based semiconductor containing Al and disposed on the substrate, and a second AlGaN layer made of group III nitride-based semiconductor having a bandgap greater than the first AlGaN layer and disposed thereon. The full width at half maximum values of X-ray rocking curves for (0002) and (10-12) planes of the first AlGaN layer are less than 1000 arcseconds.
    Type: Grant
    Filed: March 26, 2010
    Date of Patent: April 3, 2012
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventors: Shin Hashimoto, Tatsuya Tanabe, Katsushi Akita, Hideaki Nakahata, Hiroshi Amano
  • Publication number: 20120070929
    Abstract: Provided is a method for fabricating a wafer product including an active layer grown on a gallium oxide substrate and allowing an improvement in emission intensity. In step S105, a buffer layer 13 comprised of a Group III nitride such as GaN, AlGaN, or AlN is grown at 600 Celsius degrees on a primary surface 11a of a gallium oxide substrate 11. After the growth of the buffer layer 13, while supplying a gas G2, which contains hydrogen and nitrogen, into a growth reactor 10, the gallium oxide substrate 11 and the buffer layer 13 are exposed to an atmosphere in the growth reactor 11 at 1050 Celsius degrees. A Group III nitride semiconductor layer 15 is grown on the modified buffer layer. The modified buffer layer includes, for example, voids. The Group III nitride semiconductor layer 15 can be comprised of GaN and AlGaN. When the Group III nitride semiconductor layer 15 is formed of these materials, excellent crystal quality is obtained on the modified buffer layer 14.
    Type: Application
    Filed: March 1, 2010
    Publication date: March 22, 2012
    Applicants: KOHA Co., Ltd., Sumitomo Electric Industries, Ltd.
    Inventors: Shin Hashimoto, Katsushi Akita, Kensaku Motoki, Shinsuke Fujiwara, Hideaki Nakahata
  • Publication number: 20120006263
    Abstract: When a film is to be deposited on a semiconductor substrate or the like in a heating ambient, the semiconductor substrate is caused to warp (curve) to a considerable extent merely due to an increased temperature. The warpage leads to problems such as degradation of the homogeneity of the quality of the film deposited on the substrate and a high possibility of generation of a crack in the substrate. Accordingly, a film deposition apparatus of the present invention heats the substrate both from above and from below a main surface of the substrate so that a temperature gradient (temperature difference) between the upper side and the lower side of the main surface is reduced and the warpage of the substrate is suppressed. More preferably a measurement unit for measuring the curvature or warpage of the substrate is included.
    Type: Application
    Filed: August 6, 2009
    Publication date: January 12, 2012
    Applicant: SUMITOMO ELECTRIC INDUSTRIES, LTD.
    Inventors: Shin Hashimoto, Tatsuya Tanabe
  • Publication number: 20120003770
    Abstract: A method for forming an epitaxial wafer is provided as one enabling growth of a gallium nitride based semiconductor with good crystal quality on a gallium oxide region. In step S107, an AlN buffer layer 13 is grown. In step S108, at a time t5, a source gas G1 containing hydrogen, trimethylaluminum, and ammonia, in addition to nitrogen, is supplied into a growth reactor 10 to grow the AlN buffer layer 13 on a primary surface 11a. The AlN buffer layer 13 is so called a low-temperature buffer layer. After a start of film formation of the buffer layer 13, in step S109 supply of hydrogen (H2) is started at a time t6. At the time t6, H2, N2, TMA, and NH3 are supplied into the growth reactor 10. A supply amount of hydrogen is increased between times t6 and t7, and at the time t7 the increase of hydrogen is terminated to supply a constant amount of hydrogen. At the time t7, H2, TMA, and NH3 are supplied into the growth reactor 10.
    Type: Application
    Filed: February 10, 2010
    Publication date: January 5, 2012
    Applicants: KOHA CO., LTD., SUMITOMO ELECTRIC INDUSTRIES, LTD.
    Inventors: Shin Hashimoto, Katsushi Akita, Kensaku Motoki, Hideaki Nakahata, Shinsuke Fujiwara
  • Publication number: 20110315998
    Abstract: A gallium nitride based semiconductor device is provided which includes a gallium nitride based semiconductor film with a flat c-plane surface provided on a gallium oxide wafer. A light emitting diode LED includes a gallium oxide support base 32 having a primary surface 32a of monoclinic gallium oxide, and a laminate structure 33 of Group III nitride. A semiconductor mesa of the laminate structure 33 includes a low-temperature GaN buffer layer 35, an n-type GaN layer 37, an active layer 39 of a quantum well structure, and a p-type gallium nitride based semiconductor layer 37. The p-type gallium nitride based semiconductor layer 37 includes, for example, a p-type AlGaN electron block layer and a p-type GaN contact layer. The primary surface 32a of the gallium oxide support base 32 is inclined at an angle of not less than 2 degrees and not more than 4 degrees relative to a (100) plane of monoclinic gallium oxide.
    Type: Application
    Filed: February 4, 2010
    Publication date: December 29, 2011
    Applicants: KOHA CO., LTD., SUMITOMO ELECTRIC INDUSTRIES, LTD.
    Inventors: Shin Hashimoto, Katsushi Akita, Shinsuke Fujiwara, Hideaki Nakahata, Kensaku Motoki
  • Patent number: 8076736
    Abstract: A semiconductor device according to the present invention comprises a silicon carbide semiconductor substrate (1) including a silicon carbide layer (2); a high-concentration impurity region (4) provided in the silicon carbide layer (2); an ohmic electrode (9) electrically connected with the high-concentration impurity region (4); a channel region electrically connected with the high-concentration impurity region; a gate insulating layer (14) provided on the channel region; and a gate electrode (7) provided on the gate insulating layer (14). The ohmic electrode (9) contains an alloy of titanium, silicon and carbon, and the gate electrode (7) contains titanium silicide.
    Type: Grant
    Filed: February 12, 2008
    Date of Patent: December 13, 2011
    Assignee: Panasonic Corporation
    Inventors: Masashi Hayashi, Shin Hashimoto
  • Publication number: 20110278647
    Abstract: A III-nitride semiconductor electronic device comprises a semiconductor laminate provided on a primary surface of a substrate, a first electrode in contact with the semiconductor laminate, and a second electrode. The semiconductor laminate includes a channel layer and a barrier layer making a junction with the channel layer. The channel layer comprises first III-nitride semiconductor containing aluminum as a Group III constituent element, and the barrier layer comprises second III-nitride semiconductor containing aluminum as a Group III constituent element. The semiconductor laminate including first, second and third regions arranged along the primary surface, and the third region is located between the first region and the second region. The barrier layer includes first to third portions included in the first to third regions, respectively.
    Type: Application
    Filed: March 1, 2011
    Publication date: November 17, 2011
    Applicant: SUMITOMO ELECTRIC INDUSTRIES, LTD.
    Inventors: Shin HASHIMOTO, Katsushi AKITA, Yoshiyuki YAMAMOTO, Masaaki KUZUHARA, Norimasa YAFUNE
  • Patent number: 7981817
    Abstract: A production method for a semiconductor device includes providing a semiconductor substrate having semiconductor layer of a first conductivity type formed on a surface thereof; forming a first mask so as to cover a predetermined region of the semiconductor layer; (c) forming a well region of a second conductivity type by implanting impurity ions of the second conductivity type into the semiconductor layer having the first mask formed thereon; reducing the thickness of the first mask by removing a portion of the first mask; forming a second mask covering a portion of the well region by using photolithography; and forming a source region of the first conductivity type by implanting impurity ions of the first conductivity type into the semiconductor layer having the first mask with the reduced thickness and the second mask formed thereon.
    Type: Grant
    Filed: August 31, 2007
    Date of Patent: July 19, 2011
    Assignee: Panasonic Corporation
    Inventors: Koichi Hashimoto, Shin Hashimoto, Kyoko Egashira
  • Patent number: 7943964
    Abstract: An AlxGayIn1-x-yN crystal substrate of the present invention has a main plane having an area of at least 10 cm2. The main plane has an outer region located within 5 mm from an outer periphery of the main plane, and an inner region corresponding to a region other than the outer region. The inner region has a total dislocation density of at least 1×102 cm?2 and at most 1×106 cm?2. It is thereby possible to provide an AlxGayIn1-x-yN crystal substrate having a large size and a suitable dislocation density for serving as a substrate for a semiconductor device, a semiconductor device including the AlxGayIn1-x-yN crystal substrate, and a method of manufacturing the same.
    Type: Grant
    Filed: October 16, 2006
    Date of Patent: May 17, 2011
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventors: Shinsuke Fujiwara, Tomoki Uemura, Takuji Okahisa, Koji Uematsu, Manabu Okui, Muneyuki Nishioka, Shin Hashimoto
  • Publication number: 20110097880
    Abstract: Provided is a film deposition method capable of improving the crystal characteristic near an interface according to the lattice constant of a material that will constitute a thin film to be deposited. Specifically, a substrate is curved relative to the direction along one main surface on which the thin film is to be deposited, according to the lattice constant the material that will constitute the thin film to be deposited and the lattice constant of a material constituting the one main surface. The thin film is deposited on the one main surface of the substrate with the substrate curved.
    Type: Application
    Filed: June 25, 2009
    Publication date: April 28, 2011
    Applicant: SUMITOMO ELECTRIC INDUSTRIES, LTD.
    Inventors: Shin Hashimoto, Tatsuya Tanabe
  • Publication number: 20110049573
    Abstract: A group III nitride semiconductor device and a group III nitride semiconductor wafer are provided. The group III nitride semiconductor device has a channel layer comprising group III nitride-based semiconductor containing Al. The group III nitride semiconductor device can enhance the mobility of the two-dimensional electron gas and improve current characteristics. The group III nitride semiconductor wafer is used to make the group III nitride semiconductor device. The group III nitride semiconductor wafer comprises a substrate made of AlXGa1?XN (0<X?1), a first AlGaN layer made of group III nitride-based semiconductor containing Al and disposed on the substrate, and a second AlGaN layer made of group III nitride-based semiconductor having a bandgap greater than the first AlGaN layer and disposed thereon. The full width at half maximum values of X-ray rocking curves for (0002) and (10-12) planes of the first AlGaN layer are less than 1000 arcseconds.
    Type: Application
    Filed: March 26, 2010
    Publication date: March 3, 2011
    Applicant: SUMITOMO ELECTRIC INDUSTRIES, LTD.
    Inventors: Shin HASHIMOTO, Tatsuya TANABE, Katsushi AKITA, Hideaki NAKAHATA, Hiroshi AMANO
  • Patent number: 7884393
    Abstract: Affords high electron mobility transistors having a high-purity channel layer and a high-resistance buffer layer. A high electron mobility transistor (11) is provided with a supporting substrate (13) composed of gallium nitride, a buffer layer (15) composed of a first gallium nitride semiconductor, a channel layer (17) composed of a second gallium nitride semiconductor, a semiconductor layer (19) composed of a third gallium nitride semiconductor, and electrode structures (a gate electrode (21), a source electrode (23) and a drain electrode (25) for the transistor (11). The band gap of the third gallium nitride semiconductor is broader than that of the second gallium nitride semiconductor. The carbon concentration NC1 of the first gallium nitride semiconductor is 4×1017 cm?3 or more. The carbon concentration NC2 of the second gallium nitride semiconductor is less than 4×1016 cm?3.
    Type: Grant
    Filed: May 25, 2010
    Date of Patent: February 8, 2011
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventors: Shin Hashimoto, Makoto Kiyama, Takashi Sakurada, Tatsuya Tanabe, Kouhei Miura, Tomihito Miyazaki
  • Patent number: 7872285
    Abstract: Affords epitaxial substrates for vertical gallium nitride semiconductor devices that have a structure in which a gallium nitride film of n-type having a desired low carrier concentration can be provided on a gallium nitride substrate of n type. A gallium nitride epitaxial film (65) is provided on a gallium nitride substrate (63). A layer region (67) is provided in the gallium nitride substrate (63) and the gallium nitride epitaxial film (65). An interface between the gallium nitride substrate (43) and the gallium nitride epitaxial film (65) is positioned in the layer region (67). In the layer region (67), a peak value of donor impurity along an axis from the gallium nitride substrate (63) to the gallium nitride epitaxial film (65) is 1×1018 cm?3 or more. The donor impurity is at least either silicon or germanium.
    Type: Grant
    Filed: March 1, 2006
    Date of Patent: January 18, 2011
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventors: Shin Hashimoto, Makoto Kiyama, Tatsuya Tanabe, Kouhei Miura, Takashi Sakurada
  • Patent number: 7848231
    Abstract: A packet communication network is connected between a first external network and a second external network. The packet communication network includes a classifier, a parallel network that includes a plurality of physically or logically independent networks, and a multiplexing router. The classifier classifies a packet input from the first external network to one of the networks in the parallel network. Each of the networks in the parallel network transmits the packet to the multiplexing router. The multiplexing router multiplexes a packet received from the networks in the parallel network and outputs the multiplexed packet to the second external network.
    Type: Grant
    Filed: October 25, 2005
    Date of Patent: December 7, 2010
    Assignee: Nippon Telegraph and Telephone Corporation
    Inventors: Kazuhiro Hayakawa, Satoru Yoshida, Makoto Fukuda, Nobuo Shigeta, Kazuhiko Ogawa, Shin Hashimoto
  • Patent number: 7808077
    Abstract: A semiconductor device is composed of: an interconnect made of a first conductive film and a second conductive film that are stacked in sequence from the interconnect underside on an insulating film formed on a substrate; and a capacitor composed of a lower capacitor electrode made of the first conductive film, a dielectric film formed on the lower capacitor electrode, and an upper capacitor electrode made of the second conductive film and formed on the dielectric film.
    Type: Grant
    Filed: August 4, 2008
    Date of Patent: October 5, 2010
    Assignee: Panasonic Corporation
    Inventors: Kyoko Egashira, Shin Hashimoto
  • Publication number: 20100230687
    Abstract: In a group III nitride hetero junction transistor 11a, a second AlY1InY2Ga1-Y1-Y2N layer 15 forms a hetero junction 21 with a first AlX1InX2Ga1-X1-X2N layer 13a. A first electrode 17 forms a Schottky junction with the first AlX1InX2Ga1-X1-X2N layer 13a. The first AlX1InX2Ga1-X1-X2N layer 13a and the second AlY1InY2Ga1-Y1-Y2N layer 15 are provided over a substrate 23. The electrodes 17a, 18a, and 19a include a source electrode, a gate electrode, and a drain electrode, respectively. The carbon concentration NC13 in the first AlX1InX2Ga1-X1-X2N layer 13a is less than 1×1017 cm?3. The dislocation density D in the second AlY1InY2Ga1-Y1-Y2N layer 15 is 1×108 cm?2. The hetero junction 21 generates a two-dimensional electron gas layer 25. These provide a low-loss gallium nitride based electronic device.
    Type: Application
    Filed: October 28, 2008
    Publication date: September 16, 2010
    Applicant: SUMITOMO ELECTRIC INDUSTRIES, LTD.
    Inventors: Shin Hashimoto, Tatsuya Tanabe
  • Publication number: 20100230723
    Abstract: Affords high electron mobility transistors having a high-purity channel layer and a high-resistance buffer layer. A high electron mobility transistor (11) is provided with a supporting substrate (13) composed of gallium nitride, a buffer layer (15) composed of a first gallium nitride semiconductor, a channel layer (17) composed of a second gallium nitride semiconductor, a semiconductor layer (19) composed of a third gallium nitride semiconductor, and electrode structures (a gate electrode (21), a source electrode (23) and a drain electrode (25)) for the transistor (11). The band gap of the third gallium nitride semiconductor is broader than that of the second gallium nitride semiconductor. The carbon concentration NC1 of the first gallium nitride semiconductor is 4×1017 cm?3 or more. The carbon concentration NC2 of the second gallium nitride semiconductor is less than 4×1016 cm?3.
    Type: Application
    Filed: May 25, 2010
    Publication date: September 16, 2010
    Applicant: SUMITOMO ELECTRIC INDUSTRIES, LTD.
    Inventors: Shin Hashimoto, Makoto Kiyama, Takashi Sakurada, Tatsuya Tanabe, Kouhei Miura, Tomihito Miyazaki
  • Patent number: 7749828
    Abstract: Affords high electron mobility transistors having a high-purity channel layer and a high-resistance buffer layer. A high electron mobility transistor 11 is provided with a supporting substrate 13 composed of gallium nitride, a buffer layer 15 composed of a first gallium nitride semiconductor, a channel layer 17 composed of a second gallium nitride semiconductor, a semiconductor layer 19 composed of a third gallium nitride semiconductor, and electrode structures (a gate electrode 21, a source electrode 23 and a drain electrode 25) for the transistor 11. The band gap of the third gallium nitride semiconductor is broader than that of the second gallium nitride semiconductor. The carbon concentration NC1 of the first gallium nitride semiconductor is 4×1017 cm?3 or more. The carbon concentration NC2 of the second gallium nitride semiconductor is less than 4×1016 cm?3.
    Type: Grant
    Filed: March 3, 2006
    Date of Patent: July 6, 2010
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventors: Shin Hashimoto, Makoto Kiyama, Takashi Sakurada, Tatsuya Tanabe, Kouhei Miura, Tomihito Miyazaki
  • Patent number: 7741207
    Abstract: A semiconductor device comprises a first insulating film formed on a semiconductor substrate, a first metal pattern formed on the first insulating film, a second insulating film formed on the first metal pattern, a second metal pattern formed on the second insulating film, and a third metal pattern formed in the second insulating film and connecting between the first metal pattern and the second metal pattern. The third metal pattern is a single continuous structure, and the principal orientation axes of crystals of a metal constituting the third metal pattern are parallel to the principal surface of the semiconductor substrate.
    Type: Grant
    Filed: November 14, 2007
    Date of Patent: June 22, 2010
    Assignee: Panasonic Corporation
    Inventors: Shin Hashimoto, Tadaaki Mimura
  • Publication number: 20100048004
    Abstract: A production method for a semiconductor device includes the steps of: (a) providing a semiconductor substrate having a semiconductor layer 2 of a first conductivity type formed on a surface thereof; (b) forming a first mask 30 so as to cover a predetermined region of the semiconductor layer 2; (c) forming a well region 6 of a second conductivity type by implanting impurity ions of the second conductivity type into the semiconductor layer 2 having the first mask 30 formed thereon; (d) reducing the thickness t1 of the first mask 30 by removing a portion of the first mask 30; (e) forming a second mask 34 covering a portion of the well region 6 by using photolithography; and (f) forming a source region 8 of the first conductivity type by implanting impurity ions of the first conductivity type into the semiconductor layer 2 having the first mask 30? with the reduced thickness and the second mask 34 formed thereon.
    Type: Application
    Filed: August 31, 2007
    Publication date: February 25, 2010
    Inventors: Koichi Hashimoto, Shin Hashimoto, Kyoko Egashira