Patents by Inventor Shin Hashimoto

Shin Hashimoto has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 5945834
    Abstract: A retainer board, holding a semiconductor wafer having a plurality of integrated circuit terminals for testing a semiconductor chip, is provided in confronting relation to a probe sheet having a plurality of probe terminals electrically connected to their corresponding integrated circuit terminals. An insulating substrate, having wiring electrically connected to the plural probe terminals, is provided on the probe sheet in opposed relation to the retainer board. An elastic member is interposed between the probe sheet and the insulating substrate. The retainer board and the probe sheet are brought into so closer relationship that each integrated circuit terminal of the semiconductor wafer held by the retainer board is electrically connected to its corresponding probe terminal of the probe sheet.
    Type: Grant
    Filed: February 29, 1996
    Date of Patent: August 31, 1999
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Yoshirou Nakata, Toshio Yamada, Atsushi Fujiwara, Isao Miyanaga, Shin Hashimoto, Yukiharu Uraoka, Yasushi Okuda, Kenzou Hatada
  • Patent number: 5892368
    Abstract: A 12.5-MHz signal is applied from outside a semiconductor integrated circuit (SIC) device to a signal input terminal of that SIC device. A frequency multiplying circuit is fed that 12.5-MHz signal from the input terminal, and delivers a reference signal whose frequency is a multiple of the frequency of the signal received (i.e., 100 MHz), to a semiconductor memory and to a self-test circuit. The self-test circuit provides a test signal in synchronism with that 100-MHz reference signal to the semiconductor memory for testing for the presence or absence of a failure. All elements of the semiconductor memory are tested by the self-test circuit for a failure. If the self-test circuit finds a semiconductor memory element that fails to work properly, it provides a signal indicative of such failure to a failure counting circuit. This failure counting circuit counts the number of times the self-test circuit provides such a signal.
    Type: Grant
    Filed: November 4, 1996
    Date of Patent: April 6, 1999
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Yoshiro Nakata, Shin Hashimoto, Isao Miyanaga
  • Patent number: 5825193
    Abstract: A semiconductor integrated circuit apparatus having a plurality of semiconductor integrated circuit devices, each of the plurality of semiconductor devices including a semiconductor integrated circuit formed on a semiconductor substrate, a reference voltage input terminal formed on the semiconductor substrate which is operative for receiving a reference voltage input from outside of the semiconductor substrate, and a burn-in voltage control circuit formed on the semiconductor substrate operative for receiving the reference voltage which is output from the reference voltage input terminal. The burn-in voltage control circuit generates a burn-in supply voltage which is input to the semiconductor integrated circuit, and also maintains the burn-in supply voltage at the reference voltage level such that each of the integrated circuits receives a burn-in supply voltage having the same voltage level.
    Type: Grant
    Filed: December 18, 1995
    Date of Patent: October 20, 1998
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Yoshiro Nakata, Shin Hashimoto, Isao Miyanaga
  • Patent number: 5795828
    Abstract: A contact hole and a wiring groove are formed in an insulating layer formed on a semiconductor substrate. A silver layer is formed inside of the contact hole and the wiring groove and on the insulating layer with the use of an electroless plating bath comprising: silver nitrate containing silver ions; tartaric acid serving as a reducing agent of the silver ions; ethylenediamine serving as a complexing agent of the silver ions; and metallic ions of tetramethylammoniumhydroxide serving as a pH control agent. Then, the silver layer on the insulating layer is removed by a chemical and mechanical polishing method such that an embedded wiring is formed in each of the contact hole and the wiring groove.
    Type: Grant
    Filed: July 3, 1996
    Date of Patent: August 18, 1998
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Masayuki Endo, Akemi Kawaguchi, Mikio Nishio, Shin Hashimoto
  • Patent number: 5645628
    Abstract: A contact hole and a wiring groove are formed in an insulating layer formed on a semiconductor substrate. A silver layer is formed inside of the contact hole and the wiring groove and on the insulating layer with the use of an electroless plating bath comprising: silver nitrate containing silver ions; tartaric acid serving as a reducing agent of the silver ions; ethylenediamine serving as a complexing agent of the silver ions; and metallic ions of tetramethylammoniumhydroxide serving as a pH control agent. Then, the silver layer on the insulating layer is removed by a chemical and mechanical polishing method such that an embedded wiring is formed in each of the contact hole and the wiring groove.
    Type: Grant
    Filed: July 13, 1995
    Date of Patent: July 8, 1997
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Masayuki Endo, Akemi Kawaguchi, Mikio Nishio, Shin Hashimoto
  • Patent number: 5641699
    Abstract: In a semiconductor device, an outer peripheral part of an integrated circuit region separated by an insulation part is defined as a dummy cell region and a center part except the outer peripheral part of the integrated circuit region is defined as an active cell region. Memory cells such as DRAM, SRAM, EEPROM, mask ROM are formed in the active cell region. In the integrated circuit region, plural cell forming regions are provided which are respectively defined by an isolation. Active cells each having a field effect semiconductor element are provided in a region included in the active cell region of each cell forming region. Dummy cells each having an element inoperable as an semiconductor element are provided in a region included in the dummy cell region of each cell forming region.
    Type: Grant
    Filed: July 14, 1995
    Date of Patent: June 24, 1997
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Junji Hirase, Shin Hashimoto
  • Patent number: 5584964
    Abstract: There is disclosed a method of producing a semiconductor memory device. An interlayer insulation film is formed on a semiconductor substrate including a switching transistor. Then, a memory node pattern reaching an active region of the switching transistor is formed. A cell plate electrode pattern is formed through an insulation film formed on the memory node in such a manner that a value obtained by subtracting a thickness of a polycrystalline silicon film for a cell plate electrode from an overlapping dimension of a memory node pattern and the cell plate electrode pattern is not less than two times larger and not more than ten times larger than a thickness of deposition of a BPSG film. Then, the BPSG film is deposited on an entire surface, and then is caused to viscously flow by a heat treatment. Then, an aluminum wiring is formed on the BPSG film.
    Type: Grant
    Filed: May 30, 1995
    Date of Patent: December 17, 1996
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Hiroyuki Umimoto, Shin Hashimoto, Shinji Odanaka
  • Patent number: 5468983
    Abstract: In a semiconductor device, an outer peripheral part of an integrated circuit region separated by an insulation part is defined as a dummy cell region and a center part except the outer peripheral part of the integrated circuit region is defined as an active cell region. Memory cells such as DRAM, SRAM, EEPROM, mask ROM are formed in the active cell region. In the integrated circuit region, plural cell forming regions are provided which are respectively defined by an isolation. Active cells each having a field effect semiconductor element are provided in a region included in the active cell region of each cell forming region. Dummy cells each having an element inoperable as an semiconductor element are provided in a region included in the dummy cell region of each cell forming region.
    Type: Grant
    Filed: March 1, 1994
    Date of Patent: November 21, 1995
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Junji Hirase, Shin Hashimoto
  • Patent number: 5455205
    Abstract: There is disclosed a method of producing a semiconductor memory device. An interlayer insulation film is formed on a semiconductor substrate including a switching transistor. Then, a memory node pattern reaching an active region of the switching transistor is formed. A cell plate electrode pattern is formed through an insulation film formed on the memory node in such a manner that a value obtained by subtracting a thickness of a polycrystalline silicon film for a cell plate electrode from an overlapping dimension of a memory node pattern and the cell plate electrode pattern is not less than two times larger and not more than ten times larger than a thickness of deposition of a BPSG film. Then, the BPSG film is deposited on an entire surface, and then is caused to viscously flow by a heat treatment. Then, an aluminum wiring is formed on the BPSG film.
    Type: Grant
    Filed: March 19, 1993
    Date of Patent: October 3, 1995
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Hiroyuki Umimoto, Shin Hashimoto, Shinji Odanaka
  • Patent number: 5405800
    Abstract: A method of fabricating a semiconductor memory device on a semiconductor substrate is disclosed. A gate electrode that becomes a word line, a bit line, and a charge-storage electrode are formed in a memory cell array region of a semiconductor substrate. A capacitor insulator layer and a plate electrode are formed in that order. Then, a BPSG film is formed in the memory cell array region and in the peripheral circuit region. A resist pattern is formed on the BPSG film, leaving the memory cell array region exposed. Using the resist pattern thus formed as a mask, an etching treatment is applied to remove an upper surface portion of the BPSG film lying within the memory cell array region by a given amount. After the resist pattern is removed, the BPSG film is heated in order that it reflows to planarize.
    Type: Grant
    Filed: July 12, 1994
    Date of Patent: April 11, 1995
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Hisashi Ogawa, Susumu Matsumoto, Shin Hashimoto, Hiroyuki Umimoto
  • Patent number: 5300814
    Abstract: A semiconductor device comprising a semiconductor substrate, a plurality of memory cell regions each having a plurality of memory cells disposed on the semiconductor substrate, a word line formed in a first level above the semiconductor substrate, a bit line formed in a second level above the first level, and a backing line having a lower resistance than the word line and formed in a third level above the second level. A dummy bit line is formed in the second level outside the memory cell region so as to reduce the step formed at the periphery of the memory cell region. The dummy bit line is also used to interconnect the word line and the backing line so that an electrical connection therebetween is stabilized.
    Type: Grant
    Filed: July 17, 1992
    Date of Patent: April 5, 1994
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Susumu Matsumoto, Shin Hashimoto, Toshio Yamada, Yoshiro Nakata
  • Patent number: 5296719
    Abstract: A quantum wire is formed at the top of triangular protrusion of silicon substrate. A quantum wire is isolated from the substrate by silicon oxide layers. A quantum wire is isolated from the substrate by impurity layers of a conduction type different from that of the substrate. An insulator film and a gate electrode are formed at the edge of triangular protrusion of a silicon substrate, and a quantum wire is induced by applying a voltage to the gate electrode. A quantum wire structure is fabricated by forming saw-tooth-like protrusions having (111) side planes by performing anisotropic crystalline etching and by oxidizing the silicon substrate with use of the oxide protection film to remain only around the top of the protrusions unoxidized. In another method, an oxide film is formed except around the top of the protrusions whereby a quantum wire is formed at the unoxidized region. In a different method, impurity layers are formed except around the top of the protrusions by ion implantation.
    Type: Grant
    Filed: July 20, 1992
    Date of Patent: March 22, 1994
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Yoshihiko Hirai, Juro Yasui, Yasuaki Terui, Kiyoshi Morimoto, Atsuo Wada, Kenji Okada, Shin Hashimoto, Shinji Odanaka, Masaaki Niwa, Kaoru Inoue