Patents by Inventor Shin Soyano

Shin Soyano has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11075190
    Abstract: A semiconductor device includes a printed circuit board in a peripheral portion of a housing portion of a case in which a laminated substrate is housed. A terminal block holding control terminals from which control signals are outputted to the printed circuit board is disposed over the printed circuit board. A gate electrode of a semiconductor chip and the printed circuit board are electrically connected by a wire.
    Type: Grant
    Filed: July 25, 2019
    Date of Patent: July 27, 2021
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventor: Shin Soyano
  • Patent number: 10784214
    Abstract: A semiconductor module includes: a first lead frame connected to a plurality of semiconductor chips in a first arm circuit; a second lead frame connected to a plurality of semiconductor chips in a second arm circuit; a first main terminal connected to the first lead frame; and a second main terminal connected to the second lead frame, wherein each of the first lead frame and second lead frame has a facing part, a first terminal connection portion connected to the first main terminal is provided at a first end portion of the first lead frame, a second terminal connection portion connected to the second main terminal is provided at a second end portion of the second lead frame, and the first terminal connection portion and second terminal connection portion are arranged on opposite sides when viewed from the facing parts of the first lead frame and second lead frame.
    Type: Grant
    Filed: January 29, 2019
    Date of Patent: September 22, 2020
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventors: Shin Soyano, Hayato Nakano, Keiichi Higuchi, Akihiro Osawa
  • Patent number: 10637168
    Abstract: A semiconductor device is provided, in order to prevent tilt of a terminal pin in the semiconductor device with a printed board in which the terminal pin is pressed, the semiconductor device comprising a printed board, a plurality of pins pressed in the printed board, a resin block in which a plurality of through holes are formed, the plurality of pins respectively pressed in the plurality of through holes, and a resin case covering at least a part of the printed board and the resin block.
    Type: Grant
    Filed: November 24, 2017
    Date of Patent: April 28, 2020
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventor: Shin Soyano
  • Publication number: 20190348402
    Abstract: A semiconductor device includes a printed circuit board in a peripheral portion of a housing portion of a case in which a laminated substrate is housed. A terminal block holding control terminals from which control signals are outputted to the printed circuit board is disposed over the printed circuit board. A gate electrode of a semiconductor chip and the printed circuit board are electrically connected by a wire.
    Type: Application
    Filed: July 25, 2019
    Publication date: November 14, 2019
    Applicant: FUJI ELECTRIC CO., LTD.
    Inventor: Shin SOYANO
  • Patent number: 10396056
    Abstract: A semiconductor device includes a printed circuit board in a peripheral portion of a housing portion of a case in which a laminated substrate is housed. A terminal block holding control terminals from which control signals are outputted to the printed circuit board is disposed over the printed circuit board. A gate electrode of a semiconductor chip and the printed circuit board are electrically connected by a wire.
    Type: Grant
    Filed: June 8, 2016
    Date of Patent: August 27, 2019
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventor: Shin Soyano
  • Patent number: 10396023
    Abstract: The semiconductor device includes a multi-layered substrate having an insulating plate and a circuit plate, a semiconductor chip having a front surface attached with a main electrode and a control electrode formed thereon, and a back surface fixed to the circuit plate, a first wiring substrate which includes a first conductive member and is placed so as to face the main electrode connected electrically to first conductive member, a second wiring substrate which includes a second conductive member, is placed so as to face the control electrode, and has an opening, and a conductive post having one end and another end, the one end being connected electrically and mechanically to the control electrode, and the other end being connected electrically and mechanically to the second conductive member. The first conductive member is thicker than the second conductive member, and the first wiring substrate is disposed within the opening.
    Type: Grant
    Filed: September 29, 2016
    Date of Patent: August 27, 2019
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventors: Yuki Inaba, Daisuke Inoue, Shin Soyano
  • Publication number: 20190157221
    Abstract: A semiconductor module includes: a first lead frame connected to a plurality of semiconductor chips in a first arm circuit; a second lead frame connected to a plurality of semiconductor chips in a second arm circuit; a first main terminal connected to the first lead frame; and a second main terminal connected to the second lead frame, wherein each of the first lead frame and second lead frame has a facing part, a first terminal connection portion connected to the first main terminal is provided at a first end portion of the first lead frame, a second terminal connection portion connected to the second main terminal is provided at a second end portion of the second lead frame, and the first terminal connection portion and second terminal connection portion are arranged on opposite sides when viewed from the facing parts of the first lead frame and second lead frame.
    Type: Application
    Filed: January 29, 2019
    Publication date: May 23, 2019
    Inventors: Shin SOYANO, Hayato NAKANO, Keiichi HIGUCHI, Akihiro OSAWA
  • Patent number: 10283440
    Abstract: A semiconductor device includes: a frame; a first-external-terminal provided to a first side portion of the frame; a first substrate enclosed in the frame and having a first-conductive-layer at an upper surface; a first-semiconductor-element: mounted on the first-conductive-layer; having, on a lower surface, a first main electrode connecting with the first-conductive-layer; and having a second main electrode and a control electrode on an upper surface; a first terminal connecting portion establishing a connection between the first-external-terminal and an exposed portion of the first-conductive-layer between the first-semiconductor-element and the first-external-terminal; a first-external-control-terminal provided above a wire in the frame and between the first main electrode of the first-semiconductor-element and the first-external-terminal; and a first control terminal connecting portion establishing a connection: between the control electrode of the first-semiconductor-element and the first-external-contro
    Type: Grant
    Filed: February 23, 2018
    Date of Patent: May 7, 2019
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventor: Shin Soyano
  • Patent number: 10028400
    Abstract: In a semiconductor device, a multilayer substrate includes an insulating substrate, a first circuit board having a first semiconductor chip disposed thereon, and a second circuit board having a second semiconductor chip disposed thereon. On the multilayer substrate of the semiconductor device, a plate portion of a resin plate including a first positioning portion that regulates the position of each semiconductor chip is sandwiched between a first jumper terminal, which includes a first terminal connected to the first semiconductor chip and a first plate member perpendicular to the first terminal, and a second jumper terminal, which includes a second terminal connected to the second semiconductor chip and a second plate member perpendicular to the second terminal.
    Type: Grant
    Filed: July 1, 2016
    Date of Patent: July 17, 2018
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventor: Shin Soyano
  • Publication number: 20180183161
    Abstract: A semiconductor device is provided, in order to prevent tilt of a terminal pin in the semiconductor device with a printed board in which the terminal pin is pressed, the semiconductor device comprising a printed board, a plurality of pins pressed in the printed board, a resin block in which a plurality of through holes are formed, the plurality of pins respectively pressed in the plurality of through holes, and a resin case covering at least a part of the printed board and the resin block.
    Type: Application
    Filed: November 24, 2017
    Publication date: June 28, 2018
    Inventor: Shin SOYANO
  • Publication number: 20180182694
    Abstract: A semiconductor device includes: a frame; a first-external-terminal provided to a first side portion of the frame; a first substrate enclosed in the frame and having a first-conductive-layer at an upper surface; a first-semiconductor-element: mounted on the first-conductive-layer; having, on a lower surface, a first main electrode connecting with the first-conductive-layer; and having a second main electrode and a control electrode on an upper surface; a first terminal connecting portion establishing a connection between the first-external-terminal and an exposed portion of the first-conductive-layer between the first-semiconductor-element and the first-external-terminal; a first-external-control-terminal provided above a wire in the frame and between the first main electrode of the first-semiconductor-element and the first-external-terminal; and a first control terminal connecting portion establishing a connection: between the control electrode of the first-semiconductor-element and the first-external-contro
    Type: Application
    Filed: February 23, 2018
    Publication date: June 28, 2018
    Inventor: Shin SOYANO
  • Patent number: 9966344
    Abstract: A semiconductor device includes a plurality of main terminals extending from one end of a base plate toward the other end thereof, a group of semiconductor chips on a side of higher electric potential disposed on one side of the main terminal and mounted on the base plate, and a group of semiconductor chips on a side of lower electric potential disposed on the other side of the main terminal and mounted on the base plate. The one main terminal has an extending portion extending, in a direction perpendicular to the extending direction of the main terminal, toward one of both sides of the main terminal, and two adjacent semiconductor chips in one of the group of semiconductor chips on the side of higher electric potential and the group of semiconductor chips on the side of lower electric potential are axisymmetrically disposed with respect to the extending portion.
    Type: Grant
    Filed: November 23, 2016
    Date of Patent: May 8, 2018
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventor: Shin Soyano
  • Patent number: 9917031
    Abstract: A semiconductor device includes an insulating substrate; a semiconductor element mounted on the insulating substrate; and a radiation block bonded to the semiconductor element. The radiation block includes a three-dimensional radiation portion and a base portion connected to the radiation portion. The radiation portion of the radiation block has a pin shape, a fin shape, or a porous shape.
    Type: Grant
    Filed: October 8, 2015
    Date of Patent: March 13, 2018
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventor: Shin Soyano
  • Patent number: 9905494
    Abstract: A semiconductor device includes a heat radiation cooling base, a first insulating substrate including first and second copper patterns disposed on lower and upper surfaces thereof, respectively, a semiconductor chip including a first main electrode and a control electrode disposed on a first principal surface, and a second main electrode disposed on a second principal surface thereof, and a second insulating substrate including third and fourth copper patterns disposed on lower and upper surfaces thereof, respectively. The second main electrode is bonded to the second copper pattern. The third copper pattern is bonded to at least one of the first main electrode and the control electrode of the semiconductor chip. The third copper pattern and the fourth copper pattern are electrically connected to each other.
    Type: Grant
    Filed: March 29, 2017
    Date of Patent: February 27, 2018
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventor: Shin Soyano
  • Patent number: D814433
    Type: Grant
    Filed: October 12, 2016
    Date of Patent: April 3, 2018
    Assignee: Fuji Electric Co., Ltd
    Inventors: Shin Soyano, Yoshikazu Takamiya, Keiichi Higuchi, Takahiro Koyama
  • Patent number: D827593
    Type: Grant
    Filed: January 5, 2018
    Date of Patent: September 4, 2018
    Assignee: Fuji Electric Co., Ltd
    Inventors: Shin Soyano, Yoshikazu Takamiya, Keiichi Higuchi, Takahiro Koyama
  • Patent number: D903612
    Type: Grant
    Filed: September 10, 2019
    Date of Patent: December 1, 2020
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventors: Shin Soyano, Hiromichi Gohara
  • Patent number: D942404
    Type: Grant
    Filed: June 28, 2019
    Date of Patent: February 1, 2022
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventors: Shin Soyano, Daisuke Inoue
  • Patent number: D942405
    Type: Grant
    Filed: June 28, 2019
    Date of Patent: February 1, 2022
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventors: Shin Soyano, Daisuke Inoue
  • Patent number: D983759
    Type: Grant
    Filed: October 24, 2019
    Date of Patent: April 18, 2023
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventors: Daiki Yoshida, Hiromichi Gohara, Shin Soyano