Patents by Inventor Shinichi Kanno

Shinichi Kanno has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • MEMORY SYSTEM AND NON-TRANSITORY COMPUTER READABLE RECORDING MEDIUM
    Publication number: 20220253381
    Abstract: According to one embodiment, a memory system includes a nonvolatile memory, configuration unit, address translation unit, write unit and control unit. The configuration unit assigns write management areas included in a nonvolatile memory to spaces and an input space. The write management area is a unit of an area which manages the number of write. The address translation unit associates a logical address of write data with a physical address which indicates a position of the write data in the nonvolatile memory. The write unit writes the write data to the input space and then writes the write data in the input space to a space corresponding to the write data amongst the spaces. The control unit controls the spaces individually with respect to the nonvolatile memory.
    Type: Application
    Filed: April 27, 2022
    Publication date: August 11, 2022
    Inventor: Shinichi Kanno
  • Memory system and method of controlling nonvolatile memory and for reducing a buffer size
    Patent number: 11409467
    Abstract: According to one embodiment, a memory system determines, for each of groups corresponding to streams, whether or not a length of write data associated with a set of write commands belonging to a same group reaches a minimum write size of a nonvolatile memory. When a length of write data associated with a set of write commands belonging to a first group corresponding to a first stream reaches the minimum write size, the memory system transfers the write data associated with the set of write commands belonging to the first group from a write buffer in a memory of the host to a first buffer in the memory system, and writes the write data transferred to the first buffer to a first write destination block corresponding to the first stream.
    Type: Grant
    Filed: March 11, 2020
    Date of Patent: August 9, 2022
    Assignee: Kioxia Corporation
    Inventor: Shinichi Kanno
  • MEMORY SYSTEM AND METHOD FOR CONTROLLING NONVOLATILE MEMORY
    Publication number: 20220244854
    Abstract: According to one embodiment, when receiving a write command including a first identifier of identifiers for accessing regions from a host, a memory system allocates one block of a common free block group shared by the regions as a write destination block for the region corresponding to the first identifier. When receiving a copy command including a block address of a copy source block of blocks belonging to the region corresponding to the first identifier, and an identifier of a copy destination target region indicative of the first identifier from the host, the memory system allocates one block as a copy destination block for the region corresponding to the first identifier, and copies data from the copy source block to the copy destination block.
    Type: Application
    Filed: April 14, 2022
    Publication date: August 4, 2022
    Applicant: KIOXIA CORPORATION
    Inventor: Shinichi KANNO
  • MEMORY SYSTEM AND METHOD OF CONTROLLING NONVOLATILE MEMORY
    Publication number: 20220236916
    Abstract: According to one embodiment, in response to receiving a first namespace create command specifying a first attribution from a host, a controller creates a first namespace having the first attribution and a first logical address range. The first logical address range includes logical addresses. The controller sets each of the logical addresses to an unallocated state in which a physical address of the nonvolatile memory is not mapped, during a first period from a time when receiving a power loss advance notification or when detecting an unexpected power loss until a time when the controller becomes a ready state by resupply of a power to the memory system.
    Type: Application
    Filed: September 13, 2021
    Publication date: July 28, 2022
    Inventors: Naoki ESAKA, Shinichi KANNO
  • MEMORY SYSTEM AND NON-TRANSITORY COMPUTER READABLE RECORDING MEDIUM
    Publication number: 20220237114
    Abstract: According to one embodiment, a memory system includes a nonvolatile memory, configuration unit, address translation unit, write unit and control unit. The configuration unit assigns write management areas included in the nonvolatile memory to spaces. The write management area is a unit of an area which manages the number of write. The address translation unit translates a logical address of write data into a physical address of a space corresponding to the write data. The write unit writes the write data to a position indicated by the physical address in the nonvolatile memory. The control unit controls the spaces individually with respect to the nonvolatile memory.
    Type: Application
    Filed: April 19, 2022
    Publication date: July 28, 2022
    Inventor: Shinichi Kanno
  • Ligation device
    Patent number: 11389166
    Abstract: The ligation device includes a tubular body having a tubular shape and including a hollow part into which a string-shaped body can be inserted. The tubular body includes a proximal opening and a distal opening at a proximal end part and a distal end part, respectively. The proximal opening and the distal opening communicate with each other via a lumen of the tubular body. The side of a first end part of the string-shaped body can be inserted into the hollow part. The tubular body includes, on the distal end part, a locking part capable of locking the side of a second end part of the string-shaped body, after the string-shaped body is wound around the target, in a state where the first end part side of the string-shaped body is inserted into the lumen.
    Type: Grant
    Filed: May 25, 2020
    Date of Patent: July 19, 2022
    Assignee: FORCE ENGINEERING CO., LTD.
    Inventors: Takanori Imai, Takaki Sawahata, Hiroshi Hirota, Shinichi Kanno, Shinichi Ono, Tomoyuki Sawahata, Tomohiro Murakami, Tomoaki Higuchi
  • Memory system and method of controlling nonvolatile memory
    Patent number: 11392323
    Abstract: According to one embodiment, a memory system manages a plurality of first weights that correspond to the plurality of queues, and a plurality of second weights that correspond to the plurality of queues. The memory system selects a queue of a largest or smallest second weight, of the plurality of queues, as a queue of a highest priority, and starts execution of a command stored in the selected queue. The memory system updates the second weight corresponding to the selected queue by subtracting the first weight corresponding to the selected queue from the second weight corresponding to the selected queue or by adding the first weight corresponding to the selected queue to the second weight corresponding to the selected queue.
    Type: Grant
    Filed: September 10, 2020
    Date of Patent: July 19, 2022
    Assignee: Kioxia Corporation
    Inventor: Shinichi Kanno
  • Storage system
    Patent number: 11392466
    Abstract: According to one embodiment, a storage system includes a first storage including first nonvolatile memories storing data which is corrupted when data is read from the first nonvolatile memories, and a controller which controls the first storage. The controller reads data from a first nonvolatile memory at a first address, and determines that whether the read data is to be written back to the first storage or not.
    Type: Grant
    Filed: June 5, 2018
    Date of Patent: July 19, 2022
    Assignee: Kioxia Corporation
    Inventors: Shinichi Kanno, Hideki Yoshida
  • STORAGE SYSTEM, MEMORY CHIP UNIT, AND WAFER
    Publication number: 20220223552
    Abstract: A memory chip unit includes a pad electrode including first and second portions, and a memory cell array. A prober includes a probe card and a movement mechanism. The probe card includes a probe electrode to be in contact with the pad electrode, and a memory controller electrically coupled to the probe electrode and executes reading and writing on the memory cell array. The movement mechanism executes a first operation that brings the probe electrode into contact with the first portion and does not bring the probe electrode into contact with the second portion, and a second operation that does not bring the probe electrode into contact with the first portion and brings the probe electrode into contact with the second portion.
    Type: Application
    Filed: March 15, 2022
    Publication date: July 14, 2022
    Inventors: Yasuhito YOSHIMIZU, Takashi FUKUSHIMA, Tatsuro HITOMI, Arata INOUE, Masayuki MIURA, Shinichi KANNO, Toshio FUJISAWA, Keisuke NAKATSUKA, Tomoya SANUKI
  • Information processing system for controlling storage device
    Patent number: 11385800
    Abstract: According to one embodiment, when it is determined that a first storage device of a plurality of storage devices is to be removed and an additional storage device is connected to a storage controller, the storage controller writes update data portions corresponding to data portions already written to the first storage device to any storage device selected from remaining one or more storage devices of the plurality of storage devices except for the first storage device and the additional storage device. Further, the storage controller writes update data portions corresponding to data portions already written to the remaining one or more storage devices to any storage device selected from the remaining one or more storage devices and the additional storage device.
    Type: Grant
    Filed: March 14, 2019
    Date of Patent: July 12, 2022
    Assignee: Kioxia Corporation
    Inventor: Shinichi Kanno
  • MEMORY SYSTEM AND METHOD OF CONTROLLING NONVOLATILE MEMORY
    Publication number: 20220214966
    Abstract: According to one embodiment, a controller of a memory system writes write data associated with a set of received write requests to a first write destination storage region in a first write mode of writing a plurality of bits per memory cell, without writing the write data to a second storage region. When receiving from a host a first request to cause a state of the first write destination storage region to transition to a second state in which writing is suspended, the controller transfers un-transferred remaining write data from a write buffer of the host to an internal buffer, and writes the remaining write data to the second storage region in a second write mode of writing 1 bit per memory cell.
    Type: Application
    Filed: March 21, 2022
    Publication date: July 7, 2022
    Applicant: Kioxia Corporation
    Inventors: Shinichi KANNO, Naoki ESAKA
  • STORAGE DEVICE AND CONTROL METHOD
    Publication number: 20220204270
    Abstract: According to one embodiment, a storage device includes a control apparatus and a stocker. The control apparatus writes data to or reads data from a storage medium that includes a plurality of non-volatile memory chips. The stocker stores a plurality of the storage media that are detached from the control apparatus. The control apparatus includes a first temperature control system. The first temperature control system raises temperature of the storage medium to a first temperature or higher. The stocker includes a second temperature control system. The second temperature control system cools the storage medium to a second temperature or lower. The second temperature is lower than the first temperature.
    Type: Application
    Filed: March 14, 2022
    Publication date: June 30, 2022
    Inventors: Yasuhito YOSHIMIZU, Takashi FUKUSHIMA, Tatsuro HITOMI, Arata INOUE, Masayuki MIURA, Shinichi KANNO, Toshio FUJISAWA, Keisuke NAKATSUKA, Tomoya SANUKI
  • MEMORY SYSTEM AND METHOD FOR CONTROLLING NONVOLATILE MEMORY
    Publication number: 20220197817
    Abstract: According to one embodiment, when a read request received from a host includes a first identifier indicative of a first region, a memory system obtains a logical address from the received read request, obtains a physical address corresponding to the obtained logical address from a logical-to-physical address translation table which manages mapping between logical addresses and physical addresses of the first region, and reads data from the first region, based on the obtained physical address. When the received read request includes a second identifier indicative of a second region, the memory system obtains physical address information from the read request, and reads data from the second region, based on the obtained physical address information.
    Type: Application
    Filed: March 8, 2022
    Publication date: June 23, 2022
    Inventors: Hideki Yoshida, Shinichi Kanno
  • Memory including a plurality of nonvolatile memory dies each including a plurality of physical blocks
    Patent number: 11366612
    Abstract: According to one embodiment, a memory system writes first write data into each non-defective physical block belonging to a first write destination block group. The memory system notifies a host of a first identifier of the first write data, an address specifying the first write destination block group, a first offset indicating a top write destination physical storage location in the first write destination block group in which the first write data is written, length of the first write data, and first bitmap information including a plurality of bits, each of the bits corresponding to each of physical blocks belonging to the first write destination block group and indicating whether or not the corresponding physical block is a defective block.
    Type: Grant
    Filed: March 11, 2020
    Date of Patent: June 21, 2022
    Assignee: Kioxia Corporation
    Inventors: Shinichi Kanno, Takehiko Kurashige
  • MEMORY SYSTEM WITH CONTROLLER TO WRITE DATA TO MEMORY BASED ON LIFETIME INFORMATION IN WRITE COMMAND
    Publication number: 20220188039
    Abstract: According to one embodiment, a memory system detects a first block in which an elapsed time from a time point at which the block has been filled with write data exceeds a first period. The memory system notifies a host of a list of identifiers capable of identifying valid data portions stored in the first block or a list of identifiers capable of identifying all data portions stored in the first block. When receiving, from the host, a first copy request specifying one or more valid data portions stored in the first block as copy target data and specifying the second block group as a copy destination block group, the memory system copies the one or more valid data portions specified as the copy target data from the first block to the second block group.
    Type: Application
    Filed: March 2, 2022
    Publication date: June 16, 2022
    Applicant: Kioxia Corporation
    Inventor: Shinichi KANNO
  • Memory system and non-transitory computer readable recording medium
    Patent number: 11347637
    Abstract: According to one embodiment, a memory system includes a nonvolatile memory, configuration unit, address translation unit, write unit and control unit. The configuration unit assigns write management areas included in a nonvolatile memory to spaces and an input space. The write management area is a unit of an area which manages the number of write. The address translation unit associates a logical address of write data with a physical address which indicates a position of the write data in the nonvolatile memory. The write unit writes the write data to the input space and then writes the write data in the input space to a space corresponding to the write data amongst the spaces. The control unit controls the spaces individually with respect to the nonvolatile memory.
    Type: Grant
    Filed: August 7, 2020
    Date of Patent: May 31, 2022
    Assignee: Kioxia Corporation
    Inventor: Shinichi Kanno
  • Memory system and method for controlling nonvolatile memory
    Patent number: 11347655
    Abstract: According to one embodiment, when a read request received from a host includes a first identifier indicative of a first region, a memory system obtains a logical address from the received read request, obtains a physical address corresponding to the obtained logical address from a logical-to-physical address translation table which manages mapping between logical addresses and physical addresses of the first region, and reads data from the first region, based on the obtained physical address. When the received read request includes a second identifier indicative of a second region, the memory system obtains physical address information from the read request, and reads data from the second region, based on the obtained physical address information.
    Type: Grant
    Filed: December 23, 2019
    Date of Patent: May 31, 2022
    Assignee: Kioxia Corporation
    Inventors: Hideki Yoshida, Shinichi Kanno
  • MEMORY SYSTEM AND CONTROL METHOD THEREOF
    Publication number: 20220155960
    Abstract: A memory system includes a nonvolatile memory including a plurality of blocks as data erase units, a measuring unit which measures an erase time at which data of each block is erased, and a block controller which writes data supplied from at least an exterior into a first block which is set in a free state and whose erase time is oldest.
    Type: Application
    Filed: February 3, 2022
    Publication date: May 19, 2022
    Applicant: Kioxia Corporation
    Inventors: Kazuya Kitsunai, Shinichi Kanno, Hirokuni Yano, Toshikatsu Hida, Junji Yano
  • CONTROLLER FOR CONTROLLING NON-VOLATILE SEMICONDUCTOR MEMORY AND METHOD OF CONTROLLING NON-VOLATILE SEMICONDUCTOR MEMORY
    Publication number: 20220156182
    Abstract: According to one embodiment, a write instructing unit instructs a data access unit to write, in a storage area of a data storage unit indicated by a first physical address, write object data, instructs a management information access unit to update address conversion information, and instructs a first access unit to update the first physical address. A compaction unit extracts a physical address of compaction object data, instructs the data access unit to read the compaction object data stored in a storage area of the data storage unit indicated by the physical address, instructs the data access unit to write the compaction object data in a storage area of the data storage unit indicated by a second physical address, instructs the management information access unit to update the address conversion information, and instructs a second access unit to update the second physical address.
    Type: Application
    Filed: February 1, 2022
    Publication date: May 19, 2022
    Applicant: KIOXIA CORPORATION
    Inventors: Kazuhiro FUKUTOMI, Kenichiro YOSHII, Shinichi KANNO, Shigehiro ASANO
  • Memory system and method for controlling nonvolatile memory
    Patent number: 11334266
    Abstract: According to one embodiment, when receiving a write command including a first identifier of identifiers for accessing regions from a host, a memory system allocates one block of a common free block group shared by the regions as a write destination block for the region corresponding to the first identifier. When receiving a copy command including a block address of a copy source block of blocks belonging to the region corresponding to the first identifier, and an identifier of a copy destination target region indicative of the first identifier from the host, the memory system allocates one block as a copy destination block for the region corresponding to the first identifier, and copies data from the copy source block to the copy destination block.
    Type: Grant
    Filed: September 9, 2019
    Date of Patent: May 17, 2022
    Assignee: KIOXIA CORPORATION
    Inventor: Shinichi Kanno