Patents by Inventor Shinichi Kanno

Shinichi Kanno has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Memory system and method of controlling memory system
    Patent number: 11579773
    Abstract: According to one embodiment, a memory system includes a non-volatile semiconductor memory, a block management unit, and a transcription unit. The semiconductor memory includes a plurality of blocks to which data can be written in both the first mode and the second mode. The block management unit manages a block that stores therein no valid data as a free block. When the number of free blocks managed by the block management unit is smaller than or equal to a predetermined threshold value, the transcription unit selects one or more used blocks that stores therein valid data as transcription source blocks and transcribes valid data stored in the transcription source blocks to free blocks in the second mode.
    Type: Grant
    Filed: December 7, 2021
    Date of Patent: February 14, 2023
    Assignee: Toshiba Memory Corporation
    Inventors: Hiroshi Yao, Shinichi Kanno, Kazuhiro Fukutomi
  • SEMICONDUCTOR STORAGE DEVICE WITH VOLATILE AND NONVOLATILE MEMORIES TO ALLOCATE BLOCKS TO A MEMORY AND RELEASE ALLOCATED BLOCKS
    Publication number: 20230042619
    Abstract: A semiconductor storage device includes a first memory area configured in a volatile semiconductor memory, second and third memory areas configured in a nonvolatile semiconductor memory, and a controller which executes following processing. The controller executes a first processing for storing a plurality of data by the first unit in the first memory area, a second processing for storing data outputted from the first memory area by a first management unit in the second memory area, and a third processing for storing data outputted from the first memory area by a second management unit in the third memory area.
    Type: Application
    Filed: October 27, 2022
    Publication date: February 9, 2023
    Applicant: Kioxia Corporation
    Inventors: Hirokuni YANO, Shinichi KANNO, Toshikatsu HIDA, Hidenori MATSUZAKI, Kazuya KITSUNAI, Shigehiro ASANO
  • MEMORY SYSTEM AND INFORMATION PROCESSING SYSTEM
    Publication number: 20230038797
    Abstract: According to one embodiment, a memory system includes a nonvolatile memory and a memory controller configured to execute a patrol process, in response to a first command set from a host device. In the patrol process, the memory controller is configured to read first data from the nonvolatile memory, and not to output the first data to the host device.
    Type: Application
    Filed: October 24, 2022
    Publication date: February 9, 2023
    Applicant: Kioxia Corporation
    Inventors: Yasuhiko KUROSAWA, Naomi TAKEDA, Masanobu SHIRAKAWA, Yasuyuki USHIJIMA, Shinichi KANNO
  • Storage device having a controller configured to select modes as write modes based on received instructions, storage system, and control method
    Patent number: 11573717
    Abstract: According to one embodiment, a storage device includes a nonvolatile memory and a controller. The controller is configured to select a first mode as a write mode to write data from the host to the nonvolatile memory when the controller receives a first instruction from the host. In the first mode, n-bit data is written into a memory cell in a first area of the nonvolatile memory, n being a positive integer more than or equal to 1. The controller is configured to select another mode different from the first mode as the write mode when the controller receives a second instruction from the host.
    Type: Grant
    Filed: March 15, 2021
    Date of Patent: February 7, 2023
    Assignee: Kioxia Corporation
    Inventors: Takahiro Kurita, Tetsuya Sunata, Shinichi Kanno
  • Semiconductor memory device and method of controlling the same
    Patent number: 11575395
    Abstract: A semiconductor memory device includes a plurality of detecting code generators configured to generate a plurality of detecting codes to detect errors in a plurality of data items, respectively, a plurality of first correcting code generators configured to generate a plurality of first correcting codes to correct errors in a plurality of first data blocks, respectively, each of the first data blocks containing one of the data items and a corresponding detecting code, a second correcting code generators configured to generate a second correcting code to correct errors in a second data block, the second data block containing the first data blocks, and a semiconductor memory configured to nonvolatilely store the second data block, the first correcting codes, and the second correcting code.
    Type: Grant
    Filed: May 11, 2021
    Date of Patent: February 7, 2023
    Assignee: Kioxia Corporation
    Inventors: Shinichi Kanno, Hironori Uchikawa
  • MEMORY SYSTEM AND METHOD OF CONTROLLING NONVOLATILE MEMORY
    Publication number: 20230022741
    Abstract: According to one embodiment, when data is to be written to a first physical storage location that is designated by a first physical address, a memory system encrypts the data with the first physical address and a first encryption key, and writes the encrypted data to the first physical storage location. When the encrypted data is to be copied to a second physical storage location, the memory system decrypts the encrypted data with the first physical address and the first encryption key, and re-encrypts the decrypted data with a second encryption key and a copy destination physical address indicative of the second physical storage location.
    Type: Application
    Filed: October 4, 2022
    Publication date: January 26, 2023
    Applicant: KIOXIA CORPORATION
    Inventor: Shinichi KANNO
  • MEMORY SYSTEM AND METHOD OF CONTROLLING NONVOLATILE MEMORY
    Publication number: 20230014304
    Abstract: According to one embodiment, when a command executed in a nonvolatile memory is an erase/program command and when a cumulative weight value satisfies a condition that a first input is selected as an input of high priority, a memory system suspends execution of the erase/program command by transmitting a suspend command to the nonvolatile memory. The memory system repeats executing an operation of starting the execution of one read command of the first input and an operation of updating the cumulative weight by using the weight associated with the read command until read command no longer exists in the first input or until the condition that the cumulative weight is larger than the first value is not satisfied, and resumes the execution of the suspended erase/program command.
    Type: Application
    Filed: September 28, 2022
    Publication date: January 19, 2023
    Applicant: Kioxia Corporation
    Inventor: Shinichi KANNO
  • MEMORY SYSTEM AND METHOD OF CONTROLLING NONVOLATILE MEMORY
    Publication number: 20230014508
    Abstract: According to one embodiment, a controller manages a first set of blocks and a second set of blocks. The controller allocates a second block included in the second set of blocks to a first block included in the first set of blocks. In response to receiving one or more write command specifying the first block, the controller writes data associated with the one or more received write commands to the second block in units of a second minimum write size. When the first block is filled with data that has been written to the first block and unwritten region remains in the second block, the controller deallocates the second block from the first block, and allocates the deallocated second block to a write destination block other than the first block.
    Type: Application
    Filed: March 3, 2022
    Publication date: January 19, 2023
    Applicant: Kioxia Corporation
    Inventor: Shinichi KANNO
  • STORAGE DEVICE THAT WRITES DATA FROM A HOST DURING GARBAGE COLLECTION
    Publication number: 20230004289
    Abstract: A memory system includes a controller, a buffer, and a nonvolatile memory including a plurality of blocks, wherein each of the blocks includes a plurality of pages and each of the pages includes a plurality of unit data portions. The controller is configured to carry out garbage collection by reading data from one or more pages of a target block of the garbage collection and selectively copying valid unit data portions included in the read data to another block, count a number of invalid unit data portions included in the read data, and accept, in the buffer, unit data portions from a host as write data, up to a number determined based on the counted number, during the garbage collection.
    Type: Application
    Filed: September 12, 2022
    Publication date: January 5, 2023
    Inventor: Shinichi KANNO
  • Memory system and method for controlling nonvolatile memory
    Patent number: 11543997
    Abstract: According to one embodiment, a memory system includes a nonvolatile memory and a controller. The controller acquires, from a host, write data having the same first size as a data write unit of the nonvolatile memory and obtained by dividing write data associated with one write command having a first identifier indicating a first write destination block in a plurality of write destination blocks into a plurality of write data or combining write data associated with two or more write commands having the first identifier. The controller writes the acquired write data having the first size to the first write destination block by a first write operation.
    Type: Grant
    Filed: August 19, 2021
    Date of Patent: January 3, 2023
    Assignee: Kioxia Corporation
    Inventors: Shinichi Kanno, Hideki Yoshida, Naoki Esaka, Hiroshi Nishimura
  • METHOD FOR CONTROLLING WRITE AND READ OPERATIONS IN THE NONVOLATILE MEMORY BY A HOST, USING AN IDENTIFIER FOR A REGION
    Publication number: 20220413770
    Abstract: According to one embodiment, a memory system determines a write destination block and a write destination location in the write destination block to which write data is to be written, and notifies a host of an identifier of the write data, a block address of the write destination block, and an offset indicative of the write destination location. The memory system retrieves the write data from a write buffer of the host, and writes the write data to the write destination location. In a case where a read command to designate a physical address of first data is received before a write operation of the first data is finished, the memory system reads the first data from the write buffer of the host.
    Type: Application
    Filed: August 30, 2022
    Publication date: December 29, 2022
    Applicant: Kioxia Corporation
    Inventor: Shinichi KANNO
  • MEMORY SYSTEM AND METHOD FOR CONTROLLING NONVOLATILE MEMORY
    Publication number: 20220414002
    Abstract: According to one embodiment, a memory system manages a plurality of parallel units each including blocks belonging to different nonvolatile memory dies. When receiving from a host a write request designating a third address to identify first data to be written, the memory system selects one block from undefective blocks included in one parallel unit as a write destination block by referring to defect information, determines a write destination location in the selected block, and writes the first data to the write destination location. The memory system notifies the host of a first physical address indicative of both of the selected block and the write destination location, and the third address.
    Type: Application
    Filed: August 30, 2022
    Publication date: December 29, 2022
    Inventor: Shinichi Kanno
  • MEMORY SYSTEM AND METHOD FOR CONTROLLING NONVOLATILE MEMORY
    Publication number: 20220405199
    Abstract: According to one embodiment, a controller writes a first data associated with a write request and a first logical address specified by the write request to a first block. The controller updates a logical-to-physical address translation table such that a first physical address indicating a first storage location in the first block in which the first data is written is associated with the first logical address. In response to receiving an invalidation request for invalidating the first data corresponding to the first logical address, the controller acquires, from the logical-to-physical address translation table, the first physical address, and updates a valid data identifier corresponding to a storage location indicated by the first physical address to a value indicating invalidation.
    Type: Application
    Filed: March 3, 2022
    Publication date: December 22, 2022
    Applicant: Kioxia Corporation
    Inventor: Shinichi KANNO
  • MEMORY SYSTEM AND INFORMATION PROCESSING SYSTEM
    Publication number: 20220404965
    Abstract: According to one embodiment, a memory system includes a non-volatile memory and a controller. The controller manages validity of data in the non-volatile memory using a data map. The data map includes first fragment tables. Each of the first fragment tables stores first and second information. The first information indicates the validity of each data having a predetermined size written in a range of physical address in the non-volatile memory allocated to the first fragment table. The second information indicates the validity of a plurality of data having a predetermined size in each of entries. The controller selects a write destination block based on a size of write data to be written to the non-volatile memory by a write command from a host.
    Type: Application
    Filed: December 10, 2021
    Publication date: December 22, 2022
    Applicant: Kioxia Corporation
    Inventors: Yuki SASAKI, Shinichi KANNO
  • MEMORY SYSTEM AND METHOD FOR CONTROLLING NONVOLATILE MEMORY
    Publication number: 20220404966
    Abstract: According to one embodiment, a controller constructs a plurality of block groups. The plurality of block groups include at least a first block group configured using a first type block group and a second block group configured using a second block group. The first type block group includes a plurality of non-defective blocks obtained by selecting one or more non-defective blocks in an equal number from each of a plurality of dies or each of a plurality of planes. The second type block group includes a plurality of non-defective blocks. The number of non-defective blocks included in the second type block group is equal to the number of non-defective blocks included in the first type block.
    Type: Application
    Filed: March 3, 2022
    Publication date: December 22, 2022
    Applicant: Kioxia Corporation
    Inventors: Shinichi KANNO, Naoki ESAKA
  • Storage device that secures a block for a stream or namespace and system having the storage device
    Patent number: 11531480
    Abstract: A storage device includes a nonvolatile semiconductor memory device including a plurality of physical blocks and a memory controller. The memory controller is configured to associate one or more physical blocks to each of a plurality of stream IDs, execute a first command containing a first stream ID received from a host, by storing write data included in the write IO in the one or more physical blocks associated with the first stream ID, and execute a second command containing a second stream ID received from the host, by selecting a first physical block that includes valid data and invalid data, transfer the valid data stored in the first physical block to a second physical block, and associate the first physical block from which the valid data has been transferred, with the second stream ID.
    Type: Grant
    Filed: December 7, 2020
    Date of Patent: December 20, 2022
    Assignee: KIOXIA CORPORATION
    Inventors: Daisuke Hashimoto, Shinichi Kanno
  • Semiconductor storage device with volatile and nonvolatile memories to allocate blocks to a memory and release allocated blocks
    Patent number: 11513682
    Abstract: A semiconductor storage device includes a first memory area configured in a volatile semiconductor memory, second and third memory areas configured in a nonvolatile semiconductor memory, and a controller which executes following processing. The controller executes a first processing for storing a plurality of data by the first unit in the first memory area, a second processing for storing data outputted from the first memory area by a first management unit in the second memory area, and a third processing for storing data outputted from the first memory area by a second management unit in the third memory area.
    Type: Grant
    Filed: October 29, 2020
    Date of Patent: November 29, 2022
    Assignee: Kioxia Corporation
    Inventors: Hirokuni Yano, Shinichi Kanno, Toshikatsu Hida, Hidenori Matsuzaki, Kazuya Kitsunai, Shigehiro Asano
  • Memory system and information processing system
    Patent number: 11513735
    Abstract: According to one embodiment, a memory system includes a nonvolatile memory and a memory controller configured to execute a patrol process, in response to a first command set from a host device. In the patrol process, the memory controller is configured to read first data from the nonvolatile memory, and not to output the first data to the host device.
    Type: Grant
    Filed: March 3, 2021
    Date of Patent: November 29, 2022
    Assignee: Kioxia Corporation
    Inventors: Yasuhiko Kurosawa, Naomi Takeda, Masanobu Shirakawa, Yasuyuki Ushijima, Shinichi Kanno
  • Memory system and method of controlling nonvolatile memory
    Patent number: 11513707
    Abstract: According to one embodiment, when data is to be written to a first physical storage location that is designated by a first physical address, a memory system encrypts the data with the first physical address and a first encryption key, and writes the encrypted data to the first physical storage location. When the encrypted data is to be copied to a second physical storage location, the memory system decrypts the encrypted data with the first physical address and the first encryption key, and re-encrypts the decrypted data with a second encryption key and a copy destination physical address indicative of the second physical storage location.
    Type: Grant
    Filed: January 21, 2021
    Date of Patent: November 29, 2022
    Assignee: Kioxia Corporation
    Inventor: Shinichi Kanno
  • MEMORY SYSTEM AND CONTROL METHOD
    Publication number: 20220350530
    Abstract: A controller manages a plurality of block groups each including one or more blocks among a plurality of blocks provided in a non-volatile memory. The controller assigns one of the plurality of block groups to each of plurality of zones. The controller writes write data which is to be written to a first zone to a shared write buffer and writes write data which is to be written to a second zone to the shared write buffer. When a total size of the write data in the first zone stored in the shared write buffer reaches a capacity of the first zone, the controller copies the write data in the first zone stored in the shared write buffer to the first block group assigned to the first zone.
    Type: Application
    Filed: March 2, 2022
    Publication date: November 3, 2022
    Applicant: Kioxia Corporation
    Inventors: Hideki YOSHIDA, Shinichi KANNO, Naoki ESAKA