Patents by Inventor Shinichi Kanno

Shinichi Kanno has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Memory system for controlling nonvolatile memory including a plurality of nonvolatile memory dies each including a plurality of physical blocks
    Patent number: 11675544
    Abstract: According to one embodiment, a memory system writes first write data into each non-defective physical block belonging to a first write destination block group. The memory system notifies a host of a first identifier of the first write data, an address specifying the first write destination block group, a first offset indicating a top write destination physical storage location in the first write destination block group in which the first write data is written, length of the first write data, and first bitmap information including a plurality of bits, each of the bits corresponding to each of physical blocks belonging to the first write destination block group and indicating whether or not the corresponding physical block is a defective block.
    Type: Grant
    Filed: May 5, 2022
    Date of Patent: June 13, 2023
    Assignee: Kioxia Corporation
    Inventors: Shinichi Kanno, Takehiko Kurashige
  • Controller for controlling non-volatile semiconductor memory and method of controlling non-volatile semiconductor memory
    Patent number: 11675697
    Abstract: According to one embodiment, a write instructing unit instructs a data access unit to write, in a storage area of a data storage unit indicated by a first physical address, write object data, instructs a management information access unit to update address conversion information, and instructs a first access unit to update the first physical address. A compaction unit extracts a physical address of compaction object data, instructs the data access unit to read the compaction object data stored in a storage area of the data storage unit indicated by the physical address, instructs the data access unit to write the compaction object data in a storage area of the data storage unit indicated by a second physical address, instructs the management information access unit to update the address conversion information, and instructs a second access unit to update the second physical address.
    Type: Grant
    Filed: February 1, 2022
    Date of Patent: June 13, 2023
    Assignee: KIOXIA CORPORATION
    Inventors: Kazuhiro Fukutomi, Kenichiro Yoshii, Shinichi Kanno, Shigehiro Asano
  • Method for improving trim command response time
    Patent number: 11669264
    Abstract: According to one embodiment, a memory system includes a non-volatile memory and a controller. The non-volatile memory is configured to store an address translation table and a data map. In a case where an invalidation command for invalidating the data written in the non-volatile memory is received from the host, the controller is configured to update the address translation table and the data map based on the invalidation command. A response to the invalidation command is transmitted to the host after the address translation table is updated and before the data map is updated.
    Type: Grant
    Filed: March 15, 2021
    Date of Patent: June 6, 2023
    Assignee: Kioxia Corporation
    Inventors: Yuki Sasaki, Shinichi Kanno
  • Computing system and method for controlling storage device
    Patent number: 11669444
    Abstract: According to one embodiment, a computing system transmits to a storage device a write request designating a first logical address for identifying first data to be written and a length of the first data. The computing system receives from the storage device the first logical address and a first physical address indicative of both of a first block selected from blocks except a defective block by the storage device, and a first physical storage location in the first block to which the first data is written. The computing system updates a first table which manages mapping between logical addresses and physical addresses of the storage device and maps the first physical address to the first logical address.
    Type: Grant
    Filed: September 14, 2021
    Date of Patent: June 6, 2023
    Assignee: Kioxia Corporation
    Inventor: Shinichi Kanno
  • Memory system and method for controlling nonvolatile memory
    Patent number: 11669269
    Abstract: According to one embodiment, a memory system stores write data received from a host to a shared write buffer for write destination blocks, acquires first write data for plural pages from the shared write buffer, and writes the first write data to a first write destination block by a first-step write operation. When receiving write data from the host in a state in which an empty region does not exist in the shared write buffer, the memory system discards write data in the shared write buffer in which the first-step write operation has been finished. In a case where the first write data do not exist in the shared write buffer when a second-step write operation of the first write data is to be executed, the memory system transmits a request to acquire the first write data to the host.
    Type: Grant
    Filed: April 6, 2021
    Date of Patent: June 6, 2023
    Assignee: Kioxia Corporation
    Inventor: Shinichi Kanno
  • Memory system and method of controlling nonvolatile memory and for reducing a buffer size
    Patent number: 11662952
    Abstract: According to one embodiment, a memory system determines, for each of groups corresponding to streams, whether or not a length of write data associated with a set of write commands belonging to a same group reaches a minimum write size of a nonvolatile memory. When a length of write data associated with a set of write commands belonging to a first group corresponding to a first stream reaches the minimum write size, the memory system transfers the write data associated with the set of write commands belonging to the first group from a write buffer in a memory of the host to a first buffer in the memory system, and writes the write data transferred to the first buffer to a first write destination block corresponding to the first stream.
    Type: Grant
    Filed: June 29, 2022
    Date of Patent: May 30, 2023
    Assignee: KIOXIA CORPORATION
    Inventor: Shinichi Kanno
  • Memory system and method of controlling nonvolatile memory
    Patent number: 11663122
    Abstract: According to one embodiment, a controller of a memory system writes write data associated with a set of received write requests to a first write destination storage region in a first write mode of writing a plurality of bits per memory cell, without writing the write data to a second storage region. When receiving from a host a first request to cause a state of the first write destination storage region to transition to a second state in which writing is suspended, the controller transfers un-transferred remaining write data from a write buffer of the host to an internal buffer, and writes the remaining write data to the second storage region in a second write mode of writing 1 bit per memory cell.
    Type: Grant
    Filed: March 21, 2022
    Date of Patent: May 30, 2023
    Assignee: Kioxia Corporation
    Inventors: Shinichi Kanno, Naoki Esaka
  • Memory system and method of controlling nonvolatile memory
    Patent number: 11657163
    Abstract: According to one embodiment, a memory system includes a nonvolatile memory and a controller. In response to receiving from a host a write request designating a first address for identifying data to be written, the controller encrypts the data with the first address and a first encryption key, and writes the encrypted data to the nonvolatile memory together with the first address. In response to receiving from the host a read request designating a physical address indicative of a physical storage location of the nonvolatile memory, the controller reads both the encrypted data and the first address from the nonvolatile memory on the basis of the physical address, and decrypts the read encrypted data with the first encryption key and the read first address.
    Type: Grant
    Filed: February 22, 2019
    Date of Patent: May 23, 2023
    Assignee: Kioxia Corporation
    Inventor: Shinichi Kanno
  • Memory system and method for controlling nonvolatile memory with a host memory buffer
    Patent number: 11656800
    Abstract: According to one embodiment, a memory system retrieves write data from a write buffer of a host, and executes a write operation of writing the write data to a write destination location of a write destination block selected from a plurality of blocks. In a case where a first read command to designate the write data as read target data is received from the host before the write operation is finished such that the write data becomes readable, the memory system executes a read operation including an operation of reading the read target data from the write buffer of the host and an operation of returning the read target data to the host. The memory system prohibits releasing a region in the write buffer where the write data is stored until execution of the first read command is completed.
    Type: Grant
    Filed: January 11, 2022
    Date of Patent: May 23, 2023
    Assignee: Kioxia Corporation
    Inventor: Shinichi Kanno
  • MEMORY SYSTEM AND METHOD OF CONTROLLING MEMORY SYSTEM
    Publication number: 20230152969
    Abstract: According to one embodiment, a memory system includes a non-volatile semiconductor memory, a block management unit, and a transcription unit. The semiconductor memory includes a plurality of blocks to which data can be written in both the first mode and the second mode. The block management unit manages a block that stores therein no valid data as a free block. When the number of free blocks managed by the block management unit is smaller than or equal to a predetermined threshold value, the transcription unit selects one or more used blocks that stores therein valid data as transcription source blocks and transcribes valid data stored in the transcription source blocks to free blocks in the second mode.
    Type: Application
    Filed: January 17, 2023
    Publication date: May 18, 2023
    Applicant: KIOXIA CORPORATION
    Inventors: Hiroshi YAO, Shinichi KANNO, Kazuhiro FUKUTOMI
  • Memory system and method of controlling nonvolatile memory with checking a total size indicative of a sum of data length specified by a write command
    Patent number: 11650760
    Abstract: According to one embodiment, a memory system checks a first total size indicative of a sum of data lengths specified by first write commands stored in a first submission queue of a host corresponding to a first stream. When the first total size is greater than or equal to a minimum write size, the memory system fetches a set of first write commands stored in the first submission queue, transfers first write data associated with the set of first write commands from a memory of the host to the memory system, and writes the first write data into a first write destination block allocated for the first stream.
    Type: Grant
    Filed: September 24, 2021
    Date of Patent: May 16, 2023
    Assignee: Kioxia Corporation
    Inventor: Shinichi Kanno
  • SEMICONDUCTOR MEMORY DEVICE AND METHOD OF CONTROLLING THE SAME
    Publication number: 20230139971
    Abstract: A semiconductor memory device includes a plurality of detecting code generators configured to generate a plurality of detecting codes to detect errors in a plurality of data items, respectively, a plurality of first correcting code generators configured to generate a plurality of first correcting codes to correct errors in a plurality of first data blocks, respectively, each of the first data blocks containing one of the data items and a corresponding detecting code, a second correcting code generators configured to generate a second correcting code to correct errors in a second data block, the second data block containing the first data blocks, and a semiconductor memory configured to nonvolatilely store the second data block, the first correcting codes, and the second correcting code.
    Type: Application
    Filed: December 29, 2022
    Publication date: May 4, 2023
    Applicant: Kioxia Corporation
    Inventors: Shinichi KANNO, Hironori UCHIKAWA
  • MEMORY SYSTEM AND METHOD OF CONTROLLING NONVOLATILE MEMORY
    Publication number: 20230091792
    Abstract: According to one embodiment, when a total size of write data associated with one or more received write commands which specify one write destination block reaches a first write size, a controller executes a write operation for the one write destination block such that writing of write data having a first minimum write size to the one write destination block is completed, the write data having the first minimum write size being among pieces of write data stored in a write buffer of a memory included in a host. When a remaining capacity of the write buffer falls below a threshold, the controller writes, to a second block, write data corresponding to the selected write destination block, and causes the host to release a region of the write buffer storing the write data written to the second block.
    Type: Application
    Filed: March 8, 2022
    Publication date: March 23, 2023
    Applicant: Kioxia Corporation
    Inventor: Shinichi KANNO
  • STORAGE DEVICE THAT SECURES A BLOCK FOR A STREAM OR NAMESPACE AND SYSTEM HAVING THE STORAGE DEVICE
    Publication number: 20230082139
    Abstract: A storage device includes a nonvolatile semiconductor memory device including a plurality of physical blocks and a memory controller. The memory controller is configured to associate one or more physical blocks to each of a plurality of stream IDs, execute a first command containing a first stream ID received from a host, by storing write data included in the write IO in the one or more physical blocks associated with the first stream ID, and execute a second command containing a second stream ID received from the host, by selecting a first physical block that includes valid data and invalid data, transfer the valid data stored in the first physical block to a second physical block, and associate the first physical block from which the valid data has been transferred, with the second stream ID.
    Type: Application
    Filed: November 15, 2022
    Publication date: March 16, 2023
    Inventors: Daisuke HASHIMOTO, Shinichi KANNO
  • MEMORY SYSTEM AND METHOD FOR CONTROLLING NONVOLATILE MEMORY
    Publication number: 20230076210
    Abstract: According to one embodiment, a memory system includes a nonvolatile memory and a controller. The controller acquires, from a host, write data having the same first size as a data write unit of the nonvolatile memory and obtained by dividing write data associated with one write command having a first identifier indicating a first write destination block in a plurality of write destination blocks into a plurality of write data or combining write data associated with two or more write commands having the first identifier. The controller writes the acquired write data having the first size to the first write destination block by a first write operation.
    Type: Application
    Filed: November 7, 2022
    Publication date: March 9, 2023
    Applicant: KIOXIA CORPORATION
    Inventors: Shinichi KANNO, Hideki YOSHIDA, Naoki ESAKA, Hiroshi NISHIMURA
  • MEMORY SYSTEM AND METHOD
    Publication number: 20230075796
    Abstract: A memory system includes a controller and a flash memory including a plurality of first blocks. The controller writes a value having a first number of bits per memory cell to a plurality of second blocks, and writes a value having a second number of bits per memory cell to a plurality of third blocks among the first blocks. The second number is more than the first number. The controller writes data from a host device to the second blocks and transcribes valid data from the second blocks to the third blocks. The controller controls the number of second blocks in the first blocks according to an order of completion of the data writing to one or more third blocks and an amount of valid data stored in each of the one or more third blocks.
    Type: Application
    Filed: March 10, 2022
    Publication date: March 9, 2023
    Inventors: Takahiro KURITA, Shinichi KANNO
  • Memory system and method of controlling memory system
    Patent number: 11579773
    Abstract: According to one embodiment, a memory system includes a non-volatile semiconductor memory, a block management unit, and a transcription unit. The semiconductor memory includes a plurality of blocks to which data can be written in both the first mode and the second mode. The block management unit manages a block that stores therein no valid data as a free block. When the number of free blocks managed by the block management unit is smaller than or equal to a predetermined threshold value, the transcription unit selects one or more used blocks that stores therein valid data as transcription source blocks and transcribes valid data stored in the transcription source blocks to free blocks in the second mode.
    Type: Grant
    Filed: December 7, 2021
    Date of Patent: February 14, 2023
    Assignee: Toshiba Memory Corporation
    Inventors: Hiroshi Yao, Shinichi Kanno, Kazuhiro Fukutomi
  • SEMICONDUCTOR STORAGE DEVICE WITH VOLATILE AND NONVOLATILE MEMORIES TO ALLOCATE BLOCKS TO A MEMORY AND RELEASE ALLOCATED BLOCKS
    Publication number: 20230042619
    Abstract: A semiconductor storage device includes a first memory area configured in a volatile semiconductor memory, second and third memory areas configured in a nonvolatile semiconductor memory, and a controller which executes following processing. The controller executes a first processing for storing a plurality of data by the first unit in the first memory area, a second processing for storing data outputted from the first memory area by a first management unit in the second memory area, and a third processing for storing data outputted from the first memory area by a second management unit in the third memory area.
    Type: Application
    Filed: October 27, 2022
    Publication date: February 9, 2023
    Applicant: Kioxia Corporation
    Inventors: Hirokuni YANO, Shinichi KANNO, Toshikatsu HIDA, Hidenori MATSUZAKI, Kazuya KITSUNAI, Shigehiro ASANO
  • MEMORY SYSTEM AND INFORMATION PROCESSING SYSTEM
    Publication number: 20230038797
    Abstract: According to one embodiment, a memory system includes a nonvolatile memory and a memory controller configured to execute a patrol process, in response to a first command set from a host device. In the patrol process, the memory controller is configured to read first data from the nonvolatile memory, and not to output the first data to the host device.
    Type: Application
    Filed: October 24, 2022
    Publication date: February 9, 2023
    Applicant: Kioxia Corporation
    Inventors: Yasuhiko KUROSAWA, Naomi TAKEDA, Masanobu SHIRAKAWA, Yasuyuki USHIJIMA, Shinichi KANNO
  • Memory system and method for controlling nonvolatile memory
    Patent number: RE49508
    Abstract: According to one embodiment, a memory system classifies a plurality of nonvolatile memory dies connected to a plurality of channels, into a plurality of die groups such that each of the plurality of nonvolatile memory dies belongs to only one die group. The memory system performs a data write/read operation for one die group of the plurality of die groups in accordance with an I/O command from a host designating one of a plurality of regions including at least one region corresponding to each die group. The memory system manages a group of free blocks in the nonvolatile memory for each of the plurality of die group by using a plurality of free block pools corresponding to the plurality of die groups.
    Type: Grant
    Filed: November 2, 2020
    Date of Patent: April 25, 2023
    Assignee: Kioxia Corporation
    Inventor: Shinichi Kanno