Patents by Inventor Shinichi Kanno

Shinichi Kanno has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • MEMORY SYSTEM FOR CONTROLLING NONVOLATILE MEMORY
    Publication number: 20220350489
    Abstract: According to one embodiment, a memory system includes a nonvolatile memory including physical blocks, and a controller. The controller manages namespaces. The namespaces include at least a first namespace for storing a first type of data, and a second namespace for storing a second type of data having a lower update frequency than the first type of data. The controller allocates a first number of physical blocks as a physical resource for the first namespace, and allocates a second number of physical blocks as a physical resource for the second namespace, based on a request from a host device specifying an amount of physical resources to be secured for each of the namespaces.
    Type: Application
    Filed: July 20, 2022
    Publication date: November 3, 2022
    Applicant: KIOXIA CORPORATION
    Inventor: Shinichi KANNO
  • Memory system and method of controlling nonvolatile memory
    Patent number: 11487478
    Abstract: According to one embodiment, when a command executed in a nonvolatile memory is an erase/program command and when a cumulative weight value satisfies a condition that a first input is selected as an input of high priority, a memory system suspends execution of the erase/program command by transmitting a suspend command to the nonvolatile memory. The memory system repeats executing an operation of starting the execution of one read command of the first input and an operation of updating the cumulative weight by using the weight associated with the read command until read command no longer exists in the first input or until the condition that the cumulative weight is larger than the first value is not satisfied, and resumes the execution of the suspended erase/program command.
    Type: Grant
    Filed: March 16, 2021
    Date of Patent: November 1, 2022
    Assignee: Kioxia Corporation
    Inventor: Shinichi Kanno
  • MEMORY SYSTEM AND METHOD FOR CONTROLLING NONVOLATILE MEMORY
    Publication number: 20220342809
    Abstract: According to one embodiment, a memory system includes a nonvolatile memory including plural blocks each including plural pages, and a controller. When receiving a write request designating a first logical address and a first block number from the host, the controller determines a first location in a first block having the first block number to which data from the host should be written, and writes the data from the host to the first location in the first block. The controller notifies the host of either an in-block physical address indicative of the first location, or a group of the first logical address, the first block number and the first in-block physical address.
    Type: Application
    Filed: July 7, 2022
    Publication date: October 27, 2022
    Inventors: Hideki Yoshida, Shinichi Kanno
  • MEMORY SYSTEM AND METHOD OF CONTROLLING NONVOLATILE MEMORY AND FOR REDUCING A BUFFER SIZE
    Publication number: 20220334771
    Abstract: According to one embodiment, a memory system determines, for each of groups corresponding to streams, whether or not a length of write data associated with a set of write commands belonging to a same group reaches a minimum write size of a nonvolatile memory. When a length of write data associated with a set of write commands belonging to a first group corresponding to a first stream reaches the minimum write size, the memory system transfers the write data associated with the set of write commands belonging to the first group from a write buffer in a memory of the host to a first buffer in the memory system, and writes the write data transferred to the first buffer to a first write destination block corresponding to the first stream.
    Type: Application
    Filed: June 29, 2022
    Publication date: October 20, 2022
    Applicant: KIOXIA CORPORATION
    Inventor: Shinichi KANNO
  • Storage device that writes data from a host during garbage collection
    Patent number: 11474702
    Abstract: A memory system includes a controller, a buffer, and a nonvolatile memory including a plurality of blocks, wherein each of the blocks includes a plurality of pages and each of the pages includes a plurality of unit data portions. The controller is configured to carry out garbage collection by reading data from one or more pages of a target block of the garbage collection and selectively copying valid unit data portions included in the read data to another block, count a number of invalid unit data portions included in the read data, and accept, in the buffer, unit data portions from a host as write data, up to a number determined based on the counted number, during the garbage collection.
    Type: Grant
    Filed: July 27, 2020
    Date of Patent: October 18, 2022
    Assignee: KIOXIA CORPORATION
    Inventor: Shinichi Kanno
  • STORAGE SYSTEM AND INFORMATION PROCESSING SYSTEM FOR CONTROLLING NONVOLATILE MEMORY
    Publication number: 20220327050
    Abstract: According to one embodiment, a storage system includes a controller. The controller receives, from a host, a write command including a block address indicating a first block in a plurality of blocks, and a page address indicating a first page of the first block. The controller writes data designated by the write command to the first page of the first block. The controller notifies the host 2 of a page address indicating a latest readable page which is included in pages of the first block, the pages containing data which was written by the host before the designated data was written to the first page, the latest readable page having become readable by writing the designated data to the first page.
    Type: Application
    Filed: June 27, 2022
    Publication date: October 13, 2022
    Applicant: KIOXIA CORPORATION
    Inventor: Shinichi KANNO
  • Memory system and method for controlling nonvolatile memory
    Patent number: 11467955
    Abstract: According to one embodiment, a memory system manages a plurality of parallel units each including blocks belonging to different nonvolatile memory dies. When receiving from a host a write request designating a third address to identify first data to be written, the memory system selects one block from undefective blocks included in one parallel unit as a write destination block by referring to defect information, determines a write destination location in the selected block, and writes the first data to the write destination location. The memory system notifies the host of a first physical address indicative of both of the selected block and the write destination location, and the third address.
    Type: Grant
    Filed: April 27, 2021
    Date of Patent: October 11, 2022
    Assignee: Kioxia Corporation
    Inventor: Shinichi Kanno
  • Method for controlling write and read operations in the nonvolatile memory by a host, using an identifier for a region
    Patent number: 11461049
    Abstract: According to one embodiment, a memory system determines a write destination block and a write destination location in the write destination block to which write data is to be written, and notifies a host of an identifier of the write data, a block address of the write destination block, and an offset indicative of the write destination location. The memory system retrieves the write data from a write buffer of the host, and writes the write data to the write destination location. In a case where a read command to designate a physical address of first data is received before a write operation of the first data is finished, the memory system reads the first data from the write buffer of the host.
    Type: Grant
    Filed: January 8, 2021
    Date of Patent: October 4, 2022
    Assignee: Kioxia Corporation
    Inventor: Shinichi Kanno
  • STORAGE SYSTEM
    Publication number: 20220308971
    Abstract: According to one embodiment, a storage system includes a first storage including first nonvolatile memories storing data which is corrupted when data is read from the first nonvolatile memories, and a controller which controls the first storage. The controller reads data from a first nonvolatile memory at a first address, and determines that whether the read data is to be written back to the first storage or not.
    Type: Application
    Filed: June 14, 2022
    Publication date: September 29, 2022
    Inventors: Shinichi Kanno, Hideki Yoshida
  • INFORMATION PROCESSING SYSTEM FOR CONTROLLING STORAGE DEVICE
    Publication number: 20220300169
    Abstract: According to one embodiment, when it is determined that a first storage device of a plurality of storage devices is to be removed and an additional storage device is connected to a storage controller, the storage controller writes update data portions corresponding to data portions already written to the first storage device to any storage device selected from remaining one or more storage devices of the plurality of storage devices except for the first storage device and the additional storage device. Further, the storage controller writes update data portions corresponding to data portions already written to the remaining one or more storage devices to any storage device selected from the remaining one or more storage devices and the additional storage device.
    Type: Application
    Filed: June 7, 2022
    Publication date: September 22, 2022
    Applicant: Kioxia Corporation
    Inventor: Shinichi Kanno
  • MEMORY SYSTEM, INFORMATION PROCESSING SYSTEM, AND HOST DEVICE
    Publication number: 20220300172
    Abstract: A memory system may be connected to a host device. The memory system includes a nonvolatile memory and a controller configured to control the nonvolatile memory to reduce an amount of power consumption of the memory system based on a first instruction received from a host device connected to the memory system.
    Type: Application
    Filed: August 25, 2021
    Publication date: September 22, 2022
    Applicant: Kioxia Corporation
    Inventors: Takahiro KURITA, Shinichi KANNO, Yuki SASAKI
  • MEMORY SYSTEM
    Publication number: 20220300373
    Abstract: In general, according to one embodiment, a memory system includes: a memory; and a memory controller including an error detection code circuit configured to generate a first error detection code from first data and generate a second error detection code from second data containing the first error detection code. The memory controller is configured to: convert the first data and the second error detection code by a first method and generate third data; and write the third data into the memory.
    Type: Application
    Filed: September 9, 2021
    Publication date: September 22, 2022
    Applicant: Kioxia Corporation
    Inventor: Shinichi KANNO
  • MEMORY SYSTEM
    Publication number: 20220300182
    Abstract: According to one embodiment, a memory system includes a nonvolatile memory and a controller. The controller receives a first write request associated with first data from a host. In response to a lapse of first time since the reception of the first write request, the controller starts a write process of second data to the nonvolatile memory. The second data includes at least the first data. The controller transmits a first response to the first write request to the host in response to completion of the write process. The first time is time obtained by subtracting second time from third time designated by the host as a time limit of the transmission of the first response since the reception of the first write request.
    Type: Application
    Filed: September 7, 2021
    Publication date: September 22, 2022
    Applicant: Kioxia Corporation
    Inventors: Naoki ESAKA, Shinichi KANNO
  • MEMORY SYSTEM AND METHOD OF CONTROLLING NONVOLATILE MEMORY
    Publication number: 20220300214
    Abstract: According to one embodiment, a memory system manages a plurality of first weights that correspond to the plurality of queues, and a plurality of second weights that correspond to the plurality of queues. The memory system selects a queue of a largest or smallest second weight, of the plurality of queues, as a queue of a highest priority, and starts execution of a command stored in the selected queue. The memory system updates the second weight corresponding to the selected queue by subtracting the first weight corresponding to the selected queue from the second weight corresponding to the selected queue or by adding the first weight corresponding to the selected queue to the second weight corresponding to the selected queue.
    Type: Application
    Filed: June 9, 2022
    Publication date: September 22, 2022
    Applicant: Kioxia Corporation
    Inventor: Shinichi KANNO
  • Memory system for controlling nonvolatile memory
    Patent number: 11429277
    Abstract: According to one embodiment, a memory system includes a nonvolatile memory including physical blocks, and a controller. The controller manages namespaces. The namespaces include at least a first namespace for storing a first type of data, and a second namespace for storing a second type of data having a lower update frequency than the first type of data. The controller allocates a first number of physical blocks as a physical resource for the first namespace, and allocates a second number of physical blocks as a physical resource for the second namespace, based on a request from a host device specifying an amount of physical resources to be secured for each of the namespaces.
    Type: Grant
    Filed: September 2, 2020
    Date of Patent: August 30, 2022
    Assignee: Kioxia Corporation
    Inventor: Shinichi Kanno
  • Storage device and storage system including a memory to store a check code for an integrity check
    Patent number: 11422712
    Abstract: According to one embodiment, a storage device includes a stage on which a semiconductor wafer can be mounted, wherein data is capable of being read from the semiconductor wafer or data is capable of being written to the semiconductor wafer. The storage device further includes a plurality of probe pins for reading or writing data, and a controller connected the probe pins. The semiconductor wafer includes electrodes connectable to the probe pins, a first memory area that can store user data, and a second memory area that can store identification information for identification of the semiconductor wafer and a check code for checking integrity of the identification information. The controller is capable of reading the identification information and the check code from the second memory area.
    Type: Grant
    Filed: December 14, 2020
    Date of Patent: August 23, 2022
    Assignee: Kioxia Corporation
    Inventors: Yasuhito Yoshimizu, Takashi Fukushima, Tatsuro Hitomi, Arata Inoue, Masayuki Miura, Shinichi Kanno, Toshio Fujisawa, Keisuke Nakatsuka, Tomoya Sanuki
  • MEMORY SYSTEM AND METHOD OF CONTROLLING NONVOLATILE MEMORY
    Publication number: 20220261187
    Abstract: According to one embodiment, a memory system writes first write data into each non-defective physical block belonging to a first write destination block group. The memory system notifies a host of a first identifier of the first write data, an address specifying the first write destination block group, a first offset indicating a top write destination physical storage location in the first write destination block group in which the first write data is written, length of the first write data, and first bitmap information including a plurality of bits, each of the bits corresponding to each of physical blocks belonging to the first write destination block group and indicating whether or not the corresponding physical block is a defective block.
    Type: Application
    Filed: May 5, 2022
    Publication date: August 18, 2022
    Applicant: Kioxia Corporation
    Inventors: Shinichi KANNO, Takehiko KURASHIGE
  • Information processing device, information processing method, computer-readable storage medium, and information processing system
    Patent number: 11416152
    Abstract: According to one embodiment, an information processing device includes a characteristics monitoring unit, a determination unit, and a notification unit. The characteristics monitoring unit monitors characteristics information that indicates at least one of its performance and lifetime with respect to a storage device, and includes input/output characteristics. The determination unit determines, based on monitored characteristics information including the input/output characteristics, whether change instruction for changing characteristics is to be notified to the storage device. The notification unit notifies the storage device of the change instruction when the determination unit determines that the change instruction is to be notified.
    Type: Grant
    Filed: March 8, 2018
    Date of Patent: August 16, 2022
    Assignee: KIOXIA CORPORATON
    Inventors: Takeshi Ishihara, Shinichi Kanno
  • Memory system and method for controlling nonvolatile memory
    Patent number: 11416387
    Abstract: According to one embodiment, a memory system includes a nonvolatile memory including plural blocks each including plural pages, and a controller. When receiving a write request designating a first logical address and a first block number from the host, the controller determines a first location in a first block having the first block number to which data from the host should be written, and writes the data from the host to the first location in the first block. The controller notifies the host of either an in-block physical address indicative of the first location, or a group of the first logical address, the first block number and the first in-block physical address.
    Type: Grant
    Filed: June 12, 2020
    Date of Patent: August 16, 2022
    Assignee: Kioxia Corporation
    Inventors: Hideki Yoshida, Shinichi Kanno
  • Semiconductor memory device
    Patent number: RE49253
    Abstract: A CRC code is generated from an original data, a BCH code is generated with respect to the original data and the CRC code, and the original data, the CRC code, and the BCH code are recorded in pages selected from different planes of a plurality of memory chips. An RS code is generated from the original data across pages, a CRC code is generated with respect to the RS code, a BCH code is generated with respect to the RS code and the CRC code, and the RS code, the CRC code, the BCH code are recorded in a memory chip different from a memory chip including the original data. When reading data, error correction is performed on the original data by using the BCH code, and then CRC is calculated. If the number of errors is the number of errors that is correctable by erasure correction using the RS code, the original data is corrected by the erasure correction.
    Type: Grant
    Filed: September 12, 2016
    Date of Patent: October 18, 2022
    Assignee: Kioxia Corporation
    Inventor: Shinichi Kanno