Abstract: A device includes a stack above a substrate in a first direction perpendicular to a surface of the substrate, the stack including conductive layers; a semiconductor layer neighboring the stack in a second direction parallel to the surface of the substrate; a memory layer between the first stack and the semiconductor layer; memory cells between the conductive layers and the semiconductor layer; a first transistor connected between one end of the semiconductor layer in a third direction parallel to the surface of the substrate and crossing the second direction and a first interconnect in the first direction; and a second transistor connected between the other end of the semiconductor layer and a second interconnect in the first direction.

Abstract: According to one embodiment, a device includes a stack above a substrate in a first direction perpendicular to a surface of the substrate, the stack including conductive layers; a semiconductor layer neighboring the stack in a second direction parallel to the surface of the substrate; a memory layer between the first stack and the semiconductor layer; memory cells between the conductive layers and the semiconductor layer; a first transistor connected between one end of the semiconductor layer in a third direction parallel to the surface of the substrate and crossing the second direction and a first interconnect in the first direction; and a second transistor connected between the other end of the semiconductor layer and a second interconnect in the first direction.

Abstract: According to one embodiment, a semiconductor device includes a variable resistance circuit having first and second resistance elements connected in series, first and second switch elements connected in parallel with the first resistance element, and third and fourth switch elements connected in parallel with the second resistance element. In a case where the first resistance element is short-circuited, and the second resistance element is not short-circuited, one of the first and second switch elements is turned ON. In a case where the second resistance element is short-circuited, and the first resistance element is not short-circuited, one of the third and fourth switch elements is turned ON. In a case where the first and second resistance elements are short-circuited, the first to fourth switch elements are turned ON.

Abstract: According to one embodiment, a memory device includes a first address memory storing a first address; a controller which is based on a first interface which transmits a signal serially and outputs a first command in accordance with the first interface; and a memory which stores data in a nonvolatile manner, is based on the first interface, and stores received write data in an address based on the first address when the memory receives the first command.

Abstract: According to one embodiment, a semiconductor device includes a variable resistance circuit having first and second resistance elements connected in series, first and second switch elements connected in parallel with the first resistance element, and third and fourth switch elements connected in parallel with the second resistance element. In a case where the first resistance element is short-circuited, and the second resistance element is not short-circuited, one of the first and second switch elements is turned ON. In a case where the second resistance element is short-circuited, and the first resistance element is not short-circuited, one of the third and fourth switch elements is turned ON. In a case where the first and second resistance elements are short-circuited, the first to fourth switch elements are turned ON.

Abstract: According to one embodiment, a memory device includes a first address memory storing a first address; a controller which is based on a first interface which transmits a signal serially and outputs a first command in accordance with the first interface; and a memory which stores data in a nonvolatile manner, is based on the first interface, and stores received write data in an address based on the first address when the memory receives the first command.

Abstract: According to one embodiment, a memory device includes: a nonvolatile memory that stores data according to a write access; an address memory that stores a first address described with a gray code; a first counter that counts up the first address for each write access, generates a second address as the count-up result, and supplies the second address to the nonvolatile memory; a rounding circuit configured to calculate a third address that is equal to or larger than a final output of the first counter and larger than the first address by one or a power of two after a series of write accesses is completed; and a controller that rewrites the third address in the address memory.

Abstract: According to one embodiment, a memory device includes a first address memory storing a first address; a controller which is based on a first interface which transmits a signal serially and outputs a first command in accordance with the first interface; and a memory which stores data in a nonvolatile manner, is based on the first interface, and stores received write data in an address based on the first address when the memory receives the first command.

Abstract: According to one embodiment, a memory device includes: a nonvolatile memory that stores data according to a write access; an address memory that stores a first address described with a gray code; a first counter that counts up the first address for each write access, generates a second address as the count-up result, and supplies the second address to the nonvolatile memory; a rounding circuit configured to calculate a third address that is equal to or larger than a final output of the first counter and larger than the first address by one or a power of two after a series of write accesses is completed; and a controller that rewrites the third address in the address memory.

Abstract: According to one embodiment, a resistance-change memory includes bit lines running in a first direction, word lines running in a second direction, and a memory cell array includes memory cells each includes a selection transistor and a variable resistance element. In a layout of first to fourth variable resistance elements arranged in order in the first direction, the first variable resistance element and the second variable resistance element sandwich one word line therebetween, the third variable resistance element and the fourth variable resistance element sandwich one word line therebetween, a first pair includes the first and second variable resistance elements and a second pair includes the third and fourth variable resistance elements sandwich two word lines therebetween, and a column is constructed by repeating the layout in the first direction.

Abstract: A power supply circuit has a constant voltage circuit, a first MOS transistor, a second MOS transistor, a third MOS transistor, a first voltage dividing circuit that outputs a first divided voltage obtained by dividing the voltage of the output terminal by a first voltage dividing ratio, and a first differential amplifier circuit which is fed with a reference voltage and the first divided voltage and has an output connected to a gate of the second MOS transistor. The first differential amplifier circuit outputs a signal to turn on the second MOS transistor when the first divided voltage is higher than the reference voltage, and the first differential amplifier circuit outputs a signal to turn off the second MOS transistor when the first divided voltage is lower than the reference voltage.

Abstract: According to the present invention, a semiconductor storage device includes: a first memory cell array including: a first bit line; a first plate line; a first memory cell; a first sense amplifier; a first reference power line configured to supply first reference voltage; a first switching module configured to control a connection between the first reference power line and the first bit line; a second memory cell array including: a second bit line; a second plate line; a second memory cell; a second sense amplifier; a second reference power line configured to supply second reference voltage; a second switching module configured to control a connection between the second reference power line and the second bit line; a control module configured to generate the control signal so as to control a time difference between the first memory cell array and the second memory cell array in precharge operation.

Abstract: A ferroelectric memory of an embodiment of the present invention includes a plurality of units, in each of which a ferroelectric capacitor and a transistor are connected to each other in parallel.

Abstract: According to one embodiment, a resistance-change memory includes bit lines running in a first direction, word lines running in a second direction, and a memory cell array includes memory cells each includes a selection transistor and a variable resistance element. In a layout of first to fourth variable resistance elements arranged in order in the first direction, the first variable resistance element and the second variable resistance element sandwich one word line therebetween, the third variable resistance element and the fourth variable resistance element sandwich one word line therebetween, a first pair includes the first and second variable resistance elements and a second pair includes the third and fourth variable resistance elements sandwich two word lines therebetween, and a column is constructed by repeating the layout in the first direction.

Abstract: A ferroelectric semiconductor storage device includes: a block having a plurality of ferroelectric memory cells connected in series, each of the plurality of ferroelectric memory cells including a ferroelectric capacitor and a transistor connected in parallel to both ends of the ferroelectric capacitor; a word line connected to each of the transistors; a selection transistor connected to one end of the block; a bit line connected to the selection transistor; and a plate line connected to the other end of the block. The number of ferroelectric memory cells connected in each block in the ferroelectric semiconductor storage device is odd.

Abstract: According to an aspect of the present invention, there is provided a voltage step-down circuit including: a first NMOS connected between an external and an internal power-supply voltages through a PMOS turned ON during an active state and turned OFF during a standby state; a second NMOS connected between the external and the internal power-supply voltages; and a current control circuit that sinks a current from the internal power-supply voltage to a ground level for a certain period of time after an operation state is switched from the active state to the standby state.

Abstract: A semiconductor memory device includes a parity generation circuit which generates a parity bit corresponding to a first number of data bits, a memory cell array including memory cells, and having first and second areas, the first area storing data, the second area storing the parity bit, a syndrome generation circuit which generates a syndrome bit for correcting an error in read data which are read from the first area, has the first number of data bits and corresponds to the parity bit read from the second area, based on the parity bit and the read data, and a parity correction circuit which corrects the parity bit generated by the parity generation circuit. The parity generation circuit generates the parity bit for data which includes input data and a part of the read data.

Abstract: A discharge order control circuit includes a pool circuit a delay circuit and a discharge unit to control a discharge order of internal power supplies. The pool circuit stores electric charges provided from a potential of an external power supply. The delay circuit operates on the electric charges stored in the pool circuit and delays a discharge signal generated when potential of the external power supply is lowered to a predetermined potential level. The delay circuit includes an inverter array having a plurality of stages each containing an inverter. The plurality of stages include a final stage that outputs the delayed discharge signal. Only the inverter of the final stage generates an RC delay.

Abstract: A ferroelectric memory of an embodiment of the present invention includes a plurality of units, in each of which a ferroelectric capacitor and a transistor are connected to each other in parallel.

Abstract: A memory includes a cell block comprises memory cells connected in series; block select transistors connected to one ends of the cell blocks; bit lines; plate lines; a sense amplifier comprises an N-type sensor and a P-type sensor, the N-type sensor applying a low-level potential to the bit line, and the P-type sensor applying a high-level potential to the bit line; local data lines corresponding to the bit lines respectively and transmitting data; and a column select transistor between one of the bit lines and one of the local data lines; wherein either one of the P-type sensor and the N-type sensor is set in an inactive state with the other one of the P-type sensor and the N-type sensor being in an active state, when the column select transistor is turned on to transmit the data to be written from the local data line to the bit line.