Abstract: A memory includes a cell block including ferroelectric capacitors and cell transistors, the cell block being configured by unit cells formed by the ferroelectric capacitor and the cell transistor; a dummy block configured by having one end of dummy strings connected in common, the dummy string being formed by connecting in series dummy transistors; dummy word lines connected to gates of the dummy transistors; a dummy block selection transistor connected between the dummy block and a bit line; wherein in a data read operation, a dummy-word-line driver sets the dummy transistors to a conductive state, the number of the dummy transistors in the conductive state depends on the number of the cell transistors present between the unit cell to be read and the bit line, and the dummy transistors in a conductive state are conductive to the bit line.

Abstract: According to the present invention, a semiconductor storage device includes: a first memory cell array including: a first bit line; a first plate line; a first memory cell; a first sense amplifier; a first reference power line configured to supply first reference voltage; a first switching module configured to control a connection between the first reference power line and the first bit line; a second memory cell array including: a second bit line; a second plate line; a second memory cell; a second sense amplifier; a second reference power line configured to supply second reference voltage; a second switching module configured to control a connection between the second reference power line and the second bit line; a control module configured to generate the control signal so as to control a time difference between the first memory cell array and the second memory cell array in precharge operation.

Abstract: A semiconductor memory device according to an aspect of the present invention includes a memory cell array that includes a ferroelectric capacitor and a selection transistor that selects a column of the memory cell array and connects the selected column to a bit line. A plate line applies a potential for reading or writing data to the ferroelectric capacitor. A sense amplifier circuit compares and amplifies a signal read from the ferroelectric capacitor to the bit line. A plate line control circuit controls a potential of the plate line synchronously with a clock signal.

Abstract: A power supply circuit has a constant voltage circuit, a first MOS transistor, a second MOS transistor, a third MOS transistor, a first voltage dividing circuit that outputs a first divided voltage obtained by dividing the voltage of the output terminal by a first voltage dividing ratio, and a first differential amplifier circuit which is fed with a reference voltage and the first divided voltage and has an output connected to a gate of the second MOS transistor. The first differential amplifier circuit outputs a signal to turn on the second MOS transistor when the first divided voltage is higher than the reference voltage, and the first differential amplifier circuit outputs a signal to turn off the second MOS transistor when the first divided voltage is lower than the reference voltage.

Abstract: This disclosure concerns a memory including: unit cells having ferroelectric capacitors and cell transistors; two depletion transistors and two enhancement transistors serially connected between two adjacent unit series configurations configured by serially connecting the unit cells; four selective lines respectively connected to the gates of the two enhancement transistors and the two depletion transistors; word lines connected to the gates of the cell transistors; a bit line connected to the unit series configuration via at least one of the enhancement transistors and the depletion transistors; and a bit line contact connecting the bit line to at least one of the enhancement transistors and the depletion transistors, wherein in two of adjacent bit lines, the bit line contact connected to one of the two adjacent bit lines and the bit line contact connected to the other bit line are opposed to each other with respect to one of the selective lines.

Abstract: According to the present invention, there is provided a semiconductor device including a power supply circuit which receives an external power supply voltage supplied, and outputs an internal power supply voltage not higher than the external power supply voltage; a system module which receives the internal power supply voltage, and performs a predetermined operation; and a performance monitor circuit which measures a processing speed of said system module when the internal power supply voltage is applied, and, on the basis of the processing speed, outputs a first control signal which requests to set the external power supply voltage at a first level, and a second control signal which requests said power supply circuit to set the internal power supply voltage at a second level. The power supply circuit outputs the internal power supply voltage having the second level on the basis of the second control signal applied thereto.

Abstract: According to an aspect of the present invention, there is provided a voltage step-down circuit including: a first NMOS connected between an external and an internal power-supply voltages through a PMOS turned ON during an active state and turned OFF during a standby state; a second NMOS connected between the external and the internal power-supply voltages; and a current control circuit that sinks a current from the internal power-supply voltage to a ground level for a certain period of time after an operation state is switched from the active state to the standby state.

Abstract: A semiconductor integrated circuit comprising: a power controller which outputs a voltage select signal for selecting one of at least two types of voltages; a power supply voltage controller which generates and outputs a power supply voltage at an arbitrary voltage change rate on the basis of the voltage select signal; and a circuit portion which receives the power supply voltage and performs processing, wherein said circuit portion keeps operating while said power supply voltage controller is outputting the power supply voltage generated at the arbitrary voltage change rate.

Abstract: A ferroelectric semiconductor storage device includes: a block having a plurality of ferroelectric memory cells connected in series, each of the plurality of ferroelectric memory cells including a ferroelectric capacitor and a transistor connected in parallel to both ends of the ferroelectric capacitor; a word line connected to each of the transistors; a selection transistor connected to one end of the block; a bit line connected to the selection transistor; and a plate line connected to the other end of the block. The number of ferroelectric memory cells connected in each block in the ferroelectric semiconductor storage device is odd.

Abstract: A semiconductor memory comprising a memory cell array, a spare memory cell array, a spare data replacing circuit, a syndrome computing circuit, and an ECC circuit is disclosed. The data in the memory cell replaced with a memory cell in the spare memory cell array is set to 0 and then the syndromes of the data read from the memory cell array are calculated. In parallel with the syndrome calculation, the data in the memory cell of the memory cell array is replaced with the data read from a spare memory cell. Then, the syndromes of the data read from the memory cell in the spare memory cell array are calculated. The calculated syndromes and the output of the spare data replacing circuit are supplied to the ECC circuit, which corrects the error if there is a 1-bit error in the data read from the memory cell array.

Abstract: A ferroelectric memory device includes a cell block, a bit line, and a plate line. The cell block includes a ferroelectric capacitor and a transistor switch. The bit line applies a voltage to one electrode of the ferroelectric capacitor. The plate line applies a voltage to the other electrode of the ferroelectric capacitor. In a read operation of data, a first voltage is applied to the plate line. In a write operation of data, a second voltage different from the first voltage is applied to the plate line, and a voltage which is higher or lower than the second voltage is applied to the bit line.

Abstract: A semiconductor memory device includes a memory cell including a ferroelectric capacitor and a cell transistor and storing binary data at a first potential level and a second potential level which is higher than the first potential level, a bit line which reads the binary data from the memory cell, a correction circuit which corrects an error of the binary data read from the memory cell via the bit line, and a setting circuit which sets to the first potential a potential of the bit line connected to the memory cell from which at least the binary data is read, after the binary data is transferred to the correction circuit. The device further includes a control circuit which controls the potential of the bit line connected to the memory cell from which the binary data is read, in accordance with a result of error correction of the binary data.

Abstract: A first inverter circuit comprises a first transistor in which one end of a current path is grounded, and a second transistor in which one end of a current path is connected to the other end of the current path of the first transistor. A first signal is supplied to gates of the first and second transistors. A third transistor is connected between the other end of the current path of the second transistor and a node to which a second voltage higher than the first voltage is supplied. A control signal constituted of one of the ground potential and the second voltage is supplied to a gate of the third transistor behind a change of a first signal. A second signal constituted of one of the ground potential and the second voltage is output from an output terminal of the first inverter circuit.

Abstract: A semiconductor memory comprising a memory cell array, a spare memory cell array, a spare data replacing circuit, a syndrome computing circuit, and an ECC circuit is disclosed. The data in the memory cell replaced with a memory cell in the spare memory cell array is set to 0 and then the syndromes of the data read from the memory cell array are calculated. In parallel with the syndrome calculation, the data in the memory cell of the memory cell array is replaced with the data read from a spare memory cell. Then, the syndromes of the data read from the memory cell in the spare memory cell array are calculated. The calculated syndromes and the output of the spare data replacing circuit are supplied to the ECC circuit, which corrects the error if there is a 1-bit error in the data read from the memory cell array.

Abstract: A booster circuit includes a first booster unit having a first output terminal from which a boosted voltage is output. The first output terminal is connected to an external output terminal. A second booster unit has a second output terminal from which a boosted voltage is output. The second output terminal is connected to the external output terminal. A control circuit outputs a first control signal used to control the operation of the first booster unit and a second control signal used to control the operation of the second booster unit. Further, the control circuit controls the first and second control signals so that a transition between the operative state and the non-operative state of the first booster unit and a transition between the operative state and the non-operative state of the second booster unit will be made at different timings according to output voltage of the external output terminal.

Abstract: A discharge order control circuit includes a pool circuit, a delay circuit and a discharge unit to control a discharge order of internal power supplies. The pool circuit stores electric charges provided from a potential of an external power supply. The delay circuit operates on the electric charges stored in the pool circuit and delays a discharge signal generated when potential of the external power supply is lowered to a predetermined potential level. The delay circuit includes an inverter array having a plurality of stages each containing an inverter. The plurality of stages include a final stage that outputs the delayed discharge signal. Only the inverter of the final stage generates an RC delay. The discharge unit discharges a internal power supply included in the internal power supplies in response to the delayed discharge signal output from the inverter of the final stage of the inverter array.

Abstract: A semiconductor device includes signal lines over which signals are transferred, and a drive circuit driving the signal lines in operating modes. The operating modes include a dynamic operation mode in which the signal lines are precharged, and a static operation mode in which the signal lines are not precharged.

Abstract: A plurality of ferroelectric memory cells is arrayed. One terminal of each memory cells arrayed in the same column is connected in common to a first bit line. A gate of a transistor of memory cells arrayed in the same row is connected in common to a word line. The other terminal of each of memory cells arrayed in the same column or the same row is connected in common to a cell plate line. A second bit line is connected with a reference voltage supply circuit. The first and second bit lines are connected with a data read circuit. The data read circuit includes a sense amplifier and a current mirror circuit having a pair of current input node connected to the first and second bit lines, and carrying the same current flowing through one of the first and second bit line to the other bit line.

Abstract: A first logic circuit has its supply voltage controlled. A second logic circuit operates in response to an external clock signal. An adjustment circuit includes a first delay circuit supplied with the external clock signal, and a detection circuit which detects a skew between timing of a first clock signal output from the first logic circuit and a second clock signal output from the second logic circuit section. The adjustment circuit adjusts the delay time of the first delay circuit according to the result of the detection by the detection circuit and applies an output signal of the first delay circuit to the first logic circuit as a third clock signal.

Abstract: An integrated circuit device comprises a memory cell block, a word line selecting circuit and a driving circuit. The memory cell block comprises memory cells connected in series. The memory cell comprises a cell transistor including a gate which is connected to a word line, and a ferroelectric capacitor connected to terminals of the cell transistor. The word line selecting circuit successively selects the word lines connected to the cell transistors in the memory cells in the memory cell block in response to address signals successively input from an outside of the device, during an active cycle. The driving circuit applies a given voltage between ends of a current path provided of the cell transistors in the memory cells in the memory cell block, during a time period for which the word lines connected to the cell transistors are successively selected by the word line selecting circuit.