Abstract: The present invention provides a DRAM in which a first repetitive unit including a plurality of decoders for selecting a plurality of word lines and a second repetitive unit having the same arrangement as that of the first repetitive unit are arranged symmetrically with respect a boundary region therebetween. The first and second repetitive units have a wire and a contact located on a boundary portion therebetween in common.

Abstract: A semiconductor integrated circuit device includes connected TC unit type ferroelectric memory which includes series connected memory cells each having a cell transistor having a source terminal and a drain terminal and a ferroelectric capacitor inbetween the two terminals, a first power supply circuit which generates a first power supply potential supplied to the gate of the cell transistor when the cell transistor is in a standby state, and a second power supply circuit. The second power supply circuit generates a second power supply potential supplied to the source or drain of the cell transistor and starts operating following the start-up of the first power supply circuit after a power-on.

Abstract: A power supply circuit includes a transistor, a variable resistance circuit, a second resistance, and an operational amplifier. The variable resistance circuit includes a plurality of first resistances. The plurality of first resistances are selected in response to control signals. The selected first resistances are connected in series, the unselected first resistances are connected to a ground voltage. The second resistance is connected between the variable resistance circuit and the ground voltage. The operational amplifier compares the voltage of the other end of the variable resistance circuit with a reference voltage and feeds a signal indicating a comparison result back to the gate of the transistor.

Abstract: Read amplifiers are arranged adjacent to each other near the center of an amplifier string, thereby shortening the distances of read data paths from sense amplifiers to the read amplifiers. This can suppress the delay of a read operation caused by the wiring resistance of a data bus line, to realize high-speed read and write operations by reducing the wiring load on data paths in data read and write.

Abstract: There is provided a semiconductor memory device which comprises a plurality of memory cells, a plurality of bit lines connected with the plurality of memory cells, a plurality of word lines connected with the plurality of memory cells, a plurality of data line pairs, a plurality of transfer gates for effecting controlled connection of the plurality of bit lines with the plurality of data lines, a plurality of column select lines for controlling conductibility of the plurality of the transfer gates, and a column select line drive circuit for simultaneously selecting and driving at least two of the plurality of column select lines corresponding to one-time column address input from the outside of the chip.

Abstract: A semiconductor device includes signal lines over which signals are transferred, and a drive circuit driving the signal lines in operating modes. The operating modes include a dynamic operation mode in which the signal lines are precharged, and a static operation mode in which the signal lines are not precharged.

Abstract: Read amplifiers are arranged adjacent to each other near the center of an amplifier string, thereby shortening the distances of read data paths from sense amplifiers to the read amplifiers. This can suppress the delay of a read operation caused by the wiring resistance of a data bus line, to realize high-speed read and write operations by reducing the wiring load on data paths in data read and write.

Abstract: The present invention provides a DRAM in which a first repetitive unit including a plurality of decoders for selecting a plurality of word lines and a second repetitive unit having the same arrangement as that of the first repetitive unit are arranged symmetrically with respect a boundary region therebetween. The first and second repetitive units have a wire and a contact located on a boundary portion therebetween in common.

Abstract: The present invention provides a DRAM in which a first repetitive unit including a plurality of decoders for selecting a plurality of word lines and a second repetitive unit having the same arrangement as that of the first repetitive unit are arranged symmetrically with respect a boundary region therebetween. The first and second repetitive units have a wire and a contact located on a boundary portion therebetween in common.

Abstract: A semiconductor memory device includes a semiconductor substrate and a plurality of element regions formed in the semiconductor, wherein at least one column gate and at least one equalizer are formed as a set in one element region of the plurality of element regions. In one embodiment, a set of a column gate and an equalizer share a diffusion layer with an adjacent set of a column gate and an equalizer. In a second embodiment, a gate electrode of the equalizer is disposed to divide a diffusion layer into six regions. In other embodiments, the equalizer is surrounded by at least a gate electrode of a column gate. In yet other embodiments, the sets of column gates and equalizers are disposed parallel to a bit line.

Abstract: The present invention provides a DRAM in which a first repetitive unit including a plurality of decoders for selecting a plurality of word lines and a second repetitive unit having the same arrangement as that of the first repetitive unit are arranged symmetrically with respect a boundary region therebetween. The first and second repetitive units have a wire and a contact located on a boundary portion therebetween in common.

Abstract: The present invention provides a DRAM in which a first repetitive unit including a plurality of decoders for selecting a plurality of word lines and a second repetitive unit having the same arrangement as that of the first repetitive unit are arranged symmetrically with respect a boundary region therebetween. The first and second repetitive units have a wire and a contact located on a boundary portion therebetween in common.

Abstract: This invention provides a sense amplifier circuit capable of determining an output with small power consumption at high speeds and simplifying a control signal. The sources of a pair of driver nMOS transistors in a first amplifier are connected to VSS via an activation nMOS transistor. An output from the first amplifier is directly input to input/output nodes of a second, latch amplifier. The sources of a pair of nMOS transistors in the second amplifier are connected to VSS via an activation nMOS transistor. The input/output nodes are precharged to VCC by a precharge circuit in a standby state. The activation nMOS transistors are simultaneously controlled by a clock signal, and the first and second amplifiers are simultaneously activated to sense, amplify, and latch the potential difference between input/output nodes.

Abstract: A semiconductor memory device comprises a plurality of memory banks each having a plurality of memory cell arrays and a plurality of sense amplifiers such that the memory cell arrays and the sense amplifiers are alternately disposed in a first direction, the memory banks being disposed in a second direction perpendicular to the first direction, a plurality of row decoders respectively provided in the first direction for the plurality of memory banks, a column decoder provided in the second direction with respect to the plurality of memory banks, a plurality of first data lines respectively provided in the second direction for the plurality of memory banks, and connected with the plurality of sense amplifiers in accordance with a signal outputted from the column decoder, a plurality of second data lines provided in the second direction, penetrating through the plurality of memory banks, and shared by the plurality of first data lines disposed for the plurality of memory banks, and a plurality of switching elem

Abstract: A semiconductor memory device with a semiconductor substrate and a plurality of element regions formed in the semiconductor is shown. The semiconductor memory device further includes at least one column gate and at least one equalizer in which they are formed as a set in at least one of the element regions.

Abstract: There is provided a semiconductor memory device which comprises a plurality of memory cells, a plurality of bit lines connected with the plurality of memory cells, a plurality of word lines connected with the plurality of memory cells, a plurality of data line pairs, a plurality of transfer gates for effecting controlled connection of the plurality of bit lines with the plurality of data lines, a plurality of column select lines for controlling conductibility of the plurality of the transfer gates, and a column select line drive circuit for simultaneously selecting and driving at least two of the plurality of column select lines corresponding to one-time column address input from the outside of the chip.

Abstract: A dynamic semiconductor memory device can suppress an increase in the amount of current in the stand-by state even if the defect of short circuit occurs between a bit line and a word line by using a current limiting element controlled by a column selection line, for limiting the precharge current for the bit line.

Abstract: This invention discloses the layout of word line driving circuits for driving word lines. A semiconductor memory device includes a memory cell array having a bit line, n memory cells connected to the bit line, and n word lines respectively connected to the n memory cells. The semiconductor memory device further includes n/2 first word line driving circuits for driving n/2 word lines of the n word lines, and n/2 second word line driving circuits for driving the remaining n/2 word lines of the n word lines. The second word line driving circuits are arranged at the positions where the second word line driving circuits face the first word line driving circuits via the memory cell array.

Abstract: A semiconductor memory device having a sense amplifier, comprises an n-type sense amplifier formed of an nMOS transistor with a source connected to a bit line and a gate connected to an inverted bit line, and an nMOS transistor with a source connected to the inverted bit line and a gate connected to the bit line. In activating the n-type sense amplifier, the voltage of a control signal line is set to a voltage Vss2 lower than a ground voltage Vss. In restoring data in a capacitor of a memory cell, the voltage of the control signal line is set to the ground voltage Vss. With this setting, the sense amplifier can operate at an ultra-low voltage and can ensure a satisfactory operation margin.

Abstract: An OR circuit generates a spare word line group selection signal based on output signals of address coincidence detection circuits and the OR circuit generates an upper/low-order selection signal. A spare word line selecting signal generation circuit generates a spare word line selection signal based on the upper/low-order selection signal and common word line selection signal and a word line driving circuit substitutes the spare word line or lines in a redundancy memory cell array in the unit of lines smaller than the number of word lines constructing one word line group in the memory cell array according to the spare word line group selection signal and spare word line selection signal.