Patents by Inventor Shinji Yoshida

Shinji Yoshida has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10509341
    Abstract: A charged positive toner having a positive polarity that attaches to a charge roller is moved from the charge roller to a photosensitive drum, and the positive toner is transferred to an intermediate transfer belt at a primary transfer portion at which a primary-transfer power supply forms an electric potential having a negative polarity. The primary-transfer power supply forms an electric potential having the positive polarity at the primary transfer portion, and the positive toner transferred to the intermediate transfer belt is moved together with the intermediate transfer belt and is collected by the charge roller in contact with a downstream photosensitive drum.
    Type: Grant
    Filed: May 8, 2018
    Date of Patent: December 17, 2019
    Assignee: Canon Kabushiki Kaisha
    Inventors: Takayuki Tanaka, Shinji Katagiri, Tsuguhiro Yoshida, Shuichi Tetsuno, Takahiro Ikeda
  • Publication number: 20190376167
    Abstract: The steel material according to the present disclosure contains a chemical composition consisting of, in mass %, C: more than 0.50 to 0.80%, Si: 0.05 to 1.00%, Mn: 0.05 to 1.00%, P: 0.025% or less, S: 0.0100% or less, Al: 0.005 to 0.100%, Cr: 0.20 to 1.50%, Mo: 0.25 to 1.50%, Ti: 0.002 to 0.050%, B: 0.0001 to 0.0050%, N: 0.002 to 0.010% and O: 0.0100% or less, with the balance being Fe and impurities. The steel material contains an amount of dissolved C within a range of 0.010 to 0.060 mass %. The steel material also has a yield strength within a range of 965 to 1069 MPa, and a yield ratio of the steel material is 90% or more.
    Type: Application
    Filed: January 22, 2018
    Publication date: December 12, 2019
    Inventors: Shinji Yoshida, Yuji Arai, Atsushi Soma, Hiroki Kamitani
  • Publication number: 20190371799
    Abstract: A memory cell includes a memory gate structure, a first select gate structure, and a second select gate structure. In the memory gate structure, a lower memory gate insulating film, a charge storage layer, an upper memory gate insulating film, and a metal memory gate electrode are stacked in this order. The first select gate structure includes a metal first select gate electrode along a first sidewall spacer provided on a sidewall of the memory gate structure. The second select gate structure includes a metal second select gate electrode along a second sidewall spacer provided on another sidewall of the memory gate structure. Thus, the metal memory gate electrode, the metal first select gate electrode, and the metal second select gate electrode can be formed of a same metallic material as a metal logic gate electrode, permitting the memory cell to be formed together with the metal logic gate electrode.
    Type: Application
    Filed: August 14, 2019
    Publication date: December 5, 2019
    Inventors: Shoji YOSHIDA, Fukuo OWADA, Daisuke OKADA, Yasuhiko KAWASHIMA, Shinji YOSHIDA, Kazumasa YANAGISAWA, Yasuhiro TANIGUCHI
  • Publication number: 20190354527
    Abstract: A database management system (DBMS) generates a query execution plan including information representing one or more database (DB) operations necessary for executing a query and executes the query based on the query execution plan. In the execution of the query, the DBMS dynamically generates a task for executing a DB operation and executes the dynamically generated task. The DBMS executes a task in a plurality of threads executed by a processor core.
    Type: Application
    Filed: August 5, 2019
    Publication date: November 21, 2019
    Inventors: Akira SHIMIZU, Seisuke TOKUDA, Michiko YOSHIDA, Kazuhiko MOGI, Shinji FUJIWARA, Nobuo KAWAMURA, Masaru KITSUREGAWA, Kazuo GODA
  • Publication number: 20190332041
    Abstract: An intermediate transfer belt includes a surface layer with a solid lubricant added therein on an outer peripheral surface side in abutment with a photosensitive drum and a cleaning blade in a thickness direction. Further, the surface layer includes a plurality of grooves formed along a movement direction of the intermediate transfer belt in a width direction of the intermediate transfer belt. The intermediate transfer belt including the grooves satisfies J×(1/K)×L×(Q/?P)/((Q/?P)+(100/?A))<240.
    Type: Application
    Filed: April 12, 2019
    Publication date: October 31, 2019
    Inventors: Tsuguhiro Yoshida, Shinji Katagiri, Takayuki Tanaka
  • Publication number: 20190316653
    Abstract: A bending meshing type gear device includes an internal gear, an external gear which meshes with the internal gear, a wave generator which bends and deforms the external gear, and a wave generator bearing which is disposed between the wave generator and the external gear, in which the wave generator bearing has a rolling body and an outer ring, and a minimum inner peripheral length of the external gear is larger than a maximum outer peripheral length of the outer ring.
    Type: Application
    Filed: April 4, 2019
    Publication date: October 17, 2019
    Inventors: Shinji Yoshida, Toshiya Nagumo, Masayuki Ishizuka
  • Publication number: 20190317431
    Abstract: With respect to a width direction of an intermediate transfer belt perpendicular to a movement direction thereof, the width of a blade is larger than the width of an image forming region in which a toner image is able to be primarily transferred from a photosensitive drum to the intermediate transfer belt. Moreover, grooves are formed on the surface of the intermediate transfer belt, and, with respect to the width direction of the intermediate transfer belt, a dynamic friction coefficient in a first region that is in contact with the end portion side of the blade is smaller than a dynamic friction coefficient in a second region that is in contact with the central portion side of the blade.
    Type: Application
    Filed: April 9, 2019
    Publication date: October 17, 2019
    Inventors: Shohei Ishio, Keisuke Ishizumi, Takayuki Tanaka, Tsuguhiro Yoshida, Shinji Katagiri
  • Patent number: 10431589
    Abstract: A memory cell includes a memory gate structure, a first select gate structure, and a second select gate structure. In the memory gate structure, a lower memory gate insulating film, a charge storage layer, an upper memory gate insulating film, and a metal memory gate electrode are stacked in this order. The first select gate structure includes a metal first select gate electrode along a first sidewall spacer provided on a sidewall of the memory gate structure. The second select gate structure includes a metal second select gate electrode along a second sidewall spacer provided on another sidewall of the memory gate structure. Thus, the metal memory gate electrode, the metal first select gate electrode, and the metal second select gate electrode can be formed of a same metallic material as a metal logic gate electrode, permitting the memory cell to be formed together with the metal logic gate electrode.
    Type: Grant
    Filed: July 21, 2016
    Date of Patent: October 1, 2019
    Assignee: FLOADIA CORPORATION
    Inventors: Shoji Yoshida, Fukuo Owada, Daisuke Okada, Yasuhiko Kawashima, Shinji Yoshida, Kazumasa Yanagisawa, Yasuhiro Taniguchi
  • Publication number: 20190291239
    Abstract: A grinding apparatus includes a table having a holding surface, a grinding unit grinding a wafer held on the holding surface, a notification portion notifying an operator of information, an imaging unit illuminating a ground surface of the wafer which is held and ground with an illumination and imaging the ground surface, a detecting portion detecting a cross line in an imaged picture, a memory storing an X-axis and Y-axis coordinate position of an intersection point of the cross line detected, a spotlight illuminating the holding surface at the X-axis and Y-axis coordinate position stored, and a controller causing the notification portion to notify the operator that the cross line has been detected and stopping grinding operations of the grinding apparatus.
    Type: Application
    Filed: March 19, 2019
    Publication date: September 26, 2019
    Inventor: Shinji YOSHIDA
  • Publication number: 20190296030
    Abstract: When a memory cell (MC) is downsized by reducing the distance between a drain region (12a) and a source region (12b) on the surface of a fin (S2) with a high impurity concentration inside the fin (S2), the shape of the fin (S2) can be set such that a potential difference between a memory gate electrode (MG) and the fin (S2) is reduced to suppress the occurrence of disturbance. Accordingly, the memory cell (MC) achieves downsizing and suppression of the occurrence of disturbance.
    Type: Application
    Filed: June 7, 2019
    Publication date: September 26, 2019
    Inventors: Daisuke OKADA, Kazumasa YANAGISAWA, Fukuo OWADA, Shoji YOSHIDA, Yasuhiko KAWASHIMA, Shinji YOSHIDA, Yasuhiro TANIGUCHI, Kosuke OKUYAMA
  • Patent number: 10423115
    Abstract: An image forming apparatus including an image carrying member, an intermediate transfer belt having conductivity, a toner image on the image carrying member being primarily transferred to the intermediate transfer belt, a secondary transfer member in contact with an outer peripheral surface of the intermediate transfer belt, the secondary transfer member secondarily transferring the toner image on the intermediate transfer belt to a transfer material, a power supply applying a voltage to the secondary transfer member, the toner image being primarily transferred from the image carrying member to the intermediate transfer belt by having a voltage be applied to the secondary transfer member from the power supply, a contact member in contact with the intermediate transfer belt, and a constant current diode, an anode side thereof being connected to the power supply, and a cathode side thereof being connected to the contact member.
    Type: Grant
    Filed: October 8, 2018
    Date of Patent: September 24, 2019
    Assignee: CANON KABUSHIKI KAISHA
    Inventors: Shuichi Tetsuno, Shinji Katagiri, Tsuguhiro Yoshida, Koji An
  • Patent number: 10417227
    Abstract: A database management system (DBMS) generates a query execution plan including information representing one or more database (DB) operations necessary for executing a query and executes the query based on the query execution plan. In the execution of the query, the DBMS dynamically generates a task for executing a DB operation and executes the dynamically generated task. The DBMS executes a task in a plurality of threads executed by a processor core.
    Type: Grant
    Filed: April 27, 2012
    Date of Patent: September 17, 2019
    Assignees: Hitachi, Ltd., The University of Tokyo
    Inventors: Akira Shimizu, Seisuke Tokuda, Michiko Yoshida, Kazuhiko Mogi, Shinji Fujiwara, Nobuo Kawamura, Masaru Kitsuregawa, Kazuo Goda
  • Patent number: 10401779
    Abstract: A charge roller includes, in a surface thereof, recesses that have sizes that are equivalent to or larger than a volume average particle diameter of a toner accommodated in a developing unit and that are capable of collecting the toner retransferred to a photosensitive drum.
    Type: Grant
    Filed: August 3, 2018
    Date of Patent: September 3, 2019
    Assignee: Canon Kabushiki Kaisha
    Inventors: Shinji Katagiri, Tsuguhiro Yoshida, Shuichi Tetsuno, Takayuki Tanaka, Takahiro Ikeda, Satoru Motohashi, Takumi Furukawa
  • Patent number: 10391599
    Abstract: There is provided an electric power tool having a plurality of operation modes with different rotation speeds at least in a predetermined load range. The electric power tool is capable of switching between the operation modes when a predetermined condition is satisfied even during a motor is driven, and configured such that a rotation speed of the motor is changed smoothly or in a stepwise manner at the switching between the operation modes.
    Type: Grant
    Filed: July 10, 2014
    Date of Patent: August 27, 2019
    Assignee: KOKI HOLDINGS CO., LTD.
    Inventors: Kenichirou Yoshida, Akira Onose, Shinji Kuragano, Takuya Konnai
  • Patent number: 10388366
    Abstract: A semiconductor device with a memory unit of which the variations in the operation timing are reduced is provided. For example, the semiconductor device is provided with dummy bit lines which are arranged collaterally with a proper bit line, and column direction load circuits which are sequentially coupled to the dummy bit lines. Each column direction load circuit is provided with plural NMOS transistors fixed to an off state, predetermined ones of which have the source and the drain suitably coupled to any of the dummy bit lines. Load capacitance accompanying diffusion layer capacitance of the predetermined NMOS transistors is added to the dummy bit lines, and corresponding to the load capacitance, the delay time from a decode activation signal to a dummy bit line signal is set up. The dummy bit line signal is employed when setting the start-up timing of a sense amplifier.
    Type: Grant
    Filed: May 16, 2018
    Date of Patent: August 20, 2019
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Shinji Tanaka, Makoto Yabuuchi, Yuta Yoshida
  • Patent number: 10381446
    Abstract: A memory cell and a non-volatile semiconductor memory device are disclosed. Nitride sidewall layers are respectively disposed in a first sidewall spacer and a second sidewall spacer, to separate a memory gate electrode and a first select gate electrode from each other and the memory gate electrode and a second select gate electrode from each other. Hence, a breakdown voltage is improved around the memory gate electrode as compared with a conventional case in which the first sidewall spacer and the second sidewall spacer are simply made of insulating oxide films. The nitride sidewall layers are disposed farther from a memory well than a charge storage layer. Hence, charge is unlikely to be injected into the nitride sidewall layers at charge injection from the memory well into the charge storage layer, thereby preventing an operation failure due to charge storage in a region other than the charge storage layer.
    Type: Grant
    Filed: May 27, 2016
    Date of Patent: August 13, 2019
    Assignee: FLOADIA CORPORATION
    Inventors: Yasuhiro Taniguchi, Fukuo Owada, Yasuhiko Kawashima, Shinji Yoshida, Kosuke Okuyama
  • Patent number: 10373967
    Abstract: When a memory cell (MC) is downsized by reducing the distance between a drain region (12a) and a source region (12b) on the surface of a fin (S2) with a high impurity concentration inside the fin (S2), the shape of the fin (S2) can be set such that a potential difference between a memory gate electrode (MG) and the fin (S2) is reduced to suppress the occurrence of disturbance. Accordingly, the memory cell (MC) achieves downsizing and suppression of the occurrence of disturbance.
    Type: Grant
    Filed: December 7, 2016
    Date of Patent: August 6, 2019
    Assignee: FLOADIA CORPORATION
    Inventors: Daisuke Okada, Kazumasa Yanagisawa, Fukuo Owada, Shoji Yoshida, Yasuhiko Kawashima, Shinji Yoshida, Yasuhiro Taniguchi, Kosuke Okuyama
  • Patent number: 10340092
    Abstract: A solid electrolytic capacitor that includes a capacitor element including an anode portion having a metal layer, a dielectric layer, and a cathode portion having a solid electrolyte layer and a current collector layer; a leading conductor layer; an insulating resin body covering the capacitor element and the leading conductor layer, the insulating resin body having a first end surface and a second end surface opposite to each other; a first external electrode; and a second external electrode. The first external electrode has at least one plating layer on the first end surface, and is connected to the leading conductor layer at the first end surface. The second external electrode has at least one plating layer on the second end surface, and is connected to the metal layer at the second end surface.
    Type: Grant
    Filed: June 14, 2017
    Date of Patent: July 2, 2019
    Assignee: MURATA MANUFACTURING CO., LTD.
    Inventors: Hiroyuki Demizu, Kenichi Oshiumi, Tomohiro Suzuki, Shinya Yoshida, Koji Fujimoto, Tadahisa Sano, Tsuyoshi Yamamoto, Yoshinori Ueda, Shinji Otani
  • Publication number: 20190187522
    Abstract: The liquid crystal display device including: a first substrate; a liquid crystal layer; and a second substrate, the first substrate including a first electrode, and a second electrode, the liquid crystal molecules being aligned in a direction parallel to the first substrate with no voltage applied, the second electrode being provided with openings, the openings each having a long shape with two or more wide portions and one or more narrow portions, the two or more wide portions and the one or more narrow portions in each of the openings alternating with each other in a lengthwise direction of the opening, each of the wide portions of one of adjacent two openings being adjacent to one of the narrow portions of the other of the adjacent two openings, each of the narrow portions of the one opening being adjacent to one of the wide portions of the other opening.
    Type: Application
    Filed: December 18, 2018
    Publication date: June 20, 2019
    Inventors: TAKASHI KATAYAMA, SHINPEI HIGASHIDA, TAKAHIRO SASAKI, KAZUTAKA HANAOKA, KIMIAKI NAKAMURA, HIDEFUMI YOSHIDA, SHINJI SHIMADA
  • Patent number: 10295931
    Abstract: A developing device includes a casing to contain developer and define a developer circulation passage, a developing roller to bear the developer, and at least one developer conveyor to convey the developer. The developer conveyor is disposed in the developer circulation passage and lower than the developing roller. The developing device satisfies M1/L2>0.56 g/cm and M1/M2>0.50, where M1 represents an amount of developer borne on the developing roller, L1 represents a width in which the developing roller bears the developer in a longitudinal direction of the developing roller; and M2 represents an amount of developer stored in the casing and excluding the amount of developer borne.
    Type: Grant
    Filed: June 29, 2018
    Date of Patent: May 21, 2019
    Assignee: Ricoh Company, Ltd.
    Inventors: Shinji Tamaki, Ichiro Kadota, Keiichi Yoshida, Hiroshi Hosokawa