Patents by Inventor Shinya Morita

Shinya Morita has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8851886
    Abstract: Provided is a substrate processing apparatus. The substrate processing apparatus includes a reaction tube; a heating device configured to heat the reaction tube; and a manifold installed outward as compared with the heating device and made of a non-metallic material. A first thickness of the manifold defined in a direction perpendicular to a center axis of the reaction tube is greater than a second thickness of the manifold defined at a position adjacent to the reaction tube in a direction parallel to the center axis of the reaction tube. The manifold includes a protrusion part of which at least a portion protrudes inward more than an inner wall of the reaction tube, and a gas supply unit disposed at at least the protrusion part for supplying gas to an inside of the reaction tube.
    Type: Grant
    Filed: January 30, 2009
    Date of Patent: October 7, 2014
    Assignee: Hitachi Kokusai Electric, Inc.
    Inventors: Shinya Morita, Akihiro Sato, Akinori Tanaka, Shigeo Nakada, Takayuki Nakada, Shuhei Saido, Tomoyuki Matsuda
  • Publication number: 20140235102
    Abstract: A signal transmission cable comprises a cable including a dielectric layer and a metallic layer; and a connector having a chip with a terminal. The connector includes a substrate having an organic layer, and a portion of the organic layer extends from the substrate so as to form the dielectric layer of the cable. The metallic layer is located on the dielectric layer and is directly connected to the terminal.
    Type: Application
    Filed: January 23, 2014
    Publication date: August 21, 2014
    Applicant: SONY CORPORATION
    Inventors: Akira Akiba, Mitsuo Hashimoto, Shinya Morita, Shun Mitarai, Mikihiro Taketomo, Kazunao Oniki, Koichi Ikeda
  • Publication number: 20140167038
    Abstract: The inventive concept relates to a thin film transistor and a thin film transistor array panel and, in detail, relates to a thin film transistor including an oxide semiconductor. A thin film transistor according to an exemplary embodiment of the inventive concept includes: a gate electrode; a gate insulating layer positioned on or under the gate electrode; a first semiconductor and a second semiconductor that overlap the gate electrode with the gate insulating layer interposed therebetween, the first semiconductor and the second semiconductor contacting each other; a source electrode connected to the second semiconductor; and a drain electrode connected to the second semiconductor and facing the source electrode, wherein the second semiconductor includes gallium (Ga) that is not included in the first semiconductor, and a content of gallium (Ga) in the second semiconductor is greater than 0 at. % and less than or equal to about 33 at. %.
    Type: Application
    Filed: February 12, 2014
    Publication date: June 19, 2014
    Applicant: KABUSHIKI KAISHA KOBE SEIKO SHO (Kobe Steel, Ltd.)
    Inventors: Byung Du AHN, Ji Hun LIM, Gun Hee KIM, Kyoung Won LEE, Je Hun LEE, HIROSHI GOTO, AYA MIKI, SHINYA MORITA, TOSHIHIRO KUGIMIYA, Yeon Hong KIM, Yeon Gon MO, Kwang Suk KIM
  • Patent number: 8743307
    Abstract: A display device includes a first substrate, a gate line disposed on the first substrate and including a gate electrode, a gate insulating layer disposed on the gate line, a semiconductor layer disposed on the gate insulating layer, a data line disposed on the semiconductor layer and connected to a source electrode, a drain electrode disposed on the semiconductor layer and facing the source electrode and a passivation layer disposed on the data line, in which the semiconductor layer is formed of an oxide semiconductor including indium, tin, and zinc. The indium is present in an amount of about 5 atomic percent (at %) to about 50 at %, and a ratio of the zinc to the tin is about 1.38 to about 3.88.
    Type: Grant
    Filed: June 7, 2012
    Date of Patent: June 3, 2014
    Assignees: Samsung Display Co, Ltd., Kobe Steel, Ltd.
    Inventors: Jae Woo Park, Je Hun Lee, Byung Du Ahn, Sei-Yong Park, Jun Hyun Park, Gun Hee Kim, Ji Hun Lim, Kyoung Won Lee, Toshihiro Kugimiya, Aya Miki, Shinya Morita, Tomoya Kishi, Hiroaki Tao, Hiroshi Goto
  • Publication number: 20130341617
    Abstract: The oxide of the present invention for thin-film transistors is an In—Zn—Sn-based oxide containing In, Zn, and Sn, wherein when the respective contents (atomic %) of metal elements contained in the In—Zn—Sn-based oxide are expressed by [Zn], [Sn], and [In], the In—Zn—Sn-based oxide fulfills the following expressions (2) and (4) when [In]/([In]+[Sn])?0.5; or the following expressions (1), (3), and (4) when [In]/([In]+[Sn])?0.5. [In]/([In]+[Zn]+[Sn])?0.3 - - - (1), [In]/([In]+[Zn]+[Sn])?1.4×{[Zn]/([Zn]+[Sn])}?0.5 - - - (2), [Zn]/([In]+[Zn]+[Sn])?0.83 - - - (3), and 0.1?[In]/([In]+[Zn]+[Sn]) - - - (4). According to the present invention, oxide thin films for thin-film transistors can be obtained, which provide TFTs with excellent switching characteristics, and which have high sputtering rate in the sputtering and properly controlled etching rate in the wet etching.
    Type: Application
    Filed: March 8, 2012
    Publication date: December 26, 2013
    Applicants: Samsung Display Co., Ltd., KABUSHIKI KAISHA KOBE SEIKO SHO (Kobe Steel, Ltd.)
    Inventors: Hiroaki Tao, Aya Miki, Shinya Morita, Satoshi Yasuno, Toshihiro Kugimiya, Jae Woo Park, Je Hun Lee, Byung Du Ahn, Gun Hee Kim
  • Patent number: 8598580
    Abstract: Disclosed is a wiring structure that attains excellent low-contact resistance even if eliminating a barrier metal layer that normally is disposed between a Cu alloy wiring film and a semiconductor layer, and wiring structure with excellent adhesion. The wiring structure is provided with a semiconductor layer, and a Cu alloy layer, on a substrate in this order from the substrate side. A laminated structure is included between the semiconductor layer, and the Cu alloy layer. The laminated structure is composed of a (N, C, F, O) layer which contains at least one element selected from among a group composed of nitrogen, carbon, fluorine, and oxygen, and a Cu—Si diffusion layer which includes Cu and Si, in this order from the substrate side. At least one element selected from among the group composed of nitrogen, carbon, fluorine, and oxygen that composes the (N, C, F, O) layer is bonded to Si in the semiconductor layer.
    Type: Grant
    Filed: March 30, 2011
    Date of Patent: December 3, 2013
    Assignee: Kobe Steel, Ltd.
    Inventors: Yasuaki Terao, Shinya Morita, Aya Miki, Katsufumi Tomihisa, Hiroshi Goto
  • Patent number: 8591657
    Abstract: Metal corrosion and substrate contamination can be suppressed, and process quality and yield can be improved. A substrate processing apparatus comprises: a process chamber; a substrate holder; a cover part closing and opening the process chamber; a substrate holder stage; a rotary mechanism rotating the substrate holder stage; a rotation shaft inserted through the cover part and connected to the substrate holder stage and the rotary mechanism so that a first gas ejection port is formed therebetween; a first gas stagnant part surrounded by the rotary mechanism, the cover part, and the rotation shaft; a second gas ejection port formed at the substrate holder stage; a second gas stagnant part formed at the rotation shaft and communicating with the process chamber via the second gas ejection port; and a flow port formed at the rotation shaft for connecting the first and second gas stagnant parts.
    Type: Grant
    Filed: August 27, 2009
    Date of Patent: November 26, 2013
    Assignee: Hitachi Kokusai Electric Inc.
    Inventors: Takayuki Nakada, Tomoyuki Matsuda, Shinya Morita
  • Publication number: 20130270109
    Abstract: The oxides for semiconductor layers of thin-film transistors according to the present invention include: In; Zn; and at least one element (X group element) selected from the group consisting of Al, Si, Ta, Ti, La, Mg and Nb. The present invention makes it possible to provide oxides for semiconductor layers of thin-film transistors, in which connection thin-film transistors with In—Zn—O oxide semiconductors not containing Ga have favorable switching characteristics and high stress resistance, and in particular, show a small variation of the threshold voltage before and after positive bias stress tests, thereby having high stability.
    Type: Application
    Filed: December 28, 2011
    Publication date: October 17, 2013
    Applicant: Kabushiki Kaisha Kobe Seiko Sho (Kobe Steel, Ltd.)
    Inventors: Shinya Morita, Aya Miki, Satoshi Yasuno, Toshihiro Kugimiya, Tomoya Kishi
  • Publication number: 20130248858
    Abstract: The interconnect structure of the present invention includes at least a gate insulator layer and an oxide semiconductor layer on a substrate, wherein the oxide semiconductor layer is a layered product having a first oxide semiconductor layer containing at least one element (Z group element) selected from the group consisting of In, Ga, Zn and Sn; and a second oxide semiconductor layer containing at least one element (X group element) selected from the group consisting of In, Ga, Zn and Sn and at least one element (Y group element) selected from the group consisting of Al, Si, Ti, Hf, Ta, Ge, W and Ni, and wherein the second oxide semiconductor layer is interposed between the first oxide semiconductor layer and the gate insulator layer.
    Type: Application
    Filed: December 1, 2011
    Publication date: September 26, 2013
    Applicant: KABUSHIKI KAISHA KOBE SEIKO SHO (Kobe Steel, Ltd.)
    Inventors: Shinya Morita, Aya Miki, Satoshi Yasuno, Toshihiro Kugimiya
  • Publication number: 20130248855
    Abstract: This oxide for a semiconductor layer of a thin-film transistor contains Zn, Sn and In, and the content (at %) of the metal elements contained in the oxide satisfies formulas (1) to (3) when denoted as [Zn], [Sn] and [In], respectively. [In]/([In]+[Zn]+[Sn])??0.53×[Zn]/([Zn]+[Sn])+0.36 (1) [In]/([In]+[Zn]+[Sn])?2.28×[Zn]/([Zn]+[Sn])?2.01 (2) [In]/([In]+[Zn]+[Sn])?1.1×[Zn]/([Zn]+[Sn])?0.32 (3) The present invention enables a thin-film transistor oxide that achieves high mobility and has excellent stress resistance (negligible threshold voltage shift before and after applying stress) to be provided.
    Type: Application
    Filed: November 28, 2011
    Publication date: September 26, 2013
    Applicants: Samsung Display Co., Ltd., Kabushiki Kaisha Kobe Seiko Sho(Kobe Steel, Ltd.)
    Inventors: Aya Miki, Shinya Morita, Toshihiro Kugimiya, Satoshi Yasuno, Jae Woo Park, Je Hun Lee, Byung Du Ahn, Gun Hee Kim
  • Publication number: 20130240802
    Abstract: This oxide for a semiconductor layer of a thin-film transistor contains Zn, Sn and In, and at least one type of element (X group element) selected from an X group comprising Si, Hf, Ga, Al, Ni, Ge, Ta, W and Nb. The present invention enables a thin-film transistor oxide that achieves high mobility and has excellent stress resistance (negligible threshold voltage shift before and after applying stress) to be provided.
    Type: Application
    Filed: November 28, 2011
    Publication date: September 19, 2013
    Applicants: Samsung Display Co., Ltd., KABUSHIKI KAISHA KOBE SEIKO SHO (Kobe Steel ,Ltd.)
    Inventors: Aya Miki, Shinya Morita, Toshihiro Kugimiya, Satoshi Yasuno, Jae Woo Park, Je Hun Lee, Byung Du Ahn
  • Patent number: 8535997
    Abstract: Provided is a direct contact technology by which a barrier metal layer between a Cu alloy wiring composed of pure Cu or a Cu alloy and a semiconductor layer can be eliminated, and the Cu alloy wiring can be directly and surely connected to the semiconductor layer within a wide process margin. The wiring structure is provided with the semiconductor layer and the Cu alloy film composed of pure Cu or the Cu alloy on a substrate in this order from the substrate side. A laminated structure is included between the semiconductor layer and the Cu alloy film. The laminated structure is composed of an (N, C, F) layer, which contains at least one element selected from among a group composed of nitrogen, carbon and fluorine, and a Cu—Si diffusion layer, which contains Cu and Si, in this order from the substrate side. Furthermore, at least the one element selected from among the group composed of nitrogen, carbon and fluorine is bonded to Si contained in the semiconductor layer.
    Type: Grant
    Filed: July 3, 2009
    Date of Patent: September 17, 2013
    Assignee: Kobe Steel, Ltd.
    Inventors: Nobuyuki Kawakami, Shinya Fukuma, Aya Miki, Mototaka Ochi, Shinya Morita, Yoshihiro Yokota, Hiroshi Goto
  • Patent number: 8529701
    Abstract: A substrate processing apparatus includes a reaction tube, the reaction tub including an inner tube made of quartz and an outer tube made of quartz; a manifold made of quartz disposed under the outer tube, a top surface of the manifold being in air-tight contact with a bottom surface of the outer tube via a sealing member; a seal cap cover made of quartz disposed under the manifold, a top surface of the seal cap cover being in air-tight contact with a bottom surface of the manifold via a sealing member; a seal cap covered by the seal cap cover, a top surface of the seal cap being in air-tight contact with a bottom surface of the seal cap cover via a sealing member; and at least one protrusion disposed at the bottom surface of one of the outer tube, the manifold, the seal cap cover, and combinations thereof.
    Type: Grant
    Filed: August 6, 2009
    Date of Patent: September 10, 2013
    Assignee: Hitachi Kokusai Electric Inc.
    Inventors: Shinya Morita, Takayuki Nakada, Tomoyuki Matsuda, Keisuke Sakashita
  • Publication number: 20130119324
    Abstract: There is provided an oxide for semiconductor layers of thin-film transistors, which oxide can provide thin-film transistors with excellent switching characteristics and by which oxide favorable characteristics can stably be obtained even after the formation of passivation layers. The oxide to be used for semiconductor layers of thin-film transistors according to the present invention includes Zn, Sn, and Si.
    Type: Application
    Filed: July 28, 2011
    Publication date: May 16, 2013
    Applicants: Samsung Display Co., Ltd., KABUSHIKI KAISHA KOBE SEIKO SHO (Kobe Steel, Ltd.)
    Inventors: Shinya Morita, Aya Miki, Yumi Iwanari, Toshihiro Kugimiya, Satoshi Yasuno, Jae Woo Park, Je Hun Lee, Byung Du Ahn
  • Publication number: 20130075720
    Abstract: An oxide semiconductor includes a first material including at least one selected from the group consisting of zinc (Zn) and tin (Sn), and a second material, where a value acquired by subtracting an electronegativity difference value between the second material and oxygen (O) from the electronegativity difference value between the first material and oxygen (O) is less than about 1.3.
    Type: Application
    Filed: July 20, 2012
    Publication date: March 28, 2013
    Applicants: Kobe Steel, Ltd., SAMSUNG DISPLAY CO., LTD.
    Inventors: Byung Du AHN, Je Hun LEE, Sei-Yong PARK, Jun Hyun PARK, Gun Hee KIM, Ji Hun LIM, Jae Woo PARK, Jin Seong PARK, Toshihiro KUGIMIYA, Aya MIKI, Shinya MORITA, Tomoya KISHI, Hiroaki TAO
  • Publication number: 20130032798
    Abstract: Disclosed is an oxide for a semiconductor layer of a thin-film transistor, said oxide being excellent in the switching characteristics of a thin-film transistor, specifically enabling favorable characteristics to be stably obtained even in a region of which the ZnO concentration is high and even after forming a passivation layer and after applying stress. The oxide is used in a semiconductor layer of a thin-film transistor, and the aforementioned oxide contains Zn and Sn, and further contains at least one element selected from group X consisting of Al, Hf, Ta, Ti, Nb, Mg, Ga, and the rare-earth elements.
    Type: Application
    Filed: April 18, 2011
    Publication date: February 7, 2013
    Applicants: SAMSUNG DISPLAY CO., LTD., KABUSHIKI KAISHA KOBE SEIKO SHO (KOBE STEEL, LTD.)
    Inventors: Aya Miki, Yumi Iwanari, Toshihiro Kugimiya, Shinya Morita, Yasuaki Terao, Satoshi Yasuno, Jae Woo Park, Je Hun Lee, Byung Du Ahn
  • Publication number: 20130026470
    Abstract: Disclosed is a wiring structure that attains excellent low-contact resistance even if eliminating a barrier metal layer that normally is disposed between a Cu alloy wiring film and a semiconductor layer, and wiring structure with excellent adhesion. The wiring structure is provided with a semiconductor layer, and a Cu alloy layer, on a substrate in this order from the substrate side. A laminated structure is included between the semiconductor layer, and the Cu alloy layer. The laminated structure is composed of a (N, C, F, O) layer which contains at least one element selected from among a group composed of nitrogen, carbon, fluorine, and oxygen, and a Cu—Si diffusion layer which includes Cu and Si, in this order from the substrate side. At least one element selected from among the group composed of nitrogen, carbon, fluorine, and oxygen that composes the (N, C, F, O) layer is bonded to Si in the semiconductor layer.
    Type: Application
    Filed: March 30, 2011
    Publication date: January 31, 2013
    Applicant: Kabushiki Kaisha Kobe Seiko Sho (Kobe Steel, Ltd.)
    Inventors: Yasuaki Terao, Shinya Morita, Aya Miki, Katsufumi Tomihisa, Hiroshi Goto
  • Publication number: 20130009111
    Abstract: Disclosed is an oxide for a semiconductor layer of a thin film transistor, which, when used in a thin film transistor that includes an oxide semiconductor in the semiconductor layer, imparts good switching characteristics and stress resistance to the transistor. Specifically disclosed is an oxide for a semiconductor layer of a thin film transistor, which is used for a semiconductor layer of a thin film transistor and contains at least one element selected from the group consisting of In, Ga and Zn and at least one element selected from the group X consisting of Al, Si, Ni, Ge, Sn, Hf, Ta and W.
    Type: Application
    Filed: April 7, 2011
    Publication date: January 10, 2013
    Applicant: Kabushiki Kaisha Kobe Seiko Sho (Kobe Steel, Ltd.)
    Inventors: Shinya Morita, Toshihiro Kugiyama, Takeaki Maeda, Satoshi Yasuno, Yasuaki Terao, Aya Miki
  • Patent number: 8299614
    Abstract: An interconnection structure, containing a substrate and, in the following order from a side of the substrate: (I) a semiconductor layer; (II) a multilayer structure including (II-a) a first layer containing at least one type of an element selected from the group consisting of nitrogen, carbon and fluorine and (II-b) an Al—Si diffusion layer containing Al and Si; and (III) an Al film of pure Al or an Al alloy, wherein the at least one of element selected from the group consisting of nitrogen, carbon, and fluorine in the first layer is bonded with Si contained in the semiconductor layer.
    Type: Grant
    Filed: April 17, 2009
    Date of Patent: October 30, 2012
    Assignee: Kobe Steel, Ltd.
    Inventors: Nobuyuki Kawakami, Mototaka Ochi, Aya Miki, Shinya Morita, Yoshihiro Yokota, Shinya Fukuma, Hiroshi Goto
  • Patent number: D711843
    Type: Grant
    Filed: December 26, 2013
    Date of Patent: August 26, 2014
    Assignee: Hitachi Kokusai Electric Inc.
    Inventors: Keishin Yamazaki, Masahiro Miyake, Kosuke Takagi, Yasuaki Komae, Shinya Morita, Naonori Akae, Masato Terasaki