Patents by Inventor Shinya Morita

Shinya Morita has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20150255627
    Abstract: A thin film transistor containing at least, a gate electrode, a gate insulating film, an oxide semiconductor layer, source-drain electrode and a passivation film, in this order on a substrate. The oxide semiconductor layer is a laminate containing a first oxide semiconductor layer (IGZTO) and a second oxide semiconductor layer (IZTO). The second oxide semiconductor layer is formed on the gate insulating film, and the first oxide semiconductor layer is formed between the second oxide semiconductor layer and the passivation film. The contents of respective metal elements relative to the total amount of all the metal elements other than oxygen in the first oxide semiconductor layer are as follows; Ga: 8% or more and 30% or less; In: 25% or less, excluding 0%; Zn: 35% or more to 65% or less; and Sn: 5% or more to 30% or less.
    Type: Application
    Filed: May 26, 2015
    Publication date: September 10, 2015
    Inventors: Hiroshi GOTO, Aya MIKI, Tomoya KISHI, Kenta HIROSE, Shinya MORITA, Toshihiro KUGIMIYA
  • Patent number: 9111972
    Abstract: The sizes required for maintenance are reduced and an occupying floor area is reduced. The substrate processing apparatus contains a load lock chamber 41 and a transfer chamber 24 respectively provided in order from the rear side within a case 11; and a processing chamber 53 provided above the load lock chamber 41 for processing wafers 1. An opening section 27A, and an opening and closing means 28A for opening and closing the opening section 27A are respectively provided in a location at the rear side of the transfer chamber 24 where the load lock chamber 41 is not arranged.
    Type: Grant
    Filed: June 27, 2005
    Date of Patent: August 18, 2015
    Assignee: HITACHI KOKUSAI ELECTRIC INC.
    Inventors: Mitsunori Takeshita, Tomoyuki Matsuda, Mitsuhiro Hirano, Akihiro Sato, Shinya Morita, Toshimitsu Miyata, Koji Shibata
  • Publication number: 20150228674
    Abstract: Provided is a thin film transistor which is provided with an oxide semiconductor thin film layer and has a threshold voltage that does not change much due to light, a bias stress or the like, thereby exhibiting excellent stress stability. A thin film transistor of the present invention is provided with a gate electrode, an oxide semiconductor layer composed of a single layer which is used as a channel layer, an etch stopper layer to protect a surface of the oxide semiconductor layer, a source-drain electrode, and a gate insulator layer arranged between the gate electrode and the channel layer. The metal elements constituting the oxide semiconductor layer comprise In, Zn and Sn. The hydrogen concentration in the gate insulator layer in direct contact with the oxide semiconductor layer is controlled to 4 atomic % or lower.
    Type: Application
    Filed: August 30, 2013
    Publication date: August 13, 2015
    Applicants: KABUSHIKI KAISHA KOBE SEIKO SHO (KOBE STEEL, LTD.), Samsung Display Co., Ltd.
    Inventors: Aya Miki, Shinya Morita, Hiroshi Goto, Hiroaki Tao, Toshihiro Kugimiya, Byung Du Ahn, Gun Hee Kim, Jin Hyun Park, Yeon Hong Kim
  • Publication number: 20150206978
    Abstract: Provided is a thin film transistor comprising an oxide semiconductor thin film layer and has a threshold voltage that does not change much due to light, a bias stress or the like, thereby exhibiting excellent stress stability. A thin film transistor of the present invention is provided with: a gate electrode; two or more oxide semiconductor layers that are used as a channel layer; an etch stopper layer for protecting the surfaces of the oxide semiconductor layers; a source-drain electrode; and a gate insulator film interposed between the gate electrode and the channel layer. The metal elements constituting an oxide semiconductor layer that is in direct contact with the gate insulator film are In, Zn and Sn. The hydrogen concentration in the gate insulator film, which is in direct contact with the oxide semiconductor layer, is controlled to 4 atomic % or less.
    Type: Application
    Filed: August 30, 2013
    Publication date: July 23, 2015
    Applicant: Kabushiki Kaisha Kobe Seiko Sho (Kobe Steel, Ltd.)
    Inventors: Aya Miki, Shinya Morita, Hiroshi Goto, Hiroaki Tao, Toshihiro Kugimiya
  • Patent number: 9070597
    Abstract: A thin film transistor includes a gate electrode, a channel overlapped with the gate electrode, a source electrode contacting the channel, and a drain electrode spaced apart from the source electrode and contacting the channel. The channel includes indium-zinc-tin oxide sourced from a source including a single phase indium-zinc-tin oxide.
    Type: Grant
    Filed: April 27, 2014
    Date of Patent: June 30, 2015
    Assignees: SAMSUNG DISPLAY CO., LTD., KOBE STEEL, LTD.
    Inventors: Byung-Du Ahn, Gun-Hee Kim, Jun-Hyung Lim, Toshihiro Kugimiya, Hiroshi Goto, Aya Miki, Shinya Morita
  • Publication number: 20150179371
    Abstract: There is provided an electronic device including a first member formed to include at least a part of a substrate material, a second member formed to include at least a part of the substrate material and configured to be relatively movable with respect to the first member, and a fuse configured to include at least a part of the substrate material and configured to electrically connect the first member to the second member via the substrate material.
    Type: Application
    Filed: November 25, 2014
    Publication date: June 25, 2015
    Inventors: Mitsuo Hashimoto, Akira Akiba, Hideo Niikura, Satoshi Mitani, Shinya Morita, Kunihiko Saruta
  • Publication number: 20150171221
    Abstract: Provided is a thin film transistor comprising an oxide semiconductor thin film layer and has a threshold voltage that does not change much due to light, a bias stress or the like, thereby exhibiting excellent stress stability. A thin film transistor of the present invention is provided with: a gate electrode; an oxide semiconductor layer that is used as a channel layer; and a gate insulator film that is arranged between the gate electrode and the channel layer. The oxide semiconductor layer is configured of at least one metal element that is selected from the group consisting of In, Ga, Zn and Sn (excluding the cases where the oxide semiconductor layer is constituted of metal elements Sn, and at least one of In and Zn). The hydrogen concentration in the gate insulator film, which is in direct contact with the oxide semiconductor layer, is controlled to 4 atomic % or less.
    Type: Application
    Filed: August 30, 2013
    Publication date: June 18, 2015
    Applicant: Kabushiki Kaisha Kobe Seiko Sho (Kobe Steel, Ltd.)
    Inventors: Aya Miki, Shinya Morita, Hiroshi Goto, Toshihiro Kugimiya, Hiroaki Tao, Kenta Hirose
  • Patent number: 9059492
    Abstract: A waveguide includes: a waveguide portion including a first surface and a second surface that are opposed to each other; a first transmission line provided on the first surface of the waveguide portion; a second transmission line provided on the second surface of the waveguide portion; and a first conversion structure inputting a signal from the first transmission line to the waveguide portion and converting the signal.
    Type: Grant
    Filed: November 29, 2012
    Date of Patent: June 16, 2015
    Assignee: SONY CORPORATION
    Inventors: Shinya Morita, Koichi Ikeda, Akira Akiba, Mitsuo Hashimoto
  • Patent number: 9041489
    Abstract: A signal transmission cable includes a multi-layer parallel transmission path, a single-layer parallel transmission path, and a single-layer/multi-layer conversion section. The multi-layer parallel transmission path includes two or more dielectric waveguides stacked in upper and lower directions. Each dielectric waveguide includes a dielectric layer formed of a dielectric substance, two conductive layers formed to sandwich the dielectric layer, and two quasi-conductive walls. The two quasi-conductive walls include a plurality of via-holes electrically connected to the two conductive layers. The dielectric waveguides are arranged sharing the conductive layers in contact in the upper and lower directions. The single-layer parallel transmission path includes the two or more dielectric waveguides arranged in left- and right-hand directions on the same dielectric layer and conductive layer.
    Type: Grant
    Filed: April 10, 2014
    Date of Patent: May 26, 2015
    Assignee: SONY CORPORATION
    Inventors: Shinya Morita, Akira Akiba
  • Publication number: 20150123116
    Abstract: Provided is a thin film transistor having an oxide semiconductor layer that has high mobility, excellent stress resistance, and good wet etching property. The thin film transistor comprises at least, a gate electrode, a gate insulating film, an oxide semiconductor layer, source-drain electrode and a passivation film, in this order on a substrate. The oxide semiconductor layer is a laminate comprising a first oxide semiconductor layer (IGZTO) and a second oxide semiconductor layer (IZTO). The second oxide semiconductor layer is formed on the gate insulating film, and the first oxide semiconductor layer is formed between the second oxide semiconductor layer and the passivation film. The contents of respective metal elements relative to the total amount of all the metal elements other than oxygen in the first oxide semiconductor layer are as follows; Ga: 5% or more; In: 25% or less (excluding 0%); Zn: 35 to 65%; and Sn: 8 to 30%.
    Type: Application
    Filed: June 6, 2013
    Publication date: May 7, 2015
    Applicant: KABUSHIKI KAISHA KOBE SEIKO SHO (Kobe Steel, Ltd.)
    Inventors: Hiroshi Goto, Aya Miki, Tomoya Kishi, Kenta Hirose, Shinya Morita, Toshihiro Kugimiya
  • Publication number: 20150091000
    Abstract: Provided is an oxide-semiconductor-based thin film transistor having satisfactory switching characteristics and stress resistance. Change in threshold voltage through stress application is suppressed in the thin film transistor. The thin film transistor of excellent stability comprises a substrate and, formed thereon, at least a gate electrode, a gate insulating film, oxide semiconductor layers, a source-drain electrode, and a passivation film for protecting the gate insulating film, and oxide semiconductor layers, wherein the oxide semiconductor layers are laminated layers comprising a second oxide semiconductor layer consisting of In, Zn, Sn, and O and a first oxide semiconductor layer consisting of In, Ga, Zn, and O. The second oxide semiconductor layer is formed on the gate insulating film. The first oxide semiconductor layer is interposed between the second oxide semiconductor layer and the passivation film.
    Type: Application
    Filed: May 8, 2013
    Publication date: April 2, 2015
    Applicant: Kabushiki Kaisha Kobe Seiko Sho (Kobe Steel, Ltd.)
    Inventors: Shinya Morita, Aya Miki, Hiroaki Tao, Toshihiro Kugimiya
  • Publication number: 20150076489
    Abstract: Provided is an oxide semiconductor configured to be used in a thin film transistor having high field-effect mobility; a small shift in threshold voltages against light and bias stress; excellent stress resistance. The oxide semiconductor has also excellent resistance to a wet-etchant for patterning of a source-drain electrode. The oxide semiconductor comprises In, Zn, Ga, Sn and O, and satisfies the requirements represented by expressions (1) to (4) shown below, wherein [In], [Zn], [Ga], and [Sn] represent content (in atomic %) of each of the elements relative to the total content of all the metal elements other than oxygen in the oxide. (1.67×[Zn]+1.67×[Ga])?100 ??(1) {([Zn]/0.95)+([Sn]/0.40)+([In]/0.
    Type: Application
    Filed: May 28, 2013
    Publication date: March 19, 2015
    Applicant: Kabushiki Kaisha Kobe Seiko Sho (Kobe Steel, Ltd.)
    Inventors: Shinya Morita, Kenta Hirose, Aya Miki, Toshihiro Kugimiya
  • Publication number: 20150076488
    Abstract: Provided is a thin film transistor having an oxide semiconductor layer that has high mobility, excellent stress resistance, and good wet etching property. The thin film transistor comprises at least, a gate electrode, a gate insulating film, an oxide semiconductor layer, source-drain electrode and a passivation film, in this order on a substrate. The oxide semiconductor layer is a laminate comprising a first oxide semiconductor layer (IGZTO) and a second oxide semiconductor layer (IGZO). The second oxide semiconductor layer is formed on the gate insulating film, and the first oxide semiconductor layer is formed between the second oxide semiconductor layer and the passivation film. The contents of respective metal elements relative to the total amount of all the metal elements other than oxygen in the first oxide semiconductor layer are as follows; In: 25% or less (excluding 0%); Ga: 5% or more; Zn: 30.0 to 60.0%; and Sn: 8 to 30%.
    Type: Application
    Filed: June 6, 2013
    Publication date: March 19, 2015
    Applicant: KABUSHIKI KAISHA KOBE SEIKO SHO (Kobe Steel,Ltd.)
    Inventors: Tomoya Kishi, Kenta Hirose, Shinya Morita, Toshihiro Kugimiya
  • Publication number: 20140367523
    Abstract: Provided are a space debris removing device and a method which enable easy installation of a deceleration device to space debris undergoing a tumbling motion. The space debris removing device includes: a propulsion device (3) for performing approach and attitude control on target debris (1); a capture device (4) having a harpoon (41) which can be ejected toward the target debris (1); an observation device (5) for calculating a capture position (E) and a capture attitude at which the harpoon (41) can be driven into a tank (11) (hollow portion) of the target debris (1) by observing a motion of the target debris (1); a deceleration device (6) directly or indirectly connected to the harpoon (41), for decelerating the target debris (1); and a body part (21) on which the propulsion device (3), the capture device (4), the observation device (5), and the deceleration device (6) are mounted.
    Type: Application
    Filed: November 1, 2012
    Publication date: December 18, 2014
    Applicants: IHI AEROSPACE CO., LTD., IHI CORPORATION
    Inventors: Yukihito Kitazawa, Aritsune Kawabe, Kozue Hashimoto, Mitsuharu Sonehara, Masaru Uji, Shinya Morita, Katsuaki Nomura, Ayumi Nakanishi
  • Patent number: 8907334
    Abstract: Disclosed is an oxide for a semiconductor layer of a thin-film transistor, said oxide being excellent in the switching characteristics of a thin-film transistor, specifically enabling favorable characteristics to be stably obtained even in a region of which the ZnO concentration is high and even after forming a passivation layer and after applying stress. The oxide is used in a semiconductor layer of a thin-film transistor, and the aforementioned oxide contains Zn and Sn, and further contains at least one element selected from group X consisting of Al, Hf, Ta, Ti, Nb, Mg, Ga, and the rare-earth elements.
    Type: Grant
    Filed: April 18, 2011
    Date of Patent: December 9, 2014
    Assignees: Kobe Steel, Ltd., Samsung Display Co., Ltd.
    Inventors: Aya Miki, Yumi Iwanari, Toshihiro Kugimiya, Shinya Morita, Yasuaki Terao, Satoshi Yasuno, Jae Woo Park, Je Hun Lee, Byung Du Ahn
  • Publication number: 20140346498
    Abstract: A thin film transistor includes a gate electrode, a channel overlapped with the gate electrode, a source electrode contacting the channel, and a drain electrode spaced apart from the source electrode and contacting the channel. The channel includes indium-zinc-tin oxide sourced from a source including a single phase indium-zinc-tin oxide.
    Type: Application
    Filed: April 27, 2014
    Publication date: November 27, 2014
    Applicants: Samsung Display Co., Ltd., Kobe Steel, LTD.
    Inventors: Byung-Du AHN, Gun-Hee KIM, Jun-Hyung LIM, Toshihiro KUGIMIYA, Hiroshi GOTO, Aya MIKI, Shinya MORITA
  • Publication number: 20140312987
    Abstract: A signal transmission cable includes a multi-layer parallel transmission path, a single-layer parallel transmission path, and a single-layer/multi-layer conversion section. The multi-layer parallel transmission path includes two or more dielectric waveguides stacked in upper and lower directions. Each dielectric waveguide includes a dielectric layer formed of a dielectric substance, two conductive layers formed to sandwich the dielectric layer, and two quasi-conductive walls. The two quasi-conductive walls include a plurality of via-holes electrically connected to the two conductive layers. The dielectric waveguides are arranged sharing the conductive layers in contact in the upper and lower directions. The single-layer parallel transmission path includes the two or more dielectric waveguides arranged in left- and right-hand directions on the same dielectric layer and conductive layer.
    Type: Application
    Filed: April 10, 2014
    Publication date: October 23, 2014
    Applicant: SONY CORPORATION
    Inventors: Shinya Morita, Akira Akiba
  • Patent number: D719114
    Type: Grant
    Filed: December 26, 2013
    Date of Patent: December 9, 2014
    Assignee: Hitachi Kokusai Electric Inc.
    Inventors: Keishin Yamazaki, Masahiro Miyake, Kosuke Takagi, Yasuaki Komae, Shinya Morita, Naonori Akae, Masato Terasaki
  • Patent number: D720707
    Type: Grant
    Filed: December 26, 2013
    Date of Patent: January 6, 2015
    Assignee: Hitachi Kokusai Electric Inc.
    Inventors: Keishin Yamazaki, Masahiro Miyake, Kosuke Takagi, Yasuaki Komae, Shinya Morita, Naonori Akae, Masato Terasaki
  • Patent number: D725055
    Type: Grant
    Filed: December 26, 2013
    Date of Patent: March 24, 2015
    Assignee: Hitachi Kokusai Electric Inc.
    Inventors: Keishin Yamazaki, Masahiro Miyake, Kosuke Takagi, Yasuaki Komae, Shinya Morita, Naonori Akae, Masato Terasaki