Patents by Inventor Shlomo Raikin

Shlomo Raikin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9734079
    Abstract: Hybrid multi-level memory architecture technologies are described. A System on Chip (SOC) includes multiple functional units and a multi-level memory controller (MLMC) coupled to the functional units. The MLMC is coupled to a hybrid multi-level memory architecture including a first-level dynamic random access memory (DRAM) (near memory) that is located on-package of the SOC and a second-level DRAM (far memory) that is located off-package of the SOC. The MLMC presents the first-level DRAM and the second-level DRAM as a contiguous addressable memory space and provides the first-level DRAM to software as additional memory capacity to a memory capacity of the second-level DRAM. The first-level DRAM does not store a copy of contents of the second-level DRAM.
    Type: Grant
    Filed: June 28, 2013
    Date of Patent: August 15, 2017
    Assignee: Intel Corporation
    Inventors: Dannie G. Feekes, Shlomo Raikin, Blaise Fanning, Joydeep Ray, Julius Mandelblat, Ariel Berkovits, Eran Shifer, Zvika Greenfield, Evgeny Bolotin
  • Patent number: 9727503
    Abstract: A data storage system includes a storage server, including non-volatile memory (NVM) and a server network interface controller (NIC), which couples the storage server to a network. A host computer includes a host central processing unit (CPU), a host memory and a host NIC, which couples the host computer to the network. The host computer runs a driver program that is configured to receive, from processes running on the host computer, commands in accordance with a protocol defined for accessing local storage devices connected to a peripheral component interface bus of the host computer, and upon receiving a storage access command in accordance with the protocol, to initiate a remote direct memory access (RDMA) operation to be performed by the host and server NICs so as to execute on the storage server, via the network, a storage transaction specified by the command.
    Type: Grant
    Filed: March 17, 2014
    Date of Patent: August 8, 2017
    Assignee: MELLANOX TECHNOLOGIES, LTD.
    Inventors: Michael Kagan, Noam Bloch, Shlomo Raikin, Yaron Haviv, Idan Burstein
  • Patent number: 9720843
    Abstract: A processor of an aspect includes operation mode check logic to determine whether to allow an attempted access to an operation mode and access type protected memory based on an operation mode that is to indicate whether the attempted access is by an on-die processor logic. Access type check logic is to determine whether to allow the attempted access to the operation mode and access type protected memory based on an access type of the attempted access to the operation mode and access type protected memory. Protection logic is coupled with the operation mode check logic and is coupled with the access type check logic. The protection logic is to deny the attempted access to the operation mode and access type protected memory if at least one of the operation mode check logic and the access type check logic determines not to allow the attempted access.
    Type: Grant
    Filed: December 28, 2012
    Date of Patent: August 1, 2017
    Assignee: Intel Corporation
    Inventors: Gur Hildesheim, Shlomo Raikin, Ittai Anati, Gideon Gerzon, Hisham Shafi, Alex Berenzon, Geoffrey S. Strongin, Iris Sorani
  • Publication number: 20170192934
    Abstract: Methods and apparatus are disclosed for using an index array and finite state machine for scatter/gather operations. Embodiment of apparatus may comprise: decode logic to decode a scatter/gather instruction and generate a set of micro-operations, and an index array to hold a set of indices and a corresponding set of mask elements. A finite state machine facilitates the gather operation. Address generation logic generates an address from an index of the set of indices for at least each of the corresponding mask elements having a first value. An address is accessed to load a corresponding data element if the mask element had the first value. The data element is written at an in-register position in a destination vector register according to a respective in-register position the index. Values of corresponding mask elements are changed from the first value to a second value responsive to completion of their respective loads.
    Type: Application
    Filed: February 6, 2015
    Publication date: July 6, 2017
    Inventors: Zeev Sperber, Robert Valentine, Guy Patkin, Stanislav Shwartsman, Shlomo Raikin, Igor Yanover, Gal Ofir
  • Patent number: 9699110
    Abstract: Lock access is managed in a data network having an initiator node and a remote target by issuing a lock command from a first process to the remote target via an initiator network interface controller to establish a lock on a memory location, and prior to receiving a reply to the lock command communicating a data access request to the memory location from the initiator network interface controller. Prior to receiving a reply to the data access request, an unlock command issues from the initiator network interface controller. The target network interface controller determines the lock content, and when permitted by the lock accesses the memory location. After accessing the memory location the target network interface controller executes the unlock command. When the lock prevents data access, the lock operation is retried a configurable number of times until data access is allowed or a threshold is exceeded.
    Type: Grant
    Filed: June 29, 2015
    Date of Patent: July 4, 2017
    Assignee: MELLANOX TECHNOLOGIES, LTD.
    Inventors: Dror Goldenberg, Liran Liss, Shlomo Raikin
  • Patent number: 9696942
    Abstract: A method for data storage includes configuring a driver program on a host computer to receive commands in accordance with a protocol defined for accessing local storage devices connected to a peripheral component interface bus of the host computer. When the driver program receives, from an application program running on the host computer a storage access command in accordance with the protocol, specifying a storage transaction, a remote direct memory access (RDMA) operation is performed by a network interface controller (NIC) connected to the host computer so as to execute the storage transaction via a network on a remote storage device.
    Type: Grant
    Filed: March 17, 2014
    Date of Patent: July 4, 2017
    Assignee: MELLANOX TECHNOLOGIES, LTD.
    Inventors: Michael Kagan, Noam Bloch, Shlomo Raikin, Yaron Haviv, Idan Burstein
  • Patent number: 9678818
    Abstract: A method for network access of remote memory directly from a local instruction stream using conventional loads and stores. In cases where network IO access (a network phase) cannot overlap a compute phase, a direct network access from the instruction stream greatly decreases latency in CPU processing. The network is treated as yet another memory that can be directly read from, or written to, by the CPU. Network access can be done directly from the instruction stream using regular loads and stores. Example scenarios where synchronous network access can be beneficial are SHMEM (symmetric hierarchical memory access) usages (where the program directly reads/writes remote memory), and scenarios where part of system memory (for example DDR) can reside over a network and made accessible by demand to different CPUs.
    Type: Grant
    Filed: January 29, 2015
    Date of Patent: June 13, 2017
    Assignee: MELLANOX TECHNOLOGIES, LTD.
    Inventors: Shlomo Raikin, Noam Bloch, Richard Graham, Ofer Hayut, Michael Kagan, Liran Liss
  • Patent number: 9672019
    Abstract: Systems, apparatuses, and methods for a hardware and software system to automatically decompose a program into multiple parallel threads are described. In some embodiments, the systems and apparatuses execute a method of original code decomposition and/or generated thread execution.
    Type: Grant
    Filed: December 25, 2010
    Date of Patent: June 6, 2017
    Assignee: Intel Corporation
    Inventors: David J. Sager, Ruchira Sasanka, Ron Gabor, Shlomo Raikin, Joseph Nuzman, Leeor Peled, Jason A. Domer, Ho-Seop Kim, Youfeng Wu, Koichi Yamada, Tin-Fook Ngai, Howard H. Chen, Jayaram Bobba, Jeffery J. Cook, Omar M. Shaikh, Suresh Srinivas
  • Patent number: 9648081
    Abstract: A method for memory access is applied in a cluster of computers linked by a network. For a given computer, a respective physical memory range is defined including a local memory range within the local RAM of the given computer and a remote memory range allocated to the given compute within the local RAM of at least one other computer in the cluster, which is accessible via the network using the network interface controllers of the computers. When a memory operation is requested at a given address in the respective physical memory range, the operation is executed on the data in the local RAM of the given computer when the data at the given address are valid in the local memory range. Otherwise the data are fetched from the given address in the remote memory range to the local memory range before executing the operation on the data.
    Type: Grant
    Filed: March 11, 2015
    Date of Patent: May 9, 2017
    Assignee: MELLANOX TECHNOLOGIES, LTD.
    Inventors: Shlomo Raikin, Shachar Raindel, Michael Kagan
  • Patent number: 9632901
    Abstract: A method for data transfer includes receiving in a data transfer operation data to be written by a peripheral device to a specified virtual address in a random access memory (RAM) of a host computer. Upon receiving the data, it is detected that a page that contains the specified virtual address is marked as not present in a page table of the host computer. The peripheral device receives a notification that the page is not present and an estimate of a length of time that will be required to make the page available and selects a mode for handling of the data transfer operation depending upon the estimate.
    Type: Grant
    Filed: September 7, 2015
    Date of Patent: April 25, 2017
    Assignee: MELLANOX TECHNOLOGIES, LTD.
    Inventors: Shlomo Raikin, Shachar Raindel, Noam Bloch, Liran Liss
  • Patent number: 9626333
    Abstract: Methods and apparatus are disclosed using an index array and finite state machine for scatter/gather operations. Embodiment of apparatus may comprise: decode logic to decode scatter/gather instructions and generate micro-operations. An index array holds a set of indices and a corresponding set of mask elements. A finite state machine facilitates the scatter operation. Address generation logic generates an address from an index of the set of indices for at least each of the corresponding mask elements having a first value. Storage is allocated in a buffer for each of the set of addresses being generated. Data elements corresponding to the set of addresses being generated are copied to the buffer. Addresses from the set are accessed to store data elements if a corresponding mask element has said first value and the mask element is changed to a second value responsive to completion of their respective stores.
    Type: Grant
    Filed: June 2, 2012
    Date of Patent: April 18, 2017
    Assignee: Intel Corporation
    Inventors: Zeev Sperber, Robert Valentine, Shlomo Raikin, Stanislav Shwartsman, Gal Ofir, Igor Yanover, Guy Patkin, Levy Ofer
  • Patent number: 9524240
    Abstract: Methods, apparatus and systems for memory access obscuration are provided. A first embodiment provides memory access obscuration in conjunction with deadlock avoidance. Such embodiment utilizes processor features including an instruction to enable monitoring of specified cache lines and an instruction that sets a status bit responsive to any foreign access (e.g., write or eviction due to a read) to the specified lines. A second embodiment provides memory access obscuration in conjunction with deadlock detection. Such embodiment utilizes the monitoring feature, as well as handler registration. A user-level handler may be asynchronously invoked responsive to a foreign write to any of the specified lines. Invocation of the handler more frequently than expected indicates that a deadlock may have been encountered. In such case, a deadlock policy may be enforced. Other embodiments are also described and claimed.
    Type: Grant
    Filed: March 1, 2013
    Date of Patent: December 20, 2016
    Assignee: Intel Corporation
    Inventors: Shay Gueron, Gad Sheaffer, Shlomo Raikin
  • Publication number: 20160342547
    Abstract: Peripheral apparatus for use with a host computer includes an add-on device, which includes a first network port coupled to one end of a packet communication link and add-on logic, which is configured to receive and transmit packets containing data over the packet communication link and to perform computational operations on the data. A network interface controller (NIC) includes a host bus interface, configured for connection to the host bus of the host computer and a second network port, coupled to the other end of the packet communication link. Packet processing logic in the NIC is coupled between the host bus interface and the second network port, and is configured to translate between the packets transmitted and received over the packet communication link and transactions executed on the host bus so as to provide access between the add-on device and the resources of the host computer.
    Type: Application
    Filed: May 14, 2016
    Publication date: November 24, 2016
    Inventors: Liran Liss, Shachar Raindel, Shlomo Raikin, Adi Menachem, Yuval Itkin
  • Publication number: 20160330301
    Abstract: Data processing apparatus includes a host processor and a network interface controller (NIC), which is configured to couple the host processor to a packet data network. A memory holds a flow state table containing context information with respect to computational operations to be performed on multiple packet flows conveyed between the host processor and the network. Acceleration logic is coupled to perform the computational operations on payloads of packets in the multiple packet flows using the context information in the flow state table.
    Type: Application
    Filed: May 4, 2016
    Publication date: November 10, 2016
    Inventors: Shachar Raindel, Shlomo Raikin, Liran Liss
  • Publication number: 20160330112
    Abstract: A data processing device includes a first packet communication interface for communication with at least one host processor via a network interface controller (NIC) and a second packet communication interface for communication with a packet data network. A memory holds a flow state table containing context information with respect to multiple packet flows conveyed between the host processor and the network via the first and second interfaces packet communication interfaces. Acceleration logic, coupled between the first and second packet communication interfaces, performs computational operations on payloads of packets in the multiple packet flows using the context information in the flow state table.
    Type: Application
    Filed: May 4, 2016
    Publication date: November 10, 2016
    Inventors: Shachar Raindel, Shlomo Raikin, Liran Liss
  • Patent number: 9424198
    Abstract: A processor includes at least one execution unit, a near memory, and memory management logic to manage the near memory and a far memory external to the processor as a unified exclusive memory. Each of a plurality of data blocks may be exclusively stored in either the far memory or the near memory. The unified exclusive memory space may be divided into a plurality of sets and a plurality of ways. In response to a request for a first block stored in the far memory, the memory management logic may move the first block from the far memory to the near memory, and may move a second block from the near memory to the far memory. A tag buffer may store tags associated with blocks being moved between the near memory and the far memory. Fill and drain buffers may also be used. Other implementations are described and claimed.
    Type: Grant
    Filed: November 30, 2012
    Date of Patent: August 23, 2016
    Assignee: Intel Corporation
    Inventors: Shlomo Raikin, Zvika Greenfield
  • Patent number: 9411728
    Abstract: In accordance with embodiments disclosed herein, there are provided methods, systems, mechanisms, techniques, and apparatuses for implementing efficient communication between caches in hierarchical caching design. For example, in one embodiment, such means may include an integrated circuit having a data bus; a lower level cache communicably interfaced with the data bus; a higher level cache communicably interfaced with the data bus; one or more data buffers and one or more dataless buffers. The data buffers in such an embodiment being communicably interfaced with the data bus, and each of the one or more data buffers having a buffer memory to buffer a full cache line, one or more control bits to indicate state of the respective data buffer, and an address associated with the full cache line.
    Type: Grant
    Filed: December 23, 2011
    Date of Patent: August 9, 2016
    Assignee: Intel Corporation
    Inventors: Ron Shalev, Yiftach Gilad, Shlomo Raikin, Igor Yanover, Stanislav Shwartsman, Raanan Sade
  • Patent number: 9405545
    Abstract: In accordance with embodiments disclosed herein, there are provided methods, systems, mechanisms, techniques, and apparatuses for cutting senior store latency using store prefetching. For example, in one embodiment, such means may include an integrated circuit or an out of order processor means that processes out of order instructions and enforces in-order requirements for a cache. Such an integrated circuit or out of order processor means further includes means for receiving a store instruction; means for performing address generation and translation for the store instruction to calculate a physical address of the memory to be accessed by the store instruction; and means for executing a pre-fetch for a cache line based on the store instruction and the calculated physical address before the store instruction retires.
    Type: Grant
    Filed: December 30, 2011
    Date of Patent: August 2, 2016
    Assignee: Intel Corporation
    Inventors: Stanislav Shwartsman, Melih Ozgul, Sebastien Hily, Shlomo Raikin, Raanan Sade, Ron Shalev
  • Publication number: 20160170900
    Abstract: Embodiments of apparatuses and methods including virtual address memory range registers are disclosed. In one embodiment, a processor includes a memory interface, address translation hardware, and virtual memory address comparison hardware. The memory interface is to access a system memory using a physical memory address. The address translation hardware is to support translation of a virtual memory address to the physical memory address. The virtual memory address is used by software to access a virtual memory location in the virtual memory address space of the processor. The virtual memory address comparison hardware is to determine whether the virtual memory address is within a virtual memory address range.
    Type: Application
    Filed: February 19, 2016
    Publication date: June 16, 2016
    Applicant: Intel Corporation
    Inventors: Gur Hildesheim, Shlomo Raikin, Ittai Anati, Gideon Gerzon, Uday Savagaonkar, Francis Mckeen, Carlos Rozas, Michael Goldsmith, Prashant Dewan
  • Patent number: 9348766
    Abstract: In accordance with embodiments disclosed herein, there are provided methods, systems, mechanisms, techniques, and apparatuses for implementing a balanced P-LRU tree for a “multiple of 3” number of ways cache. For example, in one embodiment, such means may include an integrated circuit having a cache and a plurality of ways. In such an embodiment the plurality of ways include a quantity that is a multiple of three and not a power of two, and further in which the plurality of ways are organized into a plurality of pairs. In such an embodiment, means further include a single bit for each of the plurality of pairs, in which each single bit is to operate as an intermediate level decision node representing the associated pair of ways and a root level decision node having exactly two individual bits to point to one of the single bits to operate as the intermediate level decision nodes representing an associated pair of ways.
    Type: Grant
    Filed: December 21, 2011
    Date of Patent: May 24, 2016
    Assignee: Intel Corporation
    Inventors: Adi Basel, Gur Hildesheim, Shlomo Raikin, Robert Chappell, Ho-Seop Kim, Rohit Bhatia