Abstract: A method for processing data includes receiving in a peripheral device, which is connected by a bus to a host processor having host resources, a notification of a sleep state of at least one of the host resources. While the at least one of the host resources is in the sleep state, when the peripheral device receives data from a data source for delivery to the host processor, the peripheral device sends a message to the data source, which causes the data source to defer conveying further data to the peripheral device until the at least one of the host resources has awakened from the sleep state.

Abstract: A processor is described that includes a plurality of processing cores. The processor includes an interconnection network coupled to each of said processing cores. The processor includes snoop filter logic circuitry coupled to the interconnection network and associated with coherence plane logic circuitry of the processor. The snoop filter logic circuitry contains circuitry to hold information that identifies not only which of the processing cores are caching specific cache lines that are cached by the processing cores, but also, where in respective caches of the processing cores the cache lines are cached.

Abstract: Lock access is managed in a data network having an initiator node and a remote target by issuing a lock command from a first process to the remote target via an initiator network interface controller to establish a lock on a memory location, and prior to receiving a reply to the lock command communicating a data access request to the memory location from the initiator network interface controller. Prior to receiving a reply to the data access request, an unlock command issues from the initiator network interface controller. The target network interface controller determines the lock content, and when permitted by the lock accesses the memory location. After accessing the memory location the target network interface controller executes the unlock command. When the lock prevents data access, the lock operation is retried a configurable number of times until data access is allowed or a threshold is exceeded.

Abstract: A method for processing data includes receiving in a peripheral device, which is connected by a bus to a host processor having multiple host resources, information regarding respective power states of the host resources. The data are selectively directed from the peripheral device to the host resources responsively to the respective power states.

Abstract: A method includes communicating between at least first and second devices over a bus in accordance with a bus address space, including providing direct access over the bus to a local address space of the first device by mapping at least some of the addresses of the local address space to the bus address space. In response to indicating, by the first device or the second device, that the second device requires to access a local address in the local address space that is not currently mapped to the bus address space, the local address is mapped to the bus address space, and the local address is accessed directly, by the second device, using the mapping.

Abstract: An apparatus and method for managing a protection table by a processor. For example, a processor according to one embodiment of the invention comprises: protection table management logic to manage a protection table, the protection table having an entry for each protected page or each group of protected pages in memory; wherein the protection table management logic prevents direct access to the protection table by user application program code and operating system program code but permits direct access by the processor.

Abstract: A method for memory access is applied in a cluster of computers linked by a network. For a given computer, a respective physical memory range is defined including a local memory range within the local RAM of the given computer and a remote memory range allocated to the given compute within the local RAM of at least one other computer in the cluster, which is accessible via the network using the network interface controllers of the computers. When a memory operation is requested at a given address in the respective physical memory range, the operation is executed on the data in the local RAM of the given computer when the data at the given address are valid in the local memory range. Otherwise the data are fetched from the given address in the remote memory range to the local memory range before executing the operation on the data.

Abstract: A network interface device includes a host interface for connection to a host processor and a network interface, which is configured to transmit and receive data packets over a network, and which comprises multiple distinct physical ports configured for connection to the network. Processing circuitry is configured to receive, via one of the physical ports, a data packet from the network and to decide, responsively to a destination identifier in the packet, whether to deliver a payload of the data packet to the host processor via the host interface or to forward the data packet to the network via another one of the physical ports.

Abstract: Remote transactions using transactional memory are carried out over a data network between an initiator host and a remote target. The transaction comprises a plurality of input-output (IO) operations between an initiator network interface controller and a target network interface controller. The IO operations are controlled by the initiator network interface controller and the target network interface controller to cause the first process to perform accesses to the memory location atomically.

Abstract: A data storage system includes a storage server, including non-volatile memory (NVM) and a server network interface controller (NIC), which couples the storage server to a network. A host computer includes a host central processing unit (CPU), a host memory and a host NIC, which couples the host computer to the network. The host computer runs a driver program that is configured to receive, from processes running on the host computer, commands in accordance with a protocol defined for accessing local storage devices connected to a peripheral component interface bus of the host computer, and upon receiving a storage access command in accordance with the protocol, to initiate a remote direct memory access (RDMA) operation to be performed by the host and server NICs so as to execute on the storage server, via the network, a storage transaction specified by the command.

Abstract: A method for data storage includes configuring a driver program on a host computer to receive commands in accordance with a protocol defined for accessing local storage devices connected to a peripheral component interface bus of the host computer. When the driver program receives, from an application program running on the host computer a storage access command in accordance with the protocol, specifying a storage transaction, a remote direct memory access (RDMA) operation is performed by a network interface controller (NIC) connected to the host computer so as to execute the storage transaction via a network on a remote storage device.

Abstract: A Network Interface Controller (NIC) includes a network interface, a peer interface and steering logic. The network interface is configured to receive incoming packets from a communication network. The peer interface is configured to communicate with a peer NIC not via the communication network. The steering logic is configured to classify the packets received over the network interface into first incoming packets that are destined to a local Central Processing Unit (CPU) served by the NIC, and second incoming packets that are destined to a remote CPU served by the peer NIC, to forward the first incoming packets to the local CPU, and to forward the second incoming packets to the peer NIC over the peer interface not via the communication network.

Abstract: A method for network access of remote memory directly from a local instruction stream using conventional loads and stores. In cases where network IO access (a network phase) cannot overlap a compute phase, a direct network access from the instruction stream greatly decreases latency in CPU processing. The network is treated as yet another memory that can be directly read from, or written to, by the CPU. Network access can be done directly from the instruction stream using regular loads and stores. Example scenarios where synchronous network access can be beneficial are SHMEM (symmetric hierarchical memory access) usages (where the program directly reads/writes remote memory), and scenarios where part of system memory (for example DDR) can reside over a network and made accessible by demand to different CPUs.

Abstract: The technologies provided herein relate to protecting the integrity of original code that has been optimized. For example, a processor may perform a fetch operation to obtain specified code from a memory. During execution, the code may be optimized and stored in a portion of the memory. The processor may obtain the optimized code from the portion of the memory. An entry of a first table may be modified to indicate a relationship between the particular code and the optimized code. One or more entries of a second table may be modified to specify the one or more physical memory locations. Each of the one or more entries of the second table may correspond to the entry of the first table. The processor may execute the optimized code when each of the one or more entries of the second table are valid.

Abstract: Methods and apparatus are disclosed using an index array and finite state machine for scatter/gather operations. Embodiment of apparatus may comprise: decode logic to decode scatter/gather instructions and generate micro-operations. An index array holds a set of indices and a corresponding set of mask elements. A finite state machine facilitates the scatter operation. Address generation logic generates an address from an index of the set of indices for at least each of the corresponding mask elements having a first value. Storage is allocated in a buffer for each of the set of addresses being generated. Data elements corresponding to the set of addresses being generated are copied to the buffer. Addresses from the set are accessed to store data elements if a corresponding mask element has said first value and the mask element is changed to a second value responsive to completion of their respective stores.

Abstract: Methods and apparatus are disclosed for using an index array and finite state machine for scatter/gather operations. Embodiment of apparatus may comprise: decode logic to decode a scatter/gather instruction and generate a set of micro-operations, and an index array to hold a set of indices and a corresponding set of mask elements. A finite state machine facilitates the gather operation. Address generation logic generates an address from an index of the set of indices for at least each of the corresponding mask elements having a first value. An address is accessed to load a corresponding data element if the mask element had the first value. The data element is written at an in-register position in a destination vector register according to a respective in-register position the index. Values of corresponding mask elements are changed from the first value to a second value responsive to completion of their respective loads.

Abstract: Hybrid multi-level memory architecture technologies are described. A System on Chip (SOC) includes multiple functional units and a multi-level memory controller (MLMC) coupled to the functional units. The MLMC is coupled to a hybrid multi-level memory architecture including a first-level dynamic random access memory (DRAM) (near memory) that is located on-package of the SOC and a second-level DRAM (far memory) that is located off-package of the SOC. The MLMC presents the first-level DRAM and the second-level DRAM as a contiguous addressable memory space and provides the first-level DRAM to software as additional memory capacity to a memory capacity of the second-level DRAM. The first-level DRAM does not store a copy of contents of the second-level DRAM.

Abstract: Methods and apparatus relating to a hardware move elimination and/or next page prefetching are described. In some embodiments, a logic may provide hardware move eliminations based on stored data. In an embodiment, a next page prefetcher is disclosed. Other embodiments are also described and claimed.

Abstract: The technologies provided herein relate to protecting the integrity of original code that has been optimized. For example, a processor may perform a fetch operation to obtain specified code from a memory. During execution, the code may be optimized and stored in a portion of the memory. The processor may obtain the optimized code from the portion of the memory. An entry of a first table may be modified to indicate a relationship between the particular code and the optimized code. One or more entries of a second table may be modified to specify the one or more physical memory locations. Each of the one or more entries of the second table may correspond to the entry of the first table. The processor may execute the optimized code when each of the one or more entries of the second table are valid.

Abstract: A method and apparatus for metaphysical address space for holding lossy metadata is herein described. An explicit or implicit metadata access operation referencing data address of a data item is encountered. Hardware modifies the data address to a metadata address including a metaphysical extension. The metaphysical extension overlays one or more metaphysical address space(s) on the data address space. A portion of the metadata address including the metaphysical extension is utilized to search a tag array of the cache memory holding the data item. As a result, metadata access operations only hit metadata entries of the cache based on the metadata address extension. However, as the metadata is held within the cache, the metadata potentially competes with data for space within the cache.