Patents by Inventor Shlomo Raikin

Shlomo Raikin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20140006746
    Abstract: Embodiments of apparatuses and methods including virtual address memory range registers are disclosed. In one embodiment, a processor includes a memory interface, address translation hardware, and virtual memory address comparison hardware. The memory interface is to access a system memory using a physical memory address. The address translation hardware is to support translation of a virtual memory address to the physical memory address. The virtual memory address is used by software to access a virtual memory location in the virtual memory address space of the processor. The virtual memory address comparison hardware is to determine whether the virtual memory address is within a virtual memory address range.
    Type: Application
    Filed: June 29, 2012
    Publication date: January 2, 2014
    Inventors: Gur Hildesheim, Shlomo Raikin, Ittai Anati, Gideon Gerzon, Uday Savagaonkar, Francis Mckeen, Carlos Rozas, Michael Goldsmith, Prashant Dewan
  • Publication number: 20130326160
    Abstract: Methods and apparatus are disclosed for using an index array and finite state machine for scatter/gather operations. Embodiment of apparatus may comprise: decode logic to decode a scatter/gather instruction and generate a set of micro-operations, and an index array to hold a set of indices and a corresponding set of mask elements. A finite state machine facilitates the gather operation. Address generation logic generates an address from an index of the set of indices for at least each of the corresponding mask elements having a first value. An address is accessed to load a corresponding data element if the mask element had the first value. The data element is written at an in-register position in a destination vector register according to a respective in-register position the index. Values of corresponding mask elements are changed from the first value to a second value responsive to completion of their respective loads.
    Type: Application
    Filed: June 2, 2012
    Publication date: December 5, 2013
    Inventors: Zeev Sperber, Robert Valentine, Guv Patkin, Stanislav Shwartsman, Shlomo Raikin, Igor Yanover, Gal Ofir
  • Publication number: 20130326145
    Abstract: In accordance with embodiments disclosed herein, there are provided methods, systems, mechanisms, techniques, and apparatuses for implementing efficient communication between caches in hierarchical caching design. For example, in one embodiment, such means may include an integrated circuit having a data bus; a lower level cache communicably interfaced with the data bus; a higher level cache communicably interfaced with the data bus; one or more data buffers and one or more dataless buffers. The data buffers in such an embodiment being communicably interfaced with the data bus, and each of the one or more data buffers having a buffer memory to buffer a full cache line, one or more control bits to indicate state of the respective data buffer, and an address associated with the full cache line.
    Type: Application
    Filed: December 23, 2011
    Publication date: December 5, 2013
    Inventors: Ron Shalev, Yiftach Gilad, Shlomo Raikin, Igor Yanover, Stanislav Shwartsman, Raanan Sade
  • Patent number: 8516577
    Abstract: In one embodiment, the present invention includes a method for identifying a termination sequence for an atomic memory operation executed by a first thread, associating a timer with the first thread, and preventing the first thread from execution of a memory cluster operation after completion of the atomic memory operation until a prevention window has passed. This method may be executed by regulation logic associated with a memory execution unit of a processor, in some embodiments. Other embodiments are described and claimed.
    Type: Grant
    Filed: September 22, 2010
    Date of Patent: August 20, 2013
    Assignee: Intel Corporation
    Inventors: Michael S. Bair, David W. Burns, Robert S. Chappell, Prakash Math, Leslie A. Ong, Pankaj Raghuvanshi, Shlomo Raikin, Raanan Sade, Michael D. Tucknott, Igor Yanover
  • Patent number: 8516201
    Abstract: A method and apparatus for protecting private data from cache attacks. One embodiment includes storing private data in a protected cache line to protect it from cache attacks. A snoop request may be received to the protected cache line. In response to the snoop request, a miss may be transmitted. Other embodiments are also disclosed and claimed.
    Type: Grant
    Filed: December 5, 2007
    Date of Patent: August 20, 2013
    Assignee: Intel Corporation
    Inventors: Shlomo Raikin, Shay Gueron, Gad Sheaffer
  • Publication number: 20130179643
    Abstract: Methods, apparatus and systems for memory access obscuration are provided. A first embodiment provides memory access obscuration in conjunction with deadlock avoidance. Such embodiment utilizes processor features including an instruction to enable monitoring of specified cache lines and an instruction that sets a status bit responsive to any foreign access (e.g., write or eviction due to a read) to the specified lines. A second embodiment provides memory access obscuration in conjunction with deadlock detection. Such embodiment utilizes the monitoring feature, as well as handler registration. A user-level handler may be asynchronously invoked responsive to a foreign write to any of the specified lines. Invocation of the handler more frequently than expected indicates that a deadlock may have been encountered. In such case, a deadlock policy may be enforced. Other embodiments are also described and claimed.
    Type: Application
    Filed: March 1, 2013
    Publication date: July 11, 2013
    Inventors: Shay Gueron, Gad Sheaffer, Shlomo Raikin
  • Patent number: 8407425
    Abstract: Methods, apparatus and systems for memory access obscuration are provided. A first embodiment provides memory access obscuration in conjunction with deadlock avoidance. Such embodiment utilizes processor features including an instruction to enable monitoring of specified cache lines and an instruction that sets a status bit responsive to any foreign access (e.g., write or eviction due to a read) to the specified lines. A second embodiment provides memory access obscuration in conjunction with deadlock detection. Such embodiment utilizes the monitoring feature, as well as handler registration. A user-level handler may be asynchronously invoked responsive to a foreign write to any of the specified lines. Invocation of the handler more frequently than expected indicates that a deadlock may have been encountered. In such case, a deadlock policy may be enforced. Other embodiments are also described and claimed.
    Type: Grant
    Filed: December 28, 2007
    Date of Patent: March 26, 2013
    Assignee: Intel Corporation
    Inventors: Shay Gueron, Gad Sheaffer, Shlomo Raikin
  • Patent number: 8370577
    Abstract: Storing metadata that is disjoint from corresponding data by storing the metadata to the same address as the corresponding data but in a different address space. A metadata store instruction includes a storage address for the metadata. The storage address is the same address as that for data corresponding to the metadata, but the storage address when used for the metadata is implemented in a metadata address space while the storage address, when used for the corresponding data is implemented in a different data address space. As a result of executing the metadata store instruction, the metadata is stored at the storage address. A metadata load instruction includes the storage address for the metadata. As a result of executing the metadata load instruction, the metadata stored at the address is received. Some embodiments may further implement a metadata clear instruction which clears any entries in the metadata address space.
    Type: Grant
    Filed: June 26, 2009
    Date of Patent: February 5, 2013
    Assignee: Microsoft Corporation
    Inventors: Gad Sheaffer, David Callahan, Jan Gray, Ali-Reza Adl-Tabatabai, Shlomo Raikin
  • Patent number: 8347035
    Abstract: A processor may comprise a core area, a control unit, an uncore area. The core area may comprise multiple processing cores and line-fill buffers. A first processing core of the core area may store a first weakly ordered transaction in a first line-fill buffer. The firs processing core may offload the first weakly ordered transaction to the extended buffer space provisioned in the uncore area after receiving a request from the uncore area. The first processing core may then de-allocate the first line-fill buffer after the first weakly ordered transaction is offloaded to the extended buffer space. The uncore may then post the first weakly ordered transaction to a memory or a memory system. The control unit may track the first weakly ordered transaction to ensure that the first weakly ordered transaction is posted to the memory or the system.
    Type: Grant
    Filed: December 18, 2008
    Date of Patent: January 1, 2013
    Assignee: Intel Corporation
    Inventors: Geeyarpuram N. Santhanakrishnan, Julius Mandelblat, Ehud Cohen, Larisa Novakovsky, Zeev Offen, Michelle J. Moravan, Shlomo Raikin, Ron Gabor
  • Patent number: 8341356
    Abstract: Embodiments of the present invention provide a secure programming paradigm, and a protected cache that enable a processor to handle secret/private information while preventing, at the hardware level, malicious applications from accessing this information by circumventing the other protection mechanisms. A protected cache may be used as a building block to enhance the security of applications trying to create, manage and protect secure data. Other embodiments are described and claimed.
    Type: Grant
    Filed: May 3, 2011
    Date of Patent: December 25, 2012
    Assignee: Intel Corporation
    Inventors: Shlomo Raikin, Shay Gueron, Gad Sheaffer
  • Publication number: 20120254542
    Abstract: Apparatuses and methods to perform gather instructions are presented. In one embodiment, an apparatus comprises a gather logic module which includes a gather logic unit to identify locality of data elements in response to a gather instruction. The apparatus includes memory comprising a plurality of memory rows including a memory row associated with the gather instruction. The apparatus further includes memory structure to store data element addresses accessed in response to the gather instruction.
    Type: Application
    Filed: April 1, 2011
    Publication date: October 4, 2012
    Inventors: Shlomo Raikin, Robert Valentine
  • Patent number: 8209689
    Abstract: A method and apparatus for avoiding live-lock during transaction execution is herein described. Counting logic is utilized to track successfully committed transactions for each processing element. When a data conflict is detected between transactions on multiple processing elements, priority is provided to the processing element with the lower counting logic value. Furthermore, if the values are the same, then the processing element with the lower identification value is given priority, i.e. allowed to continue while the other transaction is aborted. To avoid live-lock between processing elements that both have predetermined counting logic values, such as maximum counting values, when one processing element reaches the predetermined counting value all counters are reset. In addition, a failure at maximum value (FMV) counter may be provided to count a number of aborts of a transaction when counting logic is at a maximum value.
    Type: Grant
    Filed: September 12, 2007
    Date of Patent: June 26, 2012
    Assignee: Intel Corporation
    Inventors: Shlomo Raikin, Shay Gueron, Gad Sheaffer
  • Publication number: 20120159079
    Abstract: A method and apparatus for providing a memory model for hardware attributes to support transactional execution is herein described. Upon encountering a load of a hardware attribute, such as a test monitor operation to load a read monitor, write monitor, or buffering attribute, a fault is issued in response to a loss field indicating the hardware attribute has been lost. Furthermore, dependency actions, such as blocking and forwarding, are provided for the attribute access operations based on address dependency and access type dependency. As a result, different scenarios for attribute loss and testing thereof are allowed and restricted in a memory model.
    Type: Application
    Filed: January 26, 2012
    Publication date: June 21, 2012
    Inventors: Gad Sheaffer, Shlomo Raikin, Vadim Bassin, Ehud Cohen, Oleg Margulis
  • Publication number: 20120117334
    Abstract: A method and apparatus for monitoring memory accesses in hardware to support transactional execution is herein described. Attributes are monitor accesses to data items without regard for detection at physical storage structure granularity, but rather ensuring monitoring at least at data items granularity. As an example, attributes are added to state bits of a cache to enable new cache coherency states. Upon a monitored memory access to a data item, which may be selectively determined, coherency states associated with the data item are updated to a monitored state. As a result, invalidating requests to the data item are detected through combination of the request type and the monitored coherency state of the data item.
    Type: Application
    Filed: January 20, 2012
    Publication date: May 10, 2012
    Inventors: Gad Sheaffer, Shlomo Raikin, Vadim Bassin, Raanan Sade, Ehud Cohen, Oleg Margulis
  • Publication number: 20120072984
    Abstract: In one embodiment, the present invention includes a method for identifying a termination sequence for an atomic memory operation executed by a first thread, associating a timer with the first thread, and preventing the first thread from execution of a memory cluster operation after completion of the atomic memory operation until a prevention window has passed. This method may be executed by regulation logic associated with a memory execution unit of a processor, in some embodiments. Other embodiments are described and claimed.
    Type: Application
    Filed: September 22, 2010
    Publication date: March 22, 2012
    Inventors: MICHAEL S. BAIR, David W. Burns, Robert S. Chappell, Prakash Math, Leslie A. Ong, Pankaj Raghuvanshi, Shlomo Raikin, Raanan Sade, Michael D. Tucknott, Igor Yanover
  • Publication number: 20110208918
    Abstract: Methods and apparatus relating to a hardware move elimination and/or next page prefetching are described. In some embodiments, a logic may provide hardware move eliminations based on stored data. In an embodiment, a next page prefetcher is disclosed. Other embodiments are also described and claimed.
    Type: Application
    Filed: December 24, 2010
    Publication date: August 25, 2011
    Inventors: Shlomo Raikin, David J. Sager, Zeev Sperber, Evgeni Krimer, Ori Lempel, Stanislav Shwartsman, Adi Yoaz, Omer Golz
  • Publication number: 20110208907
    Abstract: Embodiments of the present invention provide a secure programming paradigm, and a protected cache that enable a processor to handle secret/private information while preventing, at the hardware level, malicious applications from accessing this information by circumventing the other protection mechanisms. A protected cache may be used as a building block to enhance the security of applications trying to create, manage and protect secure data. Other embodiments are described and claimed.
    Type: Application
    Filed: May 3, 2011
    Publication date: August 25, 2011
    Inventors: Shlomo Raikin, Shay Gueron, Gad Sheaffer
  • Publication number: 20110167416
    Abstract: Systems, apparatuses, and methods for a hardware and software system to automatically decompose a program into multiple parallel threads are described. In some embodiments, the systems and apparatuses execute a method of original code decomposition and/or generated thread execution.
    Type: Application
    Filed: December 25, 2010
    Publication date: July 7, 2011
    Inventors: David J. Sager, Ruchira Sasanka, Ron Gabor, Shlomo Raikin, Joseph Nuzman, Leeor Peled, Jason A. Domer, Ho-Seop Kim, Youfeng Wu, Koichi Yamada, Tin-Fook Ngai, Howard H. Chen, Jayaram Bobba, Jeffery J. Cook, Omar M. Shaikh, Suresh Srinivas
  • Patent number: 7975129
    Abstract: Controlling a reorder buffer (ROB) to selectively perform functional hardware lock disabling (HLD) is described. One apparatus embodiment includes a unit to enable an ROB to selectively disable a lock upon Identifying a lock acquire operation (LAO) associated with a critical section (CS) entry point, a unit to selectively retire the LAO, a unit to cause the ROB to selectively disable the lock, and a unit to snoop a buffer. The apparatus may, based on the snooping, selectively abort a transaction associated with the CS.
    Type: Grant
    Filed: September 18, 2009
    Date of Patent: July 5, 2011
    Assignee: Intel Corporation
    Inventors: Shlomo Raikin, Gad Sheaffer, Doron Orenstlen
  • Patent number: 7958320
    Abstract: Embodiments of the present invention provide a secure programming paradigm, and a protected cache that enable a processor to handle secret/private information while preventing, at the hardware level, malicious applications from accessing this information by circumventing the other protection mechanisms. A protected cache may be used as a building block to enhance the security of applications trying to create, manage and protect secure data. Other embodiments are described and claimed.
    Type: Grant
    Filed: December 3, 2007
    Date of Patent: June 7, 2011
    Assignee: Intel Corporation
    Inventors: Shlomo Raikin, Shay Gueron, Gad Sheaffer